JPH0319012A - Input circuit - Google Patents

Abstract

PURPOSE:To decrease the number of input terminals in comparison with the number of input signals by producing the signals in number smaller than that of switches in accordance with the ON/OFF states of these switches and inputted the produced signals to an A/D conversion part. CONSTITUTION:A switch circuit 2 produces the signals in number smaller than that of switches in accordance with the ON/OFF states of these switches and inputs these signals to an A/D conversion part 1. A recognizing means recognizes the ON/OFF states of switches with the signals received from the circuit 2 via the part 1. That is, the circuit 2 produces the signals in number smaller than that of switches in accordance with the ON/OFF states of these switches and these signals undergo the A/D conversion via the part 1. Then the means 3 recognizes the ON/OFF states of those switches with the signals received from the part 1. As a result, the number of input terminals can be decreased in comparison with the number of input signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input circuit used for setting modes of various devices and inputting data, commands, etc.

[Conventional technology]

Normally, various devices having a microcomputer (CPU) have a plurality of switches for setting a plurality of modes, and a plurality of signals from the plurality of switches are respectively transmitted from a plurality of input ports of the CPU. The mode is set using these signals.

In addition, in various devices having a keyboard and a CP tJ, a plurality of signals from the keyboard are respectively taken in from a plurality of input ports of the CPU and processed.

[Problem to be solved by the invention]

Each of the above-mentioned devices takes in multiple signals from multiple input ports of CI)U, so if the number of the above-mentioned signals increases due to higher functionality, many input ports of the CPU will be required. In some cases, this may not be possible, and an input port expansion circuit for expanding the number of input ports is required outside the CPU.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide an input circuit in which the number of input terminals can be reduced compared to the number of input ports.

[Means to solve the problem]

In order to achieve the above object, the present invention provides an apparatus having an analog/digital converter that performs analog/digital conversion of a signal. a switch circuit 2 that generates a smaller number of signals than the number of switches and inputs them to the analog/digital converter 1;
and recognition means 3 for recognizing the on/off states of the plurality of switches from the signals inputted from the analog/digital converter 1 through the analog/digital converter 1.

[Function J] The switch circuit 2 generates a smaller number of signals than the number of the plurality of switches according to the on/off states of the plurality of switches, and this signal is converted from analog to digital by the analog/digital converter 1. Ru. The recognition hand Pi3 recognizes the on/off states of the plurality of switches from the signal from the analog/digital converter 1.

[Embodiment] Fig. 8 shows a magnetic head in an example of a data backup tape recorder to which the present invention is applied. Two writing sections each having a winding wound around each core having gaps 13a and 13b, and two reading sections each having a winding wound around each core having reading gaps 14a and 14b are integrally provided. There is. The writing part having the writing gap 13a and the reading part having the reading gap 14a arranged in the forward running direction of the magnetic tape combine the writing part and the reading part for one channel, and reduce the backward running hitting force of the magnetic tape. A writing section and a reading gap 1 having writing gaps 13b arranged in the direction
4b constitutes a writing section and a reading section for another channel, and these writing sections and reading sections for two channels are arranged at a predetermined pitch in a direction perpendicular to the running direction of the magnetic tape. It is located. The width of the writing gaps 23a, 13b is 178μ layer, and the width of the reading gaps 14a, 14b is 12μ layers.
The width is 7 μm, which is considerably narrower than the conventional 267 μm width.

In addition, this data backup tape recorder is the 7th tape recorder.
OT (Begin Of Tape) as shown in the figure
, EOT (I End Of Tape), EV (Ear
ly Warning), LP (Load l'oin
A magnetic tape 19 having marks 15 to 18 of t) is used, and other magnetic tapes mentioned above can also be used. Marks 15 to 18 on the magnetic tape 19 indicate the magnetic tape 19.
The holes are arranged parallel to the running direction of the magnetic tape 19 at the center of each of the upper and lower parts that are divided into two in the vertical direction perpendicular to the running direction of the magnetic tape 19. . BOT15. EOTI6 is provided at both ends of the magnetic tape 19, and EW17. LP18 is the center part of the upper part of the magnetic tape 19 and is BOT.
15. It is provided a certain distance inside from the EOT 16.

FIG. 2 shows the circuit configuration of this data backup tape recorder.

A reading gap 14a in the magnetic head 11.

The read signal from the reading section 33 having the 14b is amplified by the amplifier 34, and the envelope is detected by the envelope circuit 35.
U) 36 analog/digital (A/D) converter 37
is input. Further, the read signal from the amplifier 34 is frequency-divided by a frequency divider circuit 53, and the CPU 3 (i) counts the read signal from the frequency divider circuit 53 by a counter 54 to determine its frequency. detects the holes 15 to 18 and sends the detection signal to the CPU 3.
)・The rack designation circuit 39 sends a rack signal to the CPU 3 indicating the track designated by the operator.
Enter 6. Lay 1 to circuit 40 are an erasing unit having an erasing gap 12 according to a control signal from the CPU 36, @
Writing section 4 having writing gaps 13a and 13b
1 is selectively driven. The stepper 42 is the magnetic head 11
The drive circuit 43 drives the stepper 42 in response to a control signal from the CPU 36. The motor 44 is a drive circuit 45
The drive circuit 45 drives the motor 44 in response to a control signal from C1) U36.
to drive. This drive circuit 45 has a tacho generator that detects the rotation of the motor 44, and outputs pulses from the tacho generator to the CPU 36.

During the data write operation, the CPU 36 causes the drive circuit 45 to drive the motor 44 to run the magnetic tape 19 in the right direction, and the write gap 13 of the lower channel of the magnetic head 11 is moved through the write circuit 40.
A writing part having a is operated to write a reference signal of a specific frequency f0 into a reference signal area 20 from inside the BOT 15 at the center of the upper part of the magnetic tape 19, and then data is written into the data area 10. Next, the CPU 36 causes the magnetic tape I9 to travel leftward, operates the writing unit having the writing gap 13b in the upper channel of the magnetic head 11, and writes the reference information inside the central BOT 15 on the right side of the lower part of the magnetic tape 19. After a reference signal of a specific frequency f0 is written in the signal area 21, data is written in the data area tl. Next, the CPU 36 uses the magnetic tape 19.
A reference signal of a specific frequency f1 is sent to the reference signal area 22 in the upper part of the magnetic tape 19 inside the BOT 15 in the upper part of the magnetic tape 19 by running it in the right direction and using the write part having the writing gap 13a in the lower channel of the magnetic head H. After that, data is written in the data area t2, and the magnetic tape 19 is run to the left to operate the writing section having the writing gap 13b in the upper channel of the magnetic head 11, thereby writing the BOT 15 in the lower part of the magnetic tape 19. After a reference signal of a specific frequency f is written in the inner reference signals h9.23, data is written in the data area t3.

Similarly, the CPU 36 moves the magnetic tape 19 to the right.

While running the magnetic head alternately in the left direction, reference signal areas 24, 25, . . . 31 and data area t4. t5. . . . A reference signal and data of a specific frequency f are written in the tll, and the magnetic head 11 is used to write the upper and lower parts of the magnetic tape 19 while running the magnetic tape 19 alternately in the right and left directions. Each data area t12. t13. . . . data is written in t24, and finally the magnetic tape 19 is run rightward to write the reference signal and data of the specific frequency f1 in the reference signal area 32 and data area t25.

Further, during a data reading operation, the CPU 36 causes the drive circuit 43 to drive the stepper 42 to move the magnetic head II in a direction perpendicular to the running direction of the magnetic tape 19 to locate the target track in which the data to be read is written. Seek and read gap 14a or 1 in magnetic head 11 from the data area of this target track.
The data is read by a reading unit having a 4b, and the read signal is taken in via an amplifier 34 and an envelope circuit 35, and is A/D converted by an A/D converter 37 and processed. In this case, if the target track is on the lower part of the magnetic tape 19, the magnetic tape 19 is moved to the right and data is read by the reading section having the reading gap 14a, so that the target track is on the upper part of the magnetic tape 19. If so, the magnetic tape 19 is moved to the left to cause the reading section having the reading gap 14b to read data. In addition, the CPU 36 measures the optimum write current value of the write unit 41 in the E'PROM write mode and writes it into the nonvolatile memory 46 made up of E'PRON, and in the normal mode, reads the write current value from this memory 46 and writes it. The write current value of the section 41 is set in the write circuit 40.

Furthermore, in this data backup tape recorder, as shown in FIG. 3, the two unused input terminals ^/DI and A/D2 of the A/D converter 37 are used as mode setting input terminals. input terminal A/Di
, a 10Ω resistor 47 between the A/D2 and the 5V power supply.
, 118 are connected to each other. Between the input terminal A/I) 1 and the ground, there is a series circuit of a resistor 49 of 10 Ω and a reference seek mode setting switch SVI, and a series circuit of a resistor 50 of Ω 18 and a switch SV2 for setting the reference seek frequency check mode. A series circuit is connected in parallel with the input terminal A/D2 and the earth, and a series circuit of a 10Ω resistor 51 and a tape discrimination mode setting switch SW3 is connected to the input terminal A/D2 and the ground, and a series circuit of a 18Ω resistor 52 and an E” PROM. The series circuit of the light mode setting switch 5Td4 is connected in parallel.

Therefore, as shown in FIGS. 4(a) and 4(b), the input terminal A/DI is connected to the reference seek mode setting switch S.
When the WI and reference seek frequency check mode setting switch SW2 are off, the voltage is 5V, and when the reference seek mode setting switch SWI is on and the reference seek frequency check mode setting switch SW2 is off, the voltage is 2.5V. A signal voltage is input. Furthermore, when the reference seek mode setting switch 5till is turned off and the reference seek frequency check mode setting switch SW2 is turned on, a signal voltage of 3.2V is input to the input terminal A/DI, and the reference seek mode setting switch SW2 is turned on. switch 5
When the till and reference seek frequency check mode setting switch SW2 is turned on, a signal voltage of 1.96V is input to the input terminal A/DI. Similarly, the input terminal A/D2 is the tape discrimination mode setting switch SW3.
and E” PRON light mode setting switch SW4
When the switch SW3 for setting the tape discrimination mode is turned on and the switch SW4 for setting the E" PROM write mode is turned off, the voltage becomes 5V.
A signal voltage of 5V is input. When the tape discrimination mode setting switch SW3 is turned off and the E2PROM write mode setting switch SW4 is turned on, 3
．． A signal voltage of 2V is input to the input terminal A/DI, and the tape discrimination mode setting switch 5113 and E"PROM
When the light mode setting switch SW4 is turned on, the voltage (i) of 1.96V is input to the input terminal A/DI.

The CPU 36 converts the signal voltages of the two input terminals A/Di and A/D2 into digital values by the A/D converter 37, and recognizes the mote set by the switches Sli'l to SW4 from this digital value. That is, CI)tJ36
As shown in Figure 5, Nifrag 5WIF, 5Ij2F, 5
Set W3F, SI#/IF and connect input terminal A/D l
The signal voltage is read through the A/I converter 37, and if this signal voltage is 2.23ν or less, the flag 5WIF is set.
, clear 5li12F. In addition, the CPU 36 has a signal voltage of input terminal A/Di that is thicker than 2.23V (2.85V).
If it is less than V, clear flag 5WIF.

If the signal voltage of input terminal A/DI is greater than 2.85V4
．． If it is less than 1V, clear the flag 5Ii12F and leave it as is if the signal 9N voltage of the input terminal A/DI is greater than 4.1V.

Similarly, the CPU 36 changes the signal voltage of the input terminal A/D2 to A/D2.
It is read through the D converter 37, and if the voltage (i) is equal to or higher than 2°2H', flags Sli'3F and 5W4F are cleared. The signal voltage is thicker than 2.2:3V 2.8
If it is less than 5V, flag 5Ij3F is cleared and the signal voltage of input terminal A/D2 is higher than 2.85V. 4.1V
If below, clear flag 5W4F and input terminal A/D
2 signal voltage is 4. If it is larger than IV, leave it as is.

Then, as shown in FIG.
When F is set to cellar 1, it is recognized that the reference seek mode setting switch SWI is turned on, the reference seek mode is determined, and a seek in the reference signal area (reference seek) is performed.

Further, when the flag 5W2F is set, the CPU 36 recognizes that the reference seek frequency check mode setting switch SW2 is turned on, determines that the mode is the reference seek frequency check mode, and performs a frequency check of the reference signal read from the reference signal area. . Next, when the flag 5W3F is set, the CPU 36 recognizes that the tape discrimination mode setting switch 5113 is turned on, determines the tape discrimination mode, and discriminates the type of magnetic tape I9. Furthermore, the CPU 36 executes E2PR when the flag S1&'4F is set.
Recognizes that the OM write mode setting switch 5li14 is turned on and selects [i21' ROM write mode].
E2 by measuring the optimum current value of the writing section 41.
Write I) into PROM46.

In addition, in the example of "double series", four modes were set with switches SWI to SW4, but 16 modes were set with switches 5lll-5Ij4.
It is also possible to set more modes by changing the external circuit of the A/I converter 37. Furthermore, the present invention can be similarly applied to the case where a plurality of signals from a switch circuit such as a keyboard are input to the CPU via an A/D converter.
The A/D converter may be separate from the CI) TJ.

〔Effect of the invention〕

According to the present invention, as shown in E-E, in a device having an analog/digital converter that performs analog/digital conversion of a signal, the number of switches is smaller than the number of the plurality of switches depending on the on/off state of the plurality of switches. a switch circuit that generates a signal and inputs it to the analog/digital converter; and a signal input from the switch circuit through the analog/digital converter to recognize the on/off states of the plurality of switches. Since the present invention is provided with a recognition means for recognizing input terminals, the number of input terminals can be reduced compared to the number of input signals, and the number of circuits for extending the input terminals can be reduced or eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the present invention, FIG. 2 is a block diagram showing the circuit configuration of an example of a data backup tape recorder to which the present invention is applied, and FIG. 3 is a circuit diagram showing a part of the tape recorder. Figures 4(a) and 6(b) are diagrams showing the relationship between the input voltage of the A/D converter and the state of the mode setting switch in the same tape recorder, and Figures 5 and 6 are diagrams showing the relationship between the input voltage of the A/D converter and the state of the mode setting switch in the same tape recorder. FIG. 7 is a plan view showing an example of a magnetic tape, and FIG. 8 is a front view showing an example of a magnetic head. l...Analog/digital conversion unit, 2...Switch circuit, 3...Recognition means. A l form Z lower y F) δ mouth v) 40 ra) (i) form l 1/q ) 6 Fig.

Claims (1)

[Claims] In a device having an analog/digital converter that performs analog/digital conversion of a signal, the analog/digital conversion is performed by generating fewer signals than the number of the plurality of switches according to the on/off states of the plurality of switches. and a recognition means for recognizing the on/off states of the plurality of switches from a signal input from the switch circuit via the analog/digital converter. input circuit.