JPH03187511A - Active filter circuit and control circuit for the same - Google Patents

Abstract

PURPOSE:To reduce the distortion of a signal and to obtain a satisfactory filter characteristic by always operating first and second differential pairs near the center of the linear area of each differential pair. CONSTITUTION:When the voltage V5 of a terminal 24 is increased, the collector current of a transistor Q22 is decreased and the current of a transistor Q24 is increased only for the decreased part. Then, an output voltage V3 is increased. When the voltage V3 is increased, the collector current of a transistor Q12 is decreased and the current of a transistor Q14 is increased only for the decreased part. The voltage V2 of a terminal 20 is increased and the collector currents of the transistors Q12 and Q22 are suppressed to be decreased. Then, the operations of first and second differential pairs 12 and 14 are made stable. Therefore, the first and second differential pairs 12 and 14 are respectively operated near the center of each linear area at all times. Thus, the distortion of the signal is reduced and the satisfactory filter characteristic can be obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an active filter circuit.

More specifically, the present invention relates to an active filter circuit suitable for IC implementation.

[Prior art]

When attempting to incorporate a filter into an integrated circuit (RC), variations in filter characteristics occur due to variations in elements within the IC. Conventionally, in order to compensate for this variation, one method is to provide a dummy reference filter within the IC, input a reference signal into it, and perform feedback control so that the value of the output from the reference filter becomes a desired value. There was a way to apply it. This method is based on the idea that the controlled filter has a resistance or capacitance that is the same as or correlated with the reference filter, and when the same or correlated control signal is applied, the controlled filter is adjusted to have the same or correlated characteristics as the reference filter. This is a method of controlling other controlled filters within an IC using one or more reference filters and a reference signal.

The conventional example shown in FIG. 22 is an example in which the cutoff frequency rc of a low-pass filter is automatically controlled. First, a reference signal with a constant frequency Fref is input to the reference filter, and the level of the signal obtained by amplifying its output is compared with the output level of the reference frequency signal oscillator, and the control voltage V
c is output and applied to the variable capacitance diode Cv to change the filter characteristics. With this feedback control, when the attenuation amount at the reference frequency of the filter becomes equal to the gain of the amplifier, both levels become equal and the filter is in an adjusted state.

[Problem to be solved by the invention]

In the conventional method shown in FIG. 22, it is not necessary to apply an external signal to adjust the filter built into the IC, but since a reference filter of ξ- is provided within the IC, the IC
Not only does the number of elements increase, but an additional reference signal oscillator is also required.

An example of a filter circuit suitable for IC implementation is the Patent Publication No. 61, whose application was published on November 29, 1986 (Showa 61).
It is disclosed in the publication No.-55806.

In the filter circuit disclosed in Japanese Patent Publication No. 61-55806, it is necessary to add a subtracter, etc. to realize a bypass filter circuit, which not only increases the number of circuit elements but also complicates the circuit configuration. There was a problem with that.

Another object of the present invention is to provide an active filter circuit that has a simple configuration and is suitable for integration into an IC.

Another object of the present invention is to provide various circuits using such a novel active filter circuit.

[Means to solve the problem]

The first invention provides a first differential pair including first and second transistors, a first capacitive load connected to the output terminal of the second transistor of the first differential pair, a first negative feedback path for negatively feeding back the output of the second transistor to the input of the second transistor; a second differential pair including a third and fourth transistor; a second capacitive load connected to the output terminal of the fourth transistor of the dynamic pair; and a second capacitive load for negative feedback of the output of the fourth transistor to the input of the first transistor constituting the first differential pair. The active filter circuit includes a second negative feedback path.

The second invention provides a first differential pair including first and second transistors, a first capacitive load connected to the output of the second transistor of the first differential pair, and a first capacitive load connected to the output of the second transistor of the first differential pair. a second differential pair comprising third and fourth transistors;
a connection path for connecting the output of the second transistor of the first differential pair to the input of the fourth transistor of the second differential pair, a second capacitive connected to the output of the fourth transistor; The filter circuit includes a load and a negative feedback path for negatively feeding the output of the fourth transistor to the input of the first transistor constituting the first differential pair.

[Effect]

In the first invention, by the first and second negative feedback paths,
Both the first and second differential pairs now operate near the center of the direct'IA region, and the first and second differential pairs cooperate to act as a second-order active filter circuit.

In the second invention, the first
and the second differential pair each operate near the center of the 1IsN region, so the first and second differential pairs cooperate to act as a second-order active filter circuit.

〔Effect of the invention〕

According to this invention, since no additional circuit such as a subtracter is required, IC
It is possible to obtain an active filter circuit suitable for

According to the present invention, since different types of filters can be constructed using circuits having the same configuration, the respective filters have a strong correlation with each other, and therefore adjustment thereof can be performed very easily.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

〔Example〕

Before explaining a specific active filter circuit according to the present invention, a differential pair consisting of a pair of transistors used in such an active filter circuit will be explained. As shown in FIG. 2A, in the differential pair 1 consisting of transistors Ql and Q2, the collector voltage 0 of the transistor Q2 is calculated by the following equation (where RL is the load resistance).
1).

VO=gm・RL・(V3-V2)
...(1) However, gm is mutual conductance. The charge of the electron is q, the Boltzmann constant is k, and the current is t.
i, and the absolute temperature is T, the relationship expressed by the following equation (2) holds true.

4kT ′t) [1 Also, transistors Ql and Q2 forming differential pair 1
The ivy resistance, that is, the differential resistance re, is given by the following equation (3).

Therefore, the above equation (1) can be transformed as shown in the following equation (4).

Next, as shown in FIG. 2B, a constant current source with a current amount of 11 is connected in place of the load resistor RL, and a cork of the transistor Q2 is connected. When a capacitor C that acts as a capacitive load is connected in the evening, the impedance of the constant current source is assumed to be infinite, and the impedance 1/jωC due to the capacitor C corresponds to the load resistance RL, so equation (4) becomes the following equation. (5) can be modified.

Here, as shown in FIG. 2B, if a power source whose output voltage is Vl is further connected between the capacitor C and the ground, the following equation (6) is obtained.

Next, as shown in Fig. 2C, if an emitter follower is configured using the transistor Q3, the input terminal and output voltage of the emitter follower are equal, so the transistor Q
The output voltage of 3 is also given by the following equation (7).

In differential pair 1 of FIG. 2C, transistor Q1
The base input of the transistor Q2 serves as the tenth input, and the base input of the transistor Q2 serves as the one input, and the output voltage is taken out from the collector of the transistor Q2. Therefore, the second
In the example shown in Figure C, the output voltage VO is fed back to one input through the emitter follower Q3.

Referring to FIG. 1, the active filter circuit 10 of this embodiment includes the differential pair l shown in FIGS. 2A to 2C.
Two differential pairs 12 and 14 having a similar configuration are used.

10 inputs of the first differential pair 12 (transistor Q in Figure 2C)
The output voltage V3 of the second differential pair 14 is applied to the - input (corresponding to the base input of the transistor Q2 in FIG. 2C) of the first differential pair 12.
The output voltage ■2 is fed back. Voltages V1 and V4 are applied to capacitive loads or capacitors C1 and C2 of differential pairs 12 and 14, respectively. A voltage ■5 is applied to the 10 input (corresponding to the base input of transistor Q1 in FIG. 2B) of the second differential pair 14, and the voltage 5 is applied to the − input (corresponding to the base input of transistor Q2 in FIG. 2B). The output voltage (2) of the first differential pair 12 is fed back.

Specifically, the active filter circuit 10 of FIG.
It is shown in FIG. Referring to FIG. 3, active filter circuit 10 includes first and second transistors Qll
and a first differential pair 12 including Q12;
and a second differential pair 14 including third and fourth transistors Q21 and Q22.

The emitters of transistors Q11 and Q12 constituting the first differential pair 12 are connected to the transistor Q constituting a constant current source.
13 in common, and a power supply voltage (10 B) from a terminal 16 is supplied to the collector of the transistor Qll. The collector of transistor Q12 is connected to a constant current source, that is, the collector of transistor Q15, and is also connected to the base of transistor Q14, which constitutes an emitter follower of the first differential pair 12, through a capacitor CI, which constitutes a capacitive load. and is connected to terminal 18.

The output of the transistor Q24, which constitutes the emitter follower of the second differential pair 14, is connected to the base input of the transistor Qll, which constitutes the ten inputs of the first differential pair 12 in the circuit of FIG. The base input of transistor Q12 is connected to the output or terminal 20 of transistor Q14. Note that the current amount of the constant current source configured by the transistor Q13 is a current amount 211 that is twice the current amount If of the constant current source configured by the transistor Q15.
is set to

The emitters of transistors Q21 and Q22 constituting the second differential pair 14 are commonly connected to a constant current source constituted by a transistor Q23.
3 forms a current mirror circuit together with the transistor Q13. Terminal 16 is connected to the collector of transistor Q21.
A power supply voltage (10 B) is applied from. Transistor Q2
The collector of 2 is connected to a constant current source constituted by a transistor Q25, and is also connected to the base of a transistor Q24 as a follower, and is further connected to a terminal 22 via a capacitive load, a capacitor C2. be done. The base input of the transistor Q22 constituting one input of the second differential pair 14 in the circuit of FIG. The input is connected to terminal 24. Note that, in the same way as the first differential pair 12, in the second differential pair 14, ``transistor Q2
The amount of current of the constant current source composed of transistor Q2 is
Current amount of constant current source consisting of 3 ■ Current amount 2 twice as much as 2
It is set to 12.

Transistors Q16 and Q26 form a pair, and a power supply voltage (10 B) is applied to the collectors of each through a suitable resistor. The collector of transistor Q16 is connected to its own base and to transistor Q17.
connected to a constant current source consisting of Similarly, the collector of transistor Q26 is connected to the base of transistor Q26 and to a constant current source formed by transistor Q27.

Note that the transistors Q13 and Q constituting the constant current source mentioned above
23. Q17 and Q27 together constitute a parallel-connected current mirror circuit, the bases of which are commonly connected to terminal 26. By applying a control voltage Vc to this terminal 26, the amount of current flowing through each transistor is changed, and thus the filter characteristics of this active filter circuit 10 are adjusted or controlled.

Here, terminal 18. The output of transistor Q14, or terminal 20. Output of transistor Q24.

The voltages at terminals 22 and 24 are set to Vl, respectively.

V2. V3. Set as V4 and v5.

When the voltage 5 at the terminal 24 increases, the transistor Q22
The collector current of transistor Q24 decreases, and the current of transistor Q24 increases by the amount of the decrease, so that its output voltage v3 increases. When the voltage V3 rises, the collector current of the transistor Q12 decreases, and the current of the transistor Q14 increases by the amount of the decrease.
voltage v2 increases. When the voltage 2 increases, the decrease in the collector currents of the transistors Q12 and Q22 is suppressed, and the operations of the first and second differential pairs 12 and 14 become stable. Therefore, the first and second differential pairs 12 and 14 always operate near the center of the linear region of the differential pair, resulting in less signal distortion and good filter characteristics.

In the active filter circuit 10 shown in FIG. 3, the current 11 flowing through the transistors Qll and Q12 of the first differential pair 12 is expressed by the following formula, %, and the capacitor C1, where tel is the emitter resistance of the transistor Q12. The signal voltage of is given by the following equation (9).

Based on these equations (8) and (9), the first and second differential pairs 1 of the active filter circuit 10 shown in FIG.
2 and 14, the above-mentioned equation (7) holds true, and therefore, the following equations (10) and (11) are obtained.

2rel jωc, where re2 is the differential resistance or emitter resistance of transistors Q21 and Q22.

From the above equations (10) and (11), as jω=S,
When voltage v3 is eliminated, the following equation (12) is obtained.

= 2tel SCI (V2- Vl) V5-
V2 + 2 re2 S C2 (V4 - V2
) = 4rel re2 S” C2(V2 −
Vl) V5+ 2 re2 5C2V4+ 4 re
l re2 S” CIC2V1=V2+ 2 r
e2 5C2V2+ 4 rel re2 S”
CIC2V2...(12) Here, when terminals 18 and 22 are grounded and a signal is input from terminal 24, V 1 = , V 4 = 0, V5 =
Vin, and the transfer function T(*) of the active filter circuit 10 is given by the following equation (13).

...(13) This indicates a second-order low-pass function. The cutoff frequency ωC is given by the following equation (14), and is given by the following equation (1
5) is given by

In this way, the active filter circuit 10 of FIG.
is implemented as a second-order low-pass filter.

Similarly, when a signal is input to terminal 18 and terminals 22 and 24 are grounded, V1=Vin, V4=V5=0, and the transfer function T (sl) is given by the following equation (16), which is 2 Shows the order high pass function.

The cutoff frequency ωC is given by the following equation (17), and Q is given by the following equation (18).

(16) In this way, the active filter circuit 10 of FIG.
is realized as a second-order bypass filter.

Furthermore, when terminals 18 and 24 are grounded and a signal is input to terminal 22, V1=V5=O1V4=Vin, and a second-order bandpass with center frequencies ω0 and Q shown by the following equations (19) and (20) is obtained. A filter is obtained.

Also, if signals are input to terminals 18 and 24 at the same time and terminal 22 is grounded, V1=V5=Vin, V4=
0, and a second-order band elimination filter having center frequencies ω0 and Q shown in the following equations (21) and (22) is obtained.

Then, when signals are input to terminals 18 and 24 at the same time and a reverse phase signal is input to terminal 22, V1=V5=V i
n, V4= −V i n, and the following equation (23),
A second-order phase shift circuit having the center frequency ωo, Q and phase characteristics shown in (24) and (25) can be realized.

arg T (j (1)) = −2janQ
(ω02−ω2) (25) In this way, according to the embodiment in FIG. 3, different types of second-order filter circuits can be realized with the same circuit configuration, so that
When a plurality of different types of filter circuits are built into C, if the control voltage Vc applied to the terminal 26 is linked with other filter circuits as appropriate, all the filter circuits can be adjusted by adjusting only one control voltage. The filter circuit can be adjusted with almost no variation.

Referring to FIG. 4, the active filter circuit 10' of this embodiment uses differential pairs 12' and 14 at the bottom of the tank similar to the differential pair 1 previously explained in FIGS. 2A to 2C. . 10 inputs of the first differential pair 12' (transistor Q in Figure 2B)
The feedback voltage V1 from the 20th differential pair 14 is applied to the - input (corresponding to the base input of transistor Q2 in Fig. 2B), and the voltage 2 is applied to the - input (corresponding to the base input of transistor Q2 in Fig. 2B). . The capacitive loads or capacitors C1 and C2 of differential pairs 12' and 14, respectively, have a voltage Vl
and V4 are applied. Ten inputs of the second differential pair 14 (
(corresponds to the base input of transistor Q1 in Figure 2B)
A voltage 5 is applied to the - input (corresponding to the input to the transistor Q2 in FIG.
2' output voltage V3 is applied.

The active filter circuit 10' of FIG. 4 is specifically shown in FIG. The active filter circuit 10' shown in FIG. 5 differs from the embodiment shown in FIG. 3 in the following points. That is, in the embodiment shown in FIG. 3, a negative feedback path is formed between the output and input of the transistor Q12 constituting the first differential pair 12. However, in the active filter circuit 10' of this embodiment in FIG. Furthermore, the output of the second differential pair 14 is connected to the terminal 18.However, other points are the same as the embodiment shown in FIG. 3, and further redundant explanation will be omitted here.

Here, the voltages at terminals 1B, 20, 28, 22 and 24 are set to Vl, V2. V3. Set as V4 and v5.

Similar to the embodiment of FIG. 3, when the voltage V5 at the terminal 24 increases, the collector current of the transistor Q22 decreases, the current of the transistor Q24 increases by the amount of the decrease, and therefore the output voltage V1 thereof increases. And the voltage V1
When V increases, the collector current of transistor Q12 decreases, and the current of transistor Q14 increases by the amount of the decrease, so that the voltage V2 at terminal 28 increases. When this voltage V2 increases, transistors Q12 and Q22
The decrease in the collector current of is suppressed, and the operations of the first and second differential pairs 12' and 14 are stabilized. therefore,
The first and second differential pairs 12' and 14 always operate near the center of the linear region of the differential pair, so that signal distortion is small and good filter characteristics are obtained.

In the active filter circuit 10'' shown in FIG.
In connection with the first and second differential pairs 12' and 14,
By converting the previous equation (7) into summer form, we can obtain the following equations (26) and (27).
) is obtained.

From the above equations (26) and (27), as jω=S,
When voltage v3 is eliminated, the following equation (28) is obtained.

= 2re2 5C2 (Vl - V4) V2 - Vl
+ 2rel 5CI (V5 - Vl) = 4r
el re2 S” CIC2 (Vl -V4)V2
+ 2rel 5CIV5+ 4rel re2
S” CIC2V4=V1+ 2rel 5ctvt
+ 4rel re2 S” CIC2V1...(
28) Here, when terminals 22 and 24 are grounded and a signal is input from terminal 20, V4 = V5 = 0, V2 - Vin,
Transfer function T of active filter circuit 10'. ) is given by the following equation (29).

...(29) This indicates a second-order low-pass function, and its cutoff frequency ωC is given by the following equation (30), and Q is given by the following equation (
31) is given by

In this way, the active filter circuit 10 of FIG.
' is realized as a second-order low-pass filter.

Similarly, when a signal is input to terminal 22 and terminals 20 and 24 are grounded, V4=Vin, V2=V5=O, and the transfer functions T and o are given by the following equation (32), which is 2 Shows the order high pass function.

The cutoff frequency ωC is given by the following equation (33), and Q is given by the following equation (34).

(32) In this way, the active filter circuit 10 of FIG.
' is realized as a second-order bypass filter.

When terminals 20 and 22 are grounded and a signal is input to terminal 24, V2=V4-0. V5=Vin, and the following formula (35
) and (36) with center frequencies ω0 and Q are obtained.

Also, by inputting signals to terminals 20 and 22 at the same time and grounding terminal 24, V2=V4=Vin, V5=
0, and a second-order band elimination filter having center frequencies ω0 and Q shown in the following equations (37) and (38) is obtained.

Then, when signals are simultaneously input to terminals 20 and 22 and a reverse phase signal is input to terminal 24, V2=V4=Vin,
V5--Vln, and it is possible to realize a second-order phase shift circuit having the center frequency ωo, Q, and phase characteristics shown in the following equations (39), (40), and (41).

...(41) In this way, according to the embodiment in FIG. 5, different types of second-order filter circuits can be realized with the same circuit configuration, so that
When a plurality of different types of filter circuits are built in C, if the control voltage Vc applied to the terminal 26 is linked with other filter circuits as appropriate, all the filter circuits can be adjusted by adjusting only one control voltage. It can be adjusted without any variation.

The active filter circuit 10 shown in FIG. 6 is a modification of the embodiment of FIG. 3, and is similar to the embodiment of FIG. 3 except for the following points. That is, the base of the above-mentioned transistor Q12 constituting the first differential pair 12 is connected to the emitter of the emitter follower transistor Q14 via a resistor R1, and is also connected to the bias power supply 3 via a resistor R2.
Connected to 0. The output of transistor Q12 or transistor Q14 is thus fed back to the base or input of transistor Q12 via resistor R1. Further, the transistor Ql constituting the first differential pair 12
The base of l is connected via a resistor R3 to the output of a transistor Q22 constituting the second differential pair 14, that is, the output of an emitter follower transistor Q24, and is connected to the bias power supply 30 via a resistor R4. connected to.

In the active filter circuit IO shown in FIG.
) is transformed to obtain the following equations (42) and (43).

However, K is a constant (described later).

From the above equations (42) and (43), as jω=S,
When voltage v3 is eliminated, the following equation (44) is obtained.

= 2tel SCI (V2- Vl)V5-
V2+ 2re2 5C2 (V4 - V2) 4t
el e2 3g CIC2 (V2 Vl) 5 + 2 re2 SC2V4= 2 + 2 re2 C2V2 +-4tel e2 3g IC2V2 Here, when terminals 18 and 22 are grounded and a signal is input from terminal 2 4, V1=V2=O1V5= Vin
Therefore, the transfer function T(, , ) of the active filter circuit 10 shown in FIG. 6 is given by the following equation (45).

...(45) This indicates a second-order low-pass function, and its cutoff frequency ωC is given by the following equation (46), and Q is given by the following equation (
47).

In this way, the active filter circuit 10 of FIG.
is realized as a second-order low-pass filter.

Similarly, when a signal is input to terminal 18 and terminals 22 and 24 are grounded, Vl=Vin, V4=V5=0, and the transfer function T (s) is given by the following equation (48), which is The second-order high-pass function is shown.

The cutoff frequency ωC is given by the following equation (49), and Q is given by the following equation (50).

(48) In this way, the active filter circuit 10 shown in FIG. 6 is realized as a second-order bypass filter.

When terminals 18 and 24 are grounded and a signal is input to terminal 22, V1=V5=0, V4=V i n, and a quadratic signal with center frequencies ω0 and Q shown by the following equations (51) and (52) A bandpass filter is obtained.

Also, if signals are input to terminals 18 and 24 at the same time and terminal 22 is grounded, V1=V5=Vin, ■4=
0, and a second-order band elimination filter having center frequencies ω0 and Q shown in the following equations (53) and (54) is obtained.

Then, when signals are simultaneously input to terminals 18 and 24 and a reverse phase signal is input to terminal 22, V1=V5=Vin,
V4=-Vin, and it is possible to realize a second-order phase shift circuit having the center frequency ωo, Q, and phase characteristics shown by the following equations (55), (56), and (57).

arg T(jω) =-2tan-'Q(ω08
-ω2 ) ...(57) In this way, according to the embodiment in FIG. 6, the transistor Qll
By appropriately setting the constant K of the base bias resistors R1 to R4 of Q12, each of the above-mentioned filter characteristics can be changed, and the filter characteristics can also be adjusted by the control /a voltage Vc applied to the terminal 26.

The embodiment shown in FIG. 7 is a modification of the embodiment shown in FIG.
The active filter circuit IO of the embodiment shown in FIG. 6 differs from the embodiment shown in FIG. 6 in the following points. That is, in the embodiment shown in FIG.
The base of the transistor Q12 constituting the differential pair 12 is connected to the emitter of the transistor Q14 via a resistor R1, and is also connected to the bias power supply 30 via a resistor R2.
The base of the transistor Qll, which was connected to the transistor Qll and which constitutes the first differential pair 12, was connected to the emitter of the transistor Q24 via a resistor R3, and also to the bias power supply 30 via a resistor R4. however,
In the active filter circuit 10 of the embodiment shown in FIG.
and the base of transistor Q12 are connected to resistor R1, respectively.
1 and R13 through transistors Q14 and Q2
4 and interconnected via a resistor R12, and has no bias power supply.

In the embodiment of FIG. 6, transistors Qll and Q1
The current 11 flowing through 2 is exactly the following formula (58) % Formula % (3 R4) = 2 If the ratio of the resistors in the IC is 2, the error will be 2% even if they are placed close to each other. There is, K1
The relative ratio of and to 2 will have an error of 4%.

On the other hand, in the embodiment of FIG. 7, when the respective base voltages of transistors Q11 and Q12 are v11 and Vl2, Vll and v12 are given by the following equations (59) and (60), respectively.

In Figure 7, Transistor Q1 1 and Q ■ Current flowing through 2■ ' is the same as 11 in Figure 6. Similarly, it is given by the following equation (61).

(R11+R12)V3+R13V2 (R13+R12) V2 11V3 (R11+R13 + R12)・re1 rel...(61) As is clear from equation (61), the coefficients of voltages v3 and V2 are equal, and the influence of the error in the resistance ratio is It is not affected at all and does not require a bias power supply, by the way, R11 = R1, R1
When 3=R3, R12=R2+R4, K in Figure 6
is equal to

The embodiment in FIG. 8 is a modification of the embodiment in FIG. Different from the example. However, transistor Q28 constitutes an emitter follower.

In the active filter circuit lO shown in FIG.
11 flowing through 12 is connected to transistors Qll and Q12.
When the emitter resistance of is tel, it is given by the following equation (62).

However, Kl and 2 are constants (described later).

The signal voltage of the capacitor C1 C1 is expressed by the following formula (63)% Formula % From the above formulas (62) and (63), the following formula (64) is obtained.Similarly, in relation to the second differential pair 14, The following formula (65) % Formula % From the above formulas (65) and (66), by setting jω=S and eliminating the voltage v3, the following formula (66> is obtained).

= 2 tel SCI (V2-Vl) 4 to K2
V5 Juni 2 ・2re25C2V4 Ju4 rel re
2 S ” CIC2V1=2 K3V20K 1
・2re25C2V2+ 4 rel re2 S
” CIC2V2...(66) Here, if signals are input to terminals 18 and 20 at the same time and terminal 22 is grounded, vi = v5 - Vin, V
4=0, and lO of the active filter circuit in FIG.
The transfer function of The off-frequency ωC is given by the following equation (68), and Q is given by the following equation (
69), and the band rejection center frequency ω8 is given by the following equation (70
) is given by

If ω8〉ωC, a low-pass and band-stop filter (
low-pass notch filter), and in the case of ω, ωC,
It becomes a high-pass and band-rejection filter (bypass notch filter).

K1=2. When 3 = 4, a low-pass filter, a band-pass filter, a band-elimination filter, and a phase-shift filter can be implemented in the same way as shown in the previous embodiments.

In the embodiment of FIG. 8, in order to realize a low-pass notch filter or a bypass notch filter, the formula (68
) and (70), this can be realized by changing the values of 3 and 4. However, in the embodiment of FIG. 6, as is clear from the circuit diagram and equation (44), the signal input to the second differential pair 14 is not divided, but is filtered by a low-pass notch filter or a bypass notch filter. cannot be realized.

The embodiment in FIG. 9 is the second differential pair 14 in the embodiment in FIG.
This is an example in which the same changes as in the first differential pair in the embodiment of FIG. 7 are made by resistors R14 to R16, and the seventh
Similar to the embodiment shown in the figure, the effect of not being affected by errors in resistance ratio can be obtained.

The embodiment in FIG. 10 shows a modification of the embodiment in FIG. 5, in which the same changes as in the first differential pair 12 in the embodiment in FIG. be.

In this FIG. 10 embodiment, the above equation (28) is replaced by the following equation (
71〉.

V2+ 2 tel 5CIV4 + 4 rel re2 S” ClC2・-V5
=V1+2rel 5CIV1 14 rel re2 S'' ClC2・-VIHere, when terminals 22 and 24 are grounded and a signal is input from terminal 20, V4=V5=O2V2=Vin, and the first
The transfer function T(.

is given by the following equation (72).

...(72) This indicates a second-order low-pass function. The cutoff frequency ωC is given by the following equation (73), and Q is given by the following equation (73).
74〉.

In this way, the active filter circuit 1 of FIG.
0' is realized as a second-order low-pass filter.

Note that the bypass filter, bandpass filter, band elimination filter, and phase shift filter can also be realized using the circuit shown in FIG. Further explanation will be omitted here.

The embodiment of FIG. 11 is the embodiment of FIG. 10 in which the same changes as the first differential pair 12 of the embodiment of FIG. 7 are added to the second differential pair 14.

In other words, the embodiment shown in FIG. 11 is a modification of the embodiment shown in FIG.
and (76) are obtained.

From the above equations (75) and (76), as jω=S,
When voltage V3 is erased, the following equation (77) is obtained.

K I K3V2+ 4 ・2re25CIV5+ 4
rel re2 S ” CIC2V4=K I K
3V1+K 3 ・2re2 S(1:2νl+ 4
rel re2 S” CIC2V1Here, if signals are input to terminals 20 and 22 at the same time and terminal 24 is grounded, V2=V4=Vi
n, V5=0, and the transfer function T(i) of the active filter circuit 10'' in FIG. It is a pass and band rejection function.The cutoff frequency ωC is given by the following equation (79), and Q is given by the following equation (79).
80), and the band rejection center frequency ω8 is given by the following equation (8
1) is given by

If ω,〉ωC, it becomes a low-pass notch filter, and ω
If N<ωC, it becomes a bypass notch filter.

K1=2. When 3 = 4, a low-pass filter, a band-pass filter, a band-elimination filter, and a phase-shift filter can be realized in the same way as shown in the embodiment of FIG.

In the embodiment of FIG. 12 as well, as is clear from equations (61) and (63), a low-pass notch filter or a bypass notch filter can be realized by using different values of K1 and 2.

However, in the embodiment of FIG. 10, as is clear from the circuit diagram and equation (39), the first differential pair 1
The signal input to 2' is not split and cannot implement a low-pass notch filter or a bypass notch filter.

Note that in each of the embodiments shown in FIGS. 11 and 13, the input (base) voltage of the transistors constituting each differential pair is divided by three resistors in the same way as in the embodiment of FIG. 7 or 9. Since it is given by pressure, Figures 10 and 12
The influence of variations in bias resistance of each transistor in the illustrated embodiment can be eliminated. However, redundant explanation has been omitted here.

Although the above embodiment was a secondary active filter circuit 10 or 10', this invention
The present invention can be similarly applied to a third-order active filter circuit 100 as shown in the figure.

Active filter circuit 10 in FIGS. 14A to 14D
0 are specifically configured as shown in FIGS. 15A to 15D.

In the active filter circuit 100 shown in FIG. 15A, the current 11 of the transistors Q11 and Q12 constituting the first differential pair 12 is expressed by the following formula (82)%.The voltage VCII of the capacitor C11 is expressed by the following formula (83). It will be done.

From equations (82) and (83), The following equation (84) is obtained.

Similarly, for the second and third differential pairs, the following equation (8
5) and (86) hold true.

However, re3 is the emitter resistance of transistors Q31 and Q32.

From the previous equations (84), (85) and (86), jω
=S, and eliminating voltages v3 and v4, the following equation (8
7) is the % formula % ) ) ) ) (87) Here, if signals are input to terminals 22 and 34 at the same time and reverse phase signals are input to terminals 18 and 32, V4 = V7
=Vin, V1=V6=-Vin, and the transfer function T(s) of the active filter circuit 100 is given by the following equation (88).

A=8relre2re3C11C12C13-(8B
) This equation (88) represents a third-order phase shift circuit.

Similarly, third-order filter circuits are obtained in FIGS. 15B to 150, but since the details will be easily understood by those skilled in the art, their detailed explanation will be omitted here. . However, it goes without saying that in the active filter circuit 100 shown in FIGS. 15A to 150, a resistor circuit that divides the input terminals may be added in the same way as in the active filter circuit 0 or 10" described above. .

Figures 3, 5 to 13, and 15 explained above
Active filter circuit 10 shown in FIGS. A to 15D.
10' or 100 can be used as follows.

FIG. 16 shows a PL L as another embodiment of the present invention.
(Phase Locked Loop), in which an active filter circuit 10, 10' or 100 is used as a bandpass filter 40.

In FIG. 16, the amplifier 42 is connected so that the output from the bandpass filter 40 is in phase and the gain is 1 or more.
The oscillator is configured by feeding back the oscillator through the oscillator. The center frequency of this bandpass filter 40 is controlled to be vCO44.

If the input and output of the amplifier 42 are in phase and the closed loop gain of the vCO 44 is 1 or more, the phase difference between the input and output at the center frequency of the bandpass filter 40 is 0.
(in-phase), the vCO 44 oscillates at the center frequency of the bandpass filter 40. The phase of the signal obtained by this vCO 44 is compared with the input signal by a phase comparator 46.

When only the DC voltage component is extracted from the signal output from the phase comparator 46 by the low-pass filter 48, vC
A control voltage Vc is obtained according to the deviation between the oscillation signal of O44 and the input signal. When this control voltage Vc is feedback-controlled to the terminal 26 shown in FIG. 3, for example, vCO44
The output is controlled to have the same frequency as the input signal.

In this way, vCO can be built into an IC, and the same IC can also be
If multiple different types of filter circuits are built into the
By interlocking the control voltage Vc applied to the terminal 26 (FIG. 3a), all the filter circuits can be adjusted with almost no variation by adjusting only one control voltage.

FIGS. 17 and 18 are block diagrams each showing an embodiment in which a crystal filter 50 is added. This crystal filter 50 thereby has v
This is for setting the center frequency of CO44.

FIG. 19 is a block diagram showing a chroma circuit as another embodiment of the invention. In the NTSC system, a video signal is input to an input terminal 52, passes through a 3.58 MHz bandpass filter 54, and is input to a chroma demodulation circuit 58 and a phase comparator 46. 3.
The signal output from the 58 MHz VCO 60 is input to the phase comparator 46, where the phase is compared with the previously input video signal (burst). When only the DC component is extracted from the signal output from the phase comparator 46 by the low-pass filter 48, the input video signal (burst) and 3.5
A voltage corresponding to the deviation from the output signal of the 8 MHz VCO 60 is output as the control voltage Vc. When this control signal Vc is feedback-controlled to the terminal 26 shown in FIG. 3a etc., the center frequency of the bandpass filter 54 becomes equal to the input video signal (burst), and the output signal of the 3.58 MHz VCO 60 becomes equal to the input video signal (burst). be equal. This vC
The output signal of O60 is input to the chroma demodulation circuit 58, and the previously input video signal is demodulated and output as a color difference signal.

Further, the video signal inputted from the input terminal 52 is 3.
The signal is inputted to a video processing circuit 64 through a 58 MHz trap circuit 62, where it is subjected to various video processing and then output as a luminance signal.

In the example of FIG. 19, the 3.58 MIIz bandpass bandpass filter 54MHz in the VCO 60
MHz bandpass filter) and 3.58
) The wrap circuits 62 are all realized by the same active filter circuits 10, 10' or 100 shown in FIG.
58 MHz) as a control voltage to the wrap circuit 62, these filter characteristics are automatically adjusted to desired characteristics.

FIG. 20 is a block diagram showing a circuit for automatically controlling a phase shift filter in quadrature detection as an embodiment of the present invention. The FM signal input is provided from an input terminal 66 to a phase shift filter 68 and also to a multiplier 70 . The output of phase shift filter 68 is also provided to multiplier 70. The output of the multiplier 70 passes through a low-pass filter 72 and is delivered to an output terminal 74 as a demodulated output. In other words, quadrature detection is, as is well known,
The FM signal input and the signal phase-shifted by the phase-shifting filter 68 are multiplied in a multiplier 70, and when the phase difference between the two signals is 90°, the reference voltage Vref is obtained, and a three-figure curve centered on this is obtained. This is to obtain demodulated output.

What should be noted here is that the output of the multiplier 70 is applied to a low-pass filter 76, and the output of the low-pass filter 76 is applied to a level comparator 78. The low-pass filter 76 extracts a DC voltage according to the phase difference of the output from the multiplier 70, and the output of the low-pass filter 76 is given to the level comparator 78 together with the reference voltage Vref. And level comparator 78
From, the output V of the low-pass filter and the reference voltage ■ref
The control voltage Vc corresponding to the difference between
is given as the control voltage.

Incidentally, as the phase shift filter 68 in the embodiment of FIG. 20, an active filter circuit 10, 10' or 100 as shown in FIG. 3 etc. can be used.

In FIG. 20, the characteristics of the phase shift filter 68 deviate from the desired characteristics, and the phase difference is 9 at the predetermined frequency fo.
If the voltage does not reach 0°, the low-pass filter 76 extracts only the DC voltage component from the signal output from the multiplier 70, and a voltage (2) corresponding to the deviation of the filter characteristics from the reference voltage Vref is output. When the voltage V and the reference voltage Vref are compared by the level comparator 78, the level comparator 7B outputs a voltage corresponding to the deviation of the filter characteristics as the w-control voltage Vc. This control voltage Vc is
For example, when feedback control is applied to the terminal 26 shown in FIG. 3, the phase shift filter 64 is automatically controlled so that the output phase difference becomes 90 degrees.

Note that the FM detection method is not limited to the quadrature detection method described above, but may be any other method.

FIG. 21 is a block diagram showing a VIF and SIF circuit as another embodiment of the invention.

In an NTSC television receiver, a VIF signal is input to input terminals 80 and 82, and this VIF signal is applied to a video detection circuit 86 through a VIF amplifier 84. The video detection circuit 86 detects the VIP signal and extracts a video signal component, which passes through a 4.5 MHz wrap circuit 88 and becomes a video output.

Moreover, the output of the video detection circuit 86 is 4.5MH2BP
F (bandpass filter) 90, and this 4.
The output of the 5 MHz BPF 90 is applied to a 4.5 MHz discretizer (ξator) 94 via a limiter amplifier 92. And the output of the 4.5MHz disk drive 94 is F
The signal is applied to the M detection circuit 96. On the other hand, ξ ivy amplifier 9
The output of 2 is directly applied to the FM detection circuit 96. A demodulated audio output is obtained from the FM detection circuit 96.

What should be noted is that the output of the FM detection circuit 96 is provided to a level comparator 98, and this level comparator 98 is further provided with a reference voltage Vref.

In the embodiment of FIG. 21, the 4.5 MHz trap 88, 4.5 MHz BPF 90, and 4.5 MHz discreet 84 are the same active filter circuits 0.10' as shown in FIG. , or 100 are available.

Since the SIF signal is an FM wave, in FIG. 21, first, only the DC voltage component is extracted from the output signal detected by the FM detection circuit 96, and the voltage V becomes the center voltage of the original three-figure curve. power reference voltage Vref
and are compared in a level comparator 98. therefore,
In the level comparator 98, as in the embodiment of FIG.
A voltage corresponding to the deviation in the characteristics of the 4.5MHz disk drive 94 is obtained, and this voltage is set as the control voltage Vc, and the 4.5MHz
It is applied to the control input of the z disc 94.

In this embodiment, since the 4.5 MHz) wrap 88 and the 4.5 MHz BPF 90 are realized by filter circuits having the same circuit configuration, the same output of the level comparator 98, that is, the control voltage Vc is applied to these circuits 86 and 8.
8 as a control input.

In this way, the voltage V corresponding to the shift in the filter characteristics of the 4.5 MHz discret 94 is compared with the reference voltage Vref, and the difference voltage is used to determine not only the 4.5 MHz disc 94 but also the 4.5 MHz) wrap 88. and 4,5MHzB
By applying the control voltage Vc to the PF 90, the characteristics of these filters can be uniformly adjusted or controlled.

In both the embodiments shown in FIGS. 20 and 21, the deviation of the output voltage of the figure-eight curve of the FM detection circuit is compared with the reference voltage Vref. however,
This invention is applicable to other signal system ICs that do not require FM detection.
Even within the system, the active filter can be automatically adjusted or controlled to have desired characteristics. In this case, it is necessary to provide a phase shift filter as a dummy filter.

However, even in this case, there is no need to use a conventional reference signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIGS. 2A to 2C are circuit diagrams showing differential pairs that can be used in the present invention. FIG. 3 is a circuit diagram showing the embodiment of FIG. 1 in detail. FIG. 4 is a circuit diagram showing another embodiment of the invention. FIG. 5 is a circuit diagram showing the embodiment of FIG. 4 in detail. FIG. 6 is a circuit diagram showing a modification of the embodiment of FIG. 3. FIG. 7 is a circuit diagram showing a modification of the embodiment of FIG. 6. FIG. 8 is a circuit diagram showing another modification of the embodiment of FIG. 3. FIG. 9 is a circuit diagram showing a modification of the embodiment of FIG. 8. FIG. 1O is a circuit diagram showing a modification of the embodiment of FIG. 5. FIG. 11 is a circuit diagram showing a modification of the embodiment of FIG. 10. FIG. 12 is a circuit diagram showing another modification of the embodiment of FIG. 5. FIG. 13 is a circuit diagram showing a modification of the embodiment of FIG. 12. FIGS. 14A to 14D are circuit diagrams showing other embodiments of the present invention. 15A to 15D are circuit diagrams showing the embodiments of FIGS. 14A to 14D in detail, respectively. FIG. 16 is a block diagram showing an embodiment of a PLL using an active filter circuit according to the present invention. FIGS. 17 and 18 are block diagrams showing modifications of the embodiment shown in FIG. 16 in which a crystal filter is added. FIG. 19 is a block diagram showing a chroma circuit as another embodiment of the invention. FIG. 20 is a block diagram showing a quadrature detection circuit as another embodiment of the invention. FIG. 21 is a block diagram showing a VIF and SIF circuit as another embodiment of the invention. FIG. 22 is a circuit diagram showing a conventional method for automatically controlling the cutoff frequency of a low-pass filter. In the figure, 10.10' is an active filter circuit,
12.12' is a first differential pair, 14.14' is a second differential pair, 40 is a bandpass filter, and 44 is a VCO.

Claims (1)

[Claims] 1. A first differential pair including first and second transistors, a first differential pair connected to an output terminal of the second transistor of the first differential pair. a capacitive load, a first negative feedback path for negatively feeding the output of the second transistor to the input of the second transistor, and a second transistor including a third and a fourth transistor.
a second capacitive load connected to an output terminal of the fourth transistor of the second differential pair, and an output of the fourth transistor forming the first differential pair. An active filter circuit comprising a second negative feedback path for negative feedback to the input of the first transistor. 2 a first differential pair configured to include first and second transistors; a first capacitive load connected to the output of the second transistor of the first differential pair; A second transistor including a fourth transistor.
a differential pair of the first differential pair; a connection path for connecting the output of the second transistor of the first differential pair to the input of the fourth transistor of the second differential pair; a second capacitive load connected to the output; and a negative feedback path for negatively feeding the output of the fourth transistor to the input of the first transistor constituting the first differential pair. Active filter circuit. 3. The active filter circuit according to claim 1 or 2, further comprising current changing means for changing the amount of current of the first and second differential pairs in a correlated manner in response to a given control voltage. . 4. The active filter circuit according to claim 3, wherein the bases of two transistors are formed in association with at least one of the first and second differential pairs and constitute at least one of the differential pairs. The device further includes bias means for applying a bias voltage to each. 5. An active filter circuit according to claim 4, wherein the bias means includes a resistance voltage divider means for applying a divided voltage to the bases of each of the two transistors as the bias voltage. 6. An active filter circuit according to claim 5, wherein the resistor voltage dividing means includes a first resistor connected in series, the series connection point of which is connected to the base of one of the two transistors, and a first resistor connected in series to the base of the other transistor. a second resistor series connection to which the connection point is connected; 7. An active filter circuit according to claim 6, wherein the biasing means further includes a bias power supply, and one end of each of the two resistor series connections is connected to the bias power supply. 8. An active filter circuit according to claim 6, wherein said first and second resistor series connections include a common resistor interconnected to the bases of said two transistors. 9. A filter whose output phase characteristics change according to the control voltage, means for extracting a DC voltage component according to the phase characteristics of the output of the filter, and level comparison means for comparing the DC voltage component with a reference voltage. , and means for applying the control voltage to the filter based on the output of the level comparison means. 10. A filter control circuit according to claim 9, wherein the filter includes a first differential pair including a first and a second transistor, and a second differential pair of the first differential pair.
a first capacitive load connected to the output terminal of the transistor; a first negative feedback path for negatively feeding the output of the second transistor to the input of the second transistor; a second differential pair configured to include transistors; a second capacitive load connected to the output terminal of the fourth transistor of the second differential pair; the first differential pair constituting the first differential pair;
a second negative feedback path for negative feedback to the input of the transistor; and current changing means for changing the amount of current of the first and second differential pairs in a correlated manner in response to the control voltage. 11. A filter control circuit according to claim 9, comprising:
The filter includes a first differential pair including first and second transistors, and a second differential pair of the first differential pair.
a first capacitive load connected to the output of the transistor; a second capacitive load comprising a third and a fourth transistor;
a differential pair of the first differential pair; a connection path for connecting the output of the second transistor of the first differential pair to the input of the fourth transistor of the second differential pair; a second capacitive load connected to the output; a negative feedback path for negatively feeding the output of the fourth transistor to the input of the first transistor forming the first differential pair; and the control. Current changing means for changing the amount of current of the first and second differential pairs in a correlated manner in response to voltage. 12. A filter whose center frequency changes according to the control voltage; amplifier means for feeding back the output of the filter to the input in phase and having a gain of 1 or more; phase comparison means for receiving the output of the filter and another input signal; A filter control circuit comprising means for applying the control voltage to the filter based on the output of the phase comparison means. 13. A filter control circuit according to claim 12, wherein the filter includes a first transistor and a second transistor.
a differential pair, a first capacitive load connected to the output terminal of the second transistor of the first differential pair, and negative feedback of the output of the second transistor to the input of the second transistor. a first negative feedback path, a second negative feedback path including third and fourth transistors;
a second capacitive load connected to an output terminal of the fourth transistor of the second differential pair, the output of the fourth transistor forming the first differential pair; a second negative feedback path for negative feedback to the input of the first transistor; and a current changing means for changing the amount of current of the first and second differential pairs in a correlated manner in response to the control voltage. including. 14. A filter control circuit according to claim 12, wherein the filter includes a first differential pair including a first and a second transistor, and a second transistor of the first differential pair. a first capacitive load connected to the output of the second capacitive load, a second capacitive load comprising a third and a fourth transistor;
a differential pair of the first differential pair; a connection path for connecting the output of the second transistor of the first differential pair to the input of the fourth transistor of the second differential pair; a second capacitive load connected to the output; a negative feedback path for negatively feeding the output of the fourth transistor to the input of the first transistor forming the first differential pair; and the control. Current changing means for changing the amount of current of the first and second differential pairs in a correlated manner in response to voltage.