JPH0318744B2 - - Google Patents
Info
- Publication number
- JPH0318744B2 JPH0318744B2 JP60040583A JP4058385A JPH0318744B2 JP H0318744 B2 JPH0318744 B2 JP H0318744B2 JP 60040583 A JP60040583 A JP 60040583A JP 4058385 A JP4058385 A JP 4058385A JP H0318744 B2 JPH0318744 B2 JP H0318744B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- grounded
- disconnected
- integrated circuit
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 230000003068 static effect Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract 1
- 230000003467 diminishing effect Effects 0.000 abstract 1
- 230000006698 induction Effects 0.000 abstract 1
- 230000003014 reinforcing effect Effects 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 230000010354 integration Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体集積回路（IC）とその製造方
法に係り、特に、ICパツケージ（容器）の無接
続リード端子の処置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit (IC) and a method for manufacturing the same, and particularly relates to treatment of unconnected lead terminals of an IC package (container).
現在、ICは驚異的に発展し続けて、あらゆる
分野に普及し、且つ、IC自体はLSI，VLSIと著
しく高集積化・高密度化されている。それは、
ICの信頼度が高くて、システムや機器の信頼性
を向上させていることにも一因があり、また、
ICの高集積化は、高速動作などICの性能向上に
有利なためである。 Currently, ICs are continuing to develop at an amazing rate and are becoming widespread in all fields, and ICs themselves are becoming extremely highly integrated and densely packed with LSIs and VLSIs. it is,
This is partly due to the high reliability of ICs, which improves the reliability of systems and equipment.
This is because higher integration of ICs is advantageous for improving IC performance such as high-speed operation.
一方、ICには静電破壊という問題があり、そ
れはICの周囲にある物体や人体などに帯電した
静電気が、ICと接触あるいは接近した端子を通
して放電し、それによつて絶縁破壊させる現象で
ある。 On the other hand, ICs have the problem of electrostatic discharge damage, which is a phenomenon in which static electricity that has been charged on objects or people around the IC discharges through terminals that are in contact with or close to the IC, resulting in dielectric breakdown.
且つ、静電破壊はICの高集積化とは逆比例し
て増加する傾向にあり、静電破壊防止に対して高
集積化は余り好ましくはない。従つて、ICの信
頼性の面から、静電破壊とそれに伴う問題につい
て、一層十分な配慮が望まれる。 In addition, electrostatic damage tends to increase in inverse proportion to higher integration of ICs, and higher integration is not very desirable for preventing electrostatic damage. Therefore, from the standpoint of IC reliability, it is desirable to give even more careful consideration to electrostatic discharge damage and the problems associated with it.
また、一方、ICは高集積化される程、誘導ノ
イズが増加する問題があるが、このような内部回
路間の誘導ノイズはできるだけ少ないことが望ま
しい。 On the other hand, as ICs become more highly integrated, there is a problem in that induced noise increases; however, it is desirable to minimize such induced noise between internal circuits.
［従来の技術と発明が解決しようとする問題点］
さて、この静電気による破壊について、従来、
回路的には入力端子に静電破壊保護策が採られて
おり、例えば第３図に示すようなシヨツトキーク
ランプトランジスタTRとシヨツトキーダイオー
ドＤ、抵抗Ｒを組み合わせたサージ電圧放電回路
が設けられている。同図において、INは入力端
子、ＧはIC内の回路に接続する。また、図示し
ていないが、出力端子は出力回路が静電破壊から
防護する能力を有しており、同様に静電破壊から
保護されている。従つて、IC内の回路はまず安
全に保護されていると云つてよい。[Problems to be solved by the conventional technology and the invention] Now, regarding this destruction caused by static electricity, conventionally,
In terms of the circuit, electrostatic damage protection measures are taken at the input terminals, such as a surge voltage discharge circuit that combines a shot key clamp transistor TR, a shot key diode D, and a resistor R as shown in Figure 3. It is being In the figure, IN is an input terminal, and G is connected to a circuit inside the IC. Although not shown, the output terminal has the ability to protect the output circuit from electrostatic damage, and is similarly protected from electrostatic damage. Therefore, it can be said that the circuits inside the IC are safely protected.
ところが、高集積化されたLSIともなれば、IC
パツケージには多数のリード端子（以下、ピンと
呼ぶ）が設けてあり、すべてのピンが内部の回路
に接続しているわけではない。特に、ゲートアレ
イでは数千個のゲート回路を有していて、パツケ
ージには数十〜数千本程度のピンが設けられてい
るが、その内の数本〜数十本のピンは無接続ピン
となる。ゲートアレイはマスタースライス方式で
作られ、それは半導体チツプを一律に作成し、カ
スタマー（使用者）の要求でチツプ内の配線を自
在に換える方式で、この方式では無接続ピンの存
在は避けられない問題である。 However, when it comes to highly integrated LSIs, IC
The package has a large number of lead terminals (hereinafter referred to as pins), and not all pins are connected to internal circuits. In particular, gate arrays have thousands of gate circuits, and the package has tens to thousands of pins, but several to dozens of pins are not connected. It becomes a pin. Gate arrays are made using the master slice method, in which semiconductor chips are created uniformly and the wiring within the chip is freely changed at the request of the customer (user); with this method, the presence of unconnected pins is unavoidable. That's a problem.
一方、周知のように、ICでは半導体チツプ面
のボンデイングパツドとパツケージ内部のリード
との間は、金線やアルミニウム線によつてワイヤ
ーボンデイングされて接続しており、このような
ワイヤーボンデイングは自動ボンデイング機で作
業されている。従つて、チツプ内のIC回路と無
接続であり、電気的に浮遊状態になつているピン
も、一律にワイヤーボンデイングすることにより
合理化されている。 On the other hand, as is well known, in ICs, the bonding pads on the semiconductor chip surface and the leads inside the package are connected by wire bonding using gold wire or aluminum wire, and such wire bonding is automatic. Working with a bonding machine. Therefore, even pins that are electrically floating and are not connected to the IC circuit within the chip are streamlined by uniformly wire bonding them.
そうすると、若しその無接続ピンに静電気によ
る高いサージ電圧が印加されれば、電荷の抜け道
がなくなつて、絶縁耐圧の低い半導体チツプの内
部部分が破壊されて、接地状態になる。第４図は
静電気による破壊部分を例示している図で、ボン
デイングワイヤーＷがパツドPAにボンデイング
されているが、パツドPAの下層は膜厚数千Åの
二酸化シリコン膜１で覆われ、その下の半導体チ
ツプは電気的に浮遊した領域２が、接地された基
板部３に囲まれた状態となつている。ここに、静
電気が印加されると、最も絶縁耐圧の低い二酸化
シリコン膜１が矢印部分で破壊されて、無接続ピ
ンは接地状態になる。更に、サージ電圧が非常に
高いと、点矢印部分でも破壊される。 Then, if a high surge voltage due to static electricity is applied to the unconnected pin, there will be no way for the charge to escape, and the internal portion of the semiconductor chip with low dielectric strength will be destroyed, resulting in a grounded state. Fig. 4 is a diagram illustrating a part broken by static electricity, in which a bonding wire W is bonded to a pad PA, but the lower layer of the pad PA is covered with a silicon dioxide film 1 with a thickness of several thousand angstroms. The semiconductor chip has an electrically floating region 2 surrounded by a grounded substrate portion 3. When static electricity is applied here, the silicon dioxide film 1, which has the lowest dielectric strength, is destroyed at the arrowed portion, and the unconnected pin becomes grounded. Furthermore, if the surge voltage is very high, even the dotted arrow portion will be destroyed.
この無接続ピンの静電破壊を避けるためには、
その無接続ピンをワイヤーボンデイングしないこ
とが考えられるが、それは自動ボンデイング機の
入力を常時変更することになつて、大きな工数増
加につながる。 To avoid electrostatic damage to this unconnected pin,
It is conceivable not to wire-bond the unconnected pins, but this would require constant changes to the input of the automatic bonding machine, leading to a large increase in man-hours.
又、第４図における二酸化シリコン膜１の膜厚
を厚くすると絶縁耐圧は向上するが、それは段差
が大きくなつてウエハープロセスを困難にする問
題があり、そのため、チツプ収率が低下する。 Further, if the thickness of the silicon dioxide film 1 in FIG. 4 is increased, the dielectric strength is improved, but this increases the step difference, making the wafer process difficult, and as a result, the chip yield decreases.
本発明は、このような問題のある無接続ピンを
なくする半導体集積回路とその製造方法を提供す
るものである。 The present invention provides a semiconductor integrated circuit and its manufacturing method that eliminates such problematic unconnected pins.
［問題点を解決するための手段］
その目的は、ICパツケージに設けられている、
内部回路とは無接続のリード端子すべてが、接地
されている半導体集積回路によつて達成される。[Means to solve the problem] The purpose is to solve the problem by
This is accomplished by a semiconductor integrated circuit in which all lead terminals that are not connected to the internal circuit are grounded.
又、それには、配線パターン作成時に、無接続
ボンデイングパツドが接地配線に自動的に接続さ
れるようにした半導体集積回路の製造方法で作成
する。 Further, in order to do this, a semiconductor integrated circuit is manufactured using a method of manufacturing a semiconductor integrated circuit in which a non-connection bonding pad is automatically connected to a ground wiring when a wiring pattern is created.
［作用］
即ち、本発明は、たとえ静電気が印加されても
破壊されないように、電気的に浮遊状態にある無
接続ピンをなくして、接地しておく。[Function] That is, the present invention eliminates the unconnected pin that is electrically floating and grounds it so that it will not be destroyed even if static electricity is applied.
そうすれば、無接続ピンに加わる衝撃電圧がな
くなり、IC内の回路への悪影響は避けられ、更
に、回路安定化への効果も得られる。 This eliminates the impact voltage applied to the unconnected pins, avoids any negative effects on the circuitry within the IC, and further stabilizes the circuit.
［実施例］
以下、図面を参照して実施例によつて説明する
と、第１図は無接続パツド部分の平面図を示して
おり、PAはパツド、L0は接地配線、L1が本発明
に関係する接続配線パターン、Ｗはボンデイング
ワイヤーである。[Example] Hereinafter, an example will be explained with reference to the drawings. Fig. 1 shows a plan view of a non-connected pad part, where PA is a pad, L0 is a ground wiring, and L1 is a wire according to the present invention. The connection wiring pattern related to , W is a bonding wire.
従来より、半導体チツプ上の配線パターンはコ
ンピユータの力を借りて（CADシステムによつ
て）プログラム化されており、第１図のような無
接続パツドを認識すれば、配線パターンL1を作
成する命令を入力しておけば、なんら工数を増加
することなしに、すべての無接続ピンを接地ピン
に換えることができ、自動的に配線できる。 Traditionally, wiring patterns on semiconductor chips have been programmed with the help of a computer (through a CAD system), and if an unconnected pad like the one shown in Figure 1 is recognized, a wiring pattern L1 is created. By inputting a command, all unconnected pins can be replaced with ground pins without any increase in man-hours, and wiring can be done automatically.
このようなIC構造にすれば、上記したような
静電破壊が防止されるが、その他にも次のような
利点が得られる。例えば、ゲートアレイでは無接
続ピンが通常、数％〜数十％と多数存在している
が、それらを全部接地ピンにすると、ICパツケ
ージ内で接地配線が密集した信号配線間に多数存
在することになる。そのため、シールド効果が大
きくなつて、クロストークなどの誘導ノイズも減
少し、又、ノイズへの耐性が強くなつて、IC回
路が安定化される。 Such an IC structure prevents the electrostatic damage described above, but also provides the following advantages. For example, in a gate array, there are usually a large number of unconnected pins, ranging from a few percent to several tens of percent, but if all of them are grounded, a large number of them will exist between the signal lines where the ground lines are densely packed in the IC package. become. Therefore, the shielding effect is increased, inductive noise such as crosstalk is reduced, and resistance to noise is increased, and the IC circuit is stabilized.
第２図はピングリツドアレイ型パツケージを用
いたICの斜視図を示しており、チツプの周囲に
は無数のワイヤーＷがボンデイングされている。
又、裏面には多数のピンＮが設けられているが、
本発明を適用すれば密集したワイヤーＷ部分およ
びパツケージ内での輻輳したメタライズ配線部分
での誘導ノイズ耐性が強くなる。 FIG. 2 shows a perspective view of an IC using a pin grid array type package, in which numerous wires W are bonded around the chip.
Also, there are many pins N on the back side,
If the present invention is applied, the resistance to induced noise will be enhanced in the dense wire W portion and the congested metallized wiring portion within the package.
且つ、ゲートアレイでは、通常、接地配線がパ
ツドの近くに配置されたパターン構造になつてい
るため、第１図に図示した配線形成が簡単で確実
にできる。そのため、特に本発明が有効になる。 Furthermore, since the gate array usually has a pattern structure in which the ground wiring is placed near the pad, the wiring shown in FIG. 1 can be easily and reliably formed. Therefore, the present invention is particularly effective.
［発明の効果］
以上の説明から明らかなように、本発明によれ
ば静電破壊がなくなつて、且つ、ノイズに強い
ICが得られる効果がある。[Effects of the Invention] As is clear from the above explanation, the present invention eliminates electrostatic damage and is resistant to noise.
It has the effect of providing IC.
第１図は本発明にかかる無接続ボンデイングパ
ツド部分の図、第２図は本発明を適用するピング
リツドアレイ型パツケージに収容したICの斜視
図、第３図は従来のIC回路の入力端子のサージ
電圧放電回路の例図、第４図は従来の問題点を示
す半導体チツプ部分の断面図である。
図において、PAはパツド、Ｗはボンデイング
ワイヤー、L0は接地配線、L1は接地配線、Ｎは
リード端子を示している。
Fig. 1 is a diagram of the unconnected bonding pad portion according to the present invention, Fig. 2 is a perspective view of an IC housed in a pin grid array type package to which the present invention is applied, and Fig. 3 is an input of a conventional IC circuit. FIG. 4, which is an example of a terminal surge voltage discharge circuit, is a sectional view of a semiconductor chip portion showing a conventional problem. In the figure, PA is a pad, W is a bonding wire, L0 is a ground wire, L1 is a ground wire, and N is a lead terminal.
Claims (1)
回路とは無接続のリード端子すべてが、接地され
ていることを特徴とする半導体集積回路。 ２ 配線パターン設計時に、無接続ボンデイング
パツドが接地配線に自動的に接続されるようにし
たことを特徴とする半導体集積回路の製造方法。[Scope of Claims] 1. A semiconductor integrated circuit characterized in that all lead terminals provided on an integrated circuit package and not connected to an internal circuit are grounded. 2. A method for manufacturing a semiconductor integrated circuit, characterized in that a non-connection bonding pad is automatically connected to a ground wiring when designing a wiring pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60040583A JPS61199651A (en) | 1985-02-28 | 1985-02-28 | Semiconductor integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60040583A JPS61199651A (en) | 1985-02-28 | 1985-02-28 | Semiconductor integrated circuit and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61199651A JPS61199651A (en) | 1986-09-04 |
| JPH0318744B2 true JPH0318744B2 (en) | 1991-03-13 |
Family
ID=12584512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60040583A Granted JPS61199651A (en) | 1985-02-28 | 1985-02-28 | Semiconductor integrated circuit and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61199651A (en) |
-
1985
- 1985-02-28 JP JP60040583A patent/JPS61199651A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61199651A (en) | 1986-09-04 |
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