JPH03184419A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress the fluctuation of the threshold voltage of a circuit to a low level even when manufacturing dispersion occurs by connecting a second loading circuit part consisting of the same type of MOS transistor as the one comprising a driving circuit part in a stacked form to a first loading circuit part. CONSTITUTION:In a CMOS inverter, an nMOS 15 comprises the driving circuit part, and a pMOS 14 comprises the first loading circuit part, and an nMOS 13 comprises the second loading circuit part. By providing the nMOS 13, it is possible to suppress the fluctuation of the threshold voltage VT of the circuit within a range of 1.81-2.38[V] even when the manufacturing dispersion occurs in the pMOS 14 and the nMOS 15.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 11 to 16) Problems to be Solved by the Invention Means for Solving the Problems First Invention Second Invention Effects of the first invention Effects of the second invention Embodiments of the invention (Figs. 1 to 10) 1st to 7th embodiments Other effects of the invention [Summary] type of M
OS transistors, e.g. nMo S transistors and other types of MOS transistors, e.g. 9M
Regarding a semiconductor integrated circuit device including a logic gate formed by hierarchically connecting O3 transistors, one type of MOS transistor and another type of MOS transistor
To provide a semiconductor integrated circuit device including a logic gate that can suppress fluctuations in circuit threshold voltage to a small level even if manufacturing variations occur in S transistors similar to those in conventional examples, and to reduce defective chips. For the purpose of reducing the occurrence rate, that is, improving the yield, a drive circuit section consisting of one type of MOS transistor and another type of MOS transistor is installed between one voltage source and the other voltage source. The device includes a logic gate formed by sequentially connecting a first load circuit section made of a transistor and a second load circuit section made of one type of MOS transistor in a hierarchical manner.

[Industrial Application Fields] The present invention is applicable to inverters, NAND circuits, etc., using one type of transistor, for example, an nMOSMOS transistor, nMOS, and another type of transistor, for example, a 9MO3 transistor (hereinafter referred to as a 9MO8 transistor).
This invention relates to a semiconductor integrated circuit device that includes logic gates that are hierarchically connected.

In such semiconductor integrated circuit devices, manufacturing variations in the wafer process that affect the characteristics of transistors may cause large fluctuations in the threshold voltage of the circuit, resulting in defective chips. Therefore, it is necessary to include logic gates that are resistant to manufacturing variations.

[Prior Art] Conventionally, a logic gate formed by hierarchically connecting one type of transistor and another type of transistor,
For example, a CMOS whose circuit diagram is shown in FIG.
Inverters are known.

In the figure, 111 is a signal input terminal, 112 is a power supply line, and 113
is an enhancement type 9 that forms a load transistor.
MO3, 114 is an enhancement type nMOS that serves as a driving transistor, 115 is a signal output terminal, and the power supply line 112 is connected to the power supply voltage VCC1, for example, 5 [V
] is supplied.

In such a CMOS inverter, the threshold voltage V↑ of the circuit can be determined by the following equation.

However, VDD=power supply voltage, Vtop: threshold voltage of pMOS 103, V7HN: threshold voltage of nMOS 104,
βp: β of 9MO3103 βN: β of nMOS104, β is εox' μOW, provided that ε. X: Dielectric constant of gate oxide film μ0: Mobility of electrons tox: Thickness of gate oxide film W: Channel width L: Channel length. Therefore, for example, ■ Voo = + 5 [V] ■ VyHx = + 0.8 [V]■VTIP=
0.8 [V] ■ If βN:βp=6:2, the threshold voltage VT of the circuit becomes 2.04 [V].

[Problems to be Solved by the Invention] However, in the CMOS inverter of the conventional example shown in FIG. There was a problem in that the V-cho fluctuated greatly.

For example, both VTHN and VTHP are ±0.2[V]
, β9, and β2 both fluctuate in the range of 1/2 to 2 times. In the case where the threshold voltage VT of the circuit is maximum, ■VTIIN is +0.2 [V] ■VT and P are +0. 2 [V] ■If βN fluctuates by 1/2 and βP changes by twice, that is, ■VTHN = + 1.0 [V] ■VTHP =
0.6 [V] ■βN : βp = 3 : 4 In this case, the threshold voltage of the circuit is 2.82 [V] from equation (1), which is too high. Also, in the case where the circuit threshold voltage V is at its minimum, ■VTIN is -0.
, 2[V] ■VTHP is -0, 2[V] ■When βN changes by 2 times and βP changes by 1/2, that is, ■VTHN = + 0.6 [V] ■V? HP =
1.0 [V] ■βN:βp=12:1 In this case, the threshold voltage of the circuit becomes -1.36 [V], which is too low.

In this way, in the conventional CMOS inverter, V
When THN and VTHP both vary within ±0.2 [V], and β9 and β2 both vary within the range of 1/2 to 2 times, the variation range of the circuit threshold voltage Vd is 1.36 to 2.82 [V].
V], which becomes too large.

FIG. 12 is a circuit diagram showing a conventional NMOS inverter. In the figure, 121 is a signal input terminal, 122 is a power supply line, 123 is a depletion type nMO3 which is a load transistor, and 124 is a drive transistor. An enhancement type nMO3, 125 forming a transistor is a signal output terminal. Even in such an NMOS inverter, the circuit threshold voltage ■↑ fluctuates greatly due to manufacturing variations in the depletion type nMO 3123 and the enhancement type nMO 3124, which has been a problem.

As described above, in a logic gate formed by hierarchically connecting one type of transistor and another type of transistor, the threshold voltage of the circuit due to manufacturing variations of one type of transistor and the other type of transistor There were large fluctuations, which was a problem. In addition to the examples shown in FIGS. 11 and 12, examples of logic gates that can be applied include the PMOS inverter shown in FIG.
D circuit (hereinafter referred to as CMO3-NAND circuit), first
The NAND circuit (hereinafter referred to as NMO3-NAND circuit) that is connected to the bottom of the tank by NMO3 shown in Fig. 5, and the NAND circuit that is connected to the bottom of the tank by PMO3 (hereinafter referred to as PMO3) shown in Fig.
8-NAND circuit).

In addition, in FIG. 13, 131 is a signal input terminal;
2 is a power supply line, 133 is a depletion type 9MO8 which forms a load transistor, 134 is an enhancement type pMOS which forms a driving transistor, 135 is a signal output terminal, and the power supply line 132 is connected to a negative power supply voltage. −
Vcc, for example, -5 [V] is supplied.

In addition, in FIG. 14, 141.142 is a signal input terminal, 143 is a power supply line, 144.145 is an enhancement type pMO3, 146, which forms a load transistor,
147 is an enhancement type nMOS serving as a driving transistor, and 148 is a signal output terminal.

In FIG. 15, 151 and 152 are signal input terminals, 153 is a power supply line, 154 is a depletion type nMOS that serves as a load transistor, and 155 and 156 are enhancement type nMOSs that serve as a drive transistor.
S, 157 is a signal output terminal.

Further, in FIG. 16, 161 and 162 are signal input terminals, 163 is a power supply line, 164 is a depletion type pMO that serves as a load transistor, and 165 and 166 are enhancement type pMOs that serve as drive transistors.
3,167 is a signal output terminal.

In view of this point, the present invention has been made such that even if manufacturing variations occur in one type of MOS transistor and another type of MOS transistor as in the conventional example, fluctuations in the threshold voltage of the circuit can be suppressed to a small level. It is an object of the present invention to provide a semiconductor integrated circuit device including logic gates having the same structure, and to reduce the incidence of defective chips, that is, to improve yield.

[Means for Solving the Problems] The above objects are achieved by the following first and second inventions.

Plan! υ1 crazy In the present invention, the semiconductor integrated circuit device of the first invention has one type of MO5I between one voltage source and the other voltage source.
- Drive circuit section consisting of transistors and other types of MO
It is configured to include a logic gate formed by hierarchically connecting a first load circuit section consisting of an S transistor and a second load circuit section consisting of one type of MOS transistor in order.

Plan! In the present invention, a semiconductor device according to a second aspect of the present invention includes a drive circuit section consisting of one type of MOS transistor and another type of MOS transistor between one voltage source and the other voltage source. A first load circuit section consisting of a transistor, and one type of MO.
A second load circuit section consisting of a parallel circuit of an S transistor and another type of MOS transistor is sequentially connected in a hierarchical manner.

[Effect] The effects of the first and second inventions are as follows.

Notebook 1! The logic gate in the first invention originally consists of a drive circuit section consisting of one type of MOS transistor and a first load circuit section consisting of another type of MOS transistor. In a logic gate configured by connecting
On the load circuit section, a MOS that constitutes a drive circuit section is further installed.
It is configured by hierarchically connecting a second load circuit section made of MOS transistors of the same type as the transistor.

In such a logic gate, a first load circuit section and a second load circuit section composed of other types of MOS transistors constitute a load for the drive circuit section. Since it is composed of MOS transistors of the same type as the MOS transistors that make up the circuit section, even if manufacturing variations occur between one type of MOS transistor and another type of MOS transistor, fluctuations in the threshold voltage of the circuit can be minimized. It can be suppressed.

1 star! The logic gate in the second invention originally consists of a drive circuit section consisting of one type of MOS transistor and a first load circuit section consisting of another type of MOS transistor in a hierarchical manner. In the logic gate configured by connecting, a second load circuit section comprising a parallel circuit of one type of MOS transistor and another type of MOS transistor is further hierarchically connected on the first load circuit section. It is composed of:

In other words, in the logic gate according to the first invention, the second load circuit section consisting of one type of MOS transistor further includes another type of MOS transistor.
It is constructed by connecting transistors in parallel to form a new second load circuit section.

According to such a logic gate, low voltage operation is possible due to the presence of another type of MOS transistor constituting the second load circuit section;
To suppress variations in the threshold voltage of a circuit to a small level even if manufacturing variations occur between one type of MOS transistor and another type of MOS transistor due to the presence of one type of MOS transistor at the bottom of the load circuit section of the circuit. becomes possible.

[Examples] Various embodiments of the present invention will be described below with reference to FIGS. 1 to 10.

1 1 2 The first embodiment is an attempt to apply the first invention to a CMOS type semiconductor integrated circuit device, and in this first embodiment, the logic gate is, for example, the first
It is constructed as shown in FIG.

Here, FIG. 1 is an example of a CMOS inverter,
In the figure, 11 is a signal input terminal, 12 is a power supply line, and 13 is an enhancement type nMOS that serves as a load transistor.
, 14 is an enhancement type 9MO8 serving as a load transistor, 15 is an enhancement type nMOS serving as a driving transistor, and 16 is a signal output terminal. Note that in this CMOS inverter, nMOS15 is the drive circuit section, pMO314 is the first load circuit section, and nMOS
S13 constitutes a second load circuit section.

In the first embodiment, the source voltage of the pMOS 14 is V DD VT)IN, so the threshold voltage of the circuit is V . However, βX is β of the nMOS 13 and is proportional to βN. Therefore, for example, ■ VDD=+5
[v] ■V TIN = + 0.8 [V] ■Vtop
= 0.8 [V] ■ If βN : βP : βx = 6 : 2 : 3, the threshold voltage VT of the circuit is = 2.04
[V], which is the same as in the conventional example.

Furthermore, according to the CMOS inverter shown in FIG. 1,
Due to manufacturing variations in the wafer process, VT
HN, VTMP, 13 s, B p f) Even if the value N'R movement occurs, the fluctuation of the circuit threshold voltage VT can be suppressed to a small level6.
VT□, V in the same way as explained in the conventional example in Fig. 1.

Considering the case where both βN and βP fluctuate in the range of 1/2 to 2 times, the case where the threshold voltage V of the circuit is maximum is ■V TIN +0.2 [V].
2 [V] ■V TIP 11' + 0.2 [V] ■When βN changes by 1/2 and βP changes by twice, that is, ■VTHN = + 1.0 [V] ■V tI4p
= 0.6 [V]■βN :βP:βX =
3 : 4 : 1.5, in this case,
The threshold voltage Vt of the circuit is =2.38[V].

In addition, in the case where the circuit threshold voltage is V, ■ VTHN is -0, 2 [V] ■ VTHP is -0, 2 [V] ■ If βN changes twice and βP changes by 1/2, that is, , ■VTHN = + 0.6 [V] ■Vtop-1
, 0[V] ■βN:βP:βW 12:1:6, and in this case, is the minimum = 1.81[V].

As described above, according to the CMOS inverter of the example shown in FIG. 1, even if the presence of nMO 313 causes manufacturing variations in pMO 314 and nMO 315 similar to those of the conventional example shown in FIG. Fluctuations can be suppressed within the range of 1.81 to 2.38 [V]. In addition, in the case of the conventional example shown in FIG. 11, as mentioned above, it is 1.36 to 2.82 [V].

Moreover, FIG. 2 shows a CMO3-NAND circuit, and in the figure,
21 and 22 are signal input terminals, 23 is a power supply line, and 24 is an enhancement type nMOS that serves as a load transistor.
, 25 and 26 are enhancement type MOs serving as load transistors; 27 and 28 are enhancement type nMOS serving as drive transistors; and 29 is a signal output terminal. In this CMO3-NAND circuit, the nMO327 and 28 constitute a drive circuit section, the 9MO325 and 26 constitute a first load circuit section, and the nMO324 constitute a second load circuit section.

According to the CMO3-NAND circuit shown in FIG. 2, 9
Due to the presence of MO324, 9MO325,26, nM
Even if manufacturing variations occur in O324, 27, and 28, variations in the threshold voltage VT of the circuit can be suppressed to a small level.

Therefore, when constructing a CMO3 type semiconductor integrated circuit device, the semiconductor integrated circuit device of this first embodiment, that is,
The CMOS inverter in the example in Figure 1 and the CMO3- in the example in Figure 2
If a CMO3 type semiconductor integrated circuit device including a logic gate such as a NAND circuit is applied, the incidence of defective chips can be reduced, that is, the yield can be improved.

2nd (3) FIG. 3 shows the main parts of a CMO3 type semiconductor integrated circuit device which is a second embodiment of the present invention. is used only for the input circuit, and the rest is placed at the bottom of the tank as before.In the figure, 31 is the semiconductor integrated circuit device main body;
32 is an external bin, and 33 is an internal circuit.

According to the second embodiment, even if manufacturing variations occur, variations in the threshold voltage required for the input stage of the semiconductor integrated circuit device can be suppressed to a minimum.

3 4 5 The third embodiment is an attempt to apply the first invention to an NMO3 type semiconductor integrated circuit device, and in this third embodiment, the logic gate is, for example, a fourth
The bottom of the tank is placed as shown in the figure and FIG.

Here, FIG. 4 is an example of an NMOS inverter,
In the figure, 41 is a signal input terminal, 42 is a power supply line, and 43 is an enhancement type nMOS that serves as a load transistor.
, 44 is a depletion type nMOS serving as a load transistor, 45 is an enhancement type nMOS serving as a driving transistor, and 46 is a signal output terminal.

In addition, in this NMOS inverter, nMOS43 is a drive circuit section, nMO344 is a first load circuit section, and nMOS
43 constitutes a second load circuit section.

According to the NMOS inverter of the example in FIG.
Due to the presence of S43, enhancement type nMOS
Even if manufacturing variations occur in the nMO 344 of the 43.45 and depletion type, variations in the threshold voltage v of the circuit can be suppressed to a small level.

Moreover, FIG. 5 is an example of an NMO3-NAND circuit,
In the figure, 51 and 52 are signal input terminals, 53 is a power line, and 54
is an enhancement type n that forms a load transistor.
MO3, 55 are load transistors, depletion type nMO3, 56, 57 are drive transistors, and enhancement type nMO3, 58 are signal output terminals. In addition, in this NMO3-NAND circuit,
The nMOS 43 and 57 constitute a drive circuit section, the nMOS 43 constitutes a first load circuit section, and the nMOS 43 constitutes a to-type load circuit section.

According to the NMO3-NAND circuit shown in FIG. 5, n
Due to the presence of MO354, the enhancement form of nM
O354, 56, 57 and depletion type nMOS
Even if manufacturing variations occur in 43, variations in the threshold voltage VT of the circuit can be suppressed to a small level.

Therefore, when constructing an NMO3 type semiconductor integrated circuit device, the semiconductor integrated circuit device of this third embodiment, that is,
The NMOS inverter in the example in Figure 4 and the NMO3- in the example in Figure 5
If an NMO3 type semiconductor integrated circuit device including a logic gate such as a NAND circuit is applied, the incidence of defective chips can be reduced, that is, the yield can be improved.

4 6 7) The fourth embodiment is an attempt to apply the first invention to a PMO3 type semiconductor integrated circuit device, and in this fourth embodiment, the logic gate is, for example, 6
It is constructed as shown in FIGS.

Here, FIG. 6 is an example of a PMOS inverter,
In the figure, 61 is a signal input terminal, 62 is a power supply line, and 63 is an enhancement type pMO8 that serves as a load transistor.
, 64 is a depletion type transistor 9MO3, 65 is an enhancement type transistor 9MO3, and 66 is a signal output terminal.

In addition, in this PMOS inverter, pMO365 is a drive circuit section, pMO364 is a first load circuit section, and 9MO3
63 constitutes a second load circuit section.

According to the PMOS inverter of the example in FIG.
Due to the presence of 363, the enhancement form of 9MO3
Even if manufacturing variations occur in the pMO 63, 65 and the depletion type pMO 364, variations in the threshold voltage Vt of the circuit can be suppressed to a small level.

Moreover, FIG. 7 is an example of a PMO3-NAND circuit,
In the figure, 71 and 72 are signal input terminals, 73 is a power line, and 74
is an enhancement type 9 that forms a load transistor.
MO3, 75 are depletion type transistors; MO3, 76, 77 are drive transistors; enhancement type MO3, 78 are signal output terminals. In addition, in this PMO3-NAND circuit,
9 MOs 76 and 77 constitute a drive circuit section, PMOS 75 constitutes a first load circuit section, and 9 MOs 374 constitutes a second load circuit section.

According to the PMO3-NAND circuit shown in FIG. 7, 9
Due to the presence of MO374, the enhancement form of 9M
O374,76,77 and depletion form pMO3
Even if manufacturing variations occur in the circuit 75, variations in the threshold voltage V of the circuit can be suppressed to a small level.

Therefore, when constructing a PMO3 type semiconductor integrated circuit device, the semiconductor integrated circuit device of this fourth embodiment, that is,
The PMOS inverter in the example in Figure 6 and the PMO5- in the example in Figure 7
If a PMOS type semiconductor integrated circuit device including a logic gate such as a NAND circuit is applied, the incidence of defective chips can be reduced, that is, the yield can be improved.

5th 8th Embodiment The fifth embodiment is an attempt to apply the second invention of the present invention to an 0MO9 type semiconductor integrated circuit device that performs low voltage operation. is configured, for example, as shown in FIG.

Here, FIG. 8 shows an example of a CMOS inverter,
In the figure, 81 is a signal input terminal, 82 is a power supply line, and 83 is an enhancement type nMO3 which is a load transistor.
, 84 and 85 are load transistors; 86 is an enhancement type nMO3; 86 is a drive transistor; and 87 is a signal output terminal. Note that in this CMOS inverter, nM.

S86 constitutes a drive circuit section, 9MO385 constitutes a first load circuit section, and nMO383 and pMO384 constitute a second load circuit section.

According to such a CMOS inverter, the source voltage of 9MO385 is reduced to Vc due to the presence of 9MOs84.
c can be used for low voltage operation, e.g.
cc=1.5 [V].

Also in this case, due to the presence of nM O383, even if manufacturing variations occur in 9MOs84.85 and nMOs83.86, fluctuations in the threshold voltage Vt of the circuit can be suppressed to a small level.

Therefore, when configuring a CMO3 type semiconductor integrated circuit device that operates at a low voltage, the semiconductor integrated circuit device of this fourth embodiment, that is, the CMO8 type semiconductor integrated circuit device including a logic gate such as the CMOS inverter shown in the example in FIG. By applying this semiconductor integrated circuit device, it is possible to reduce the incidence of defective chips, that is, to improve yield.

Note that the CMOS inverter shown in the example of FIG. 8 can be used only for the input circuit. In this case, even if manufacturing variations occur, variations in the threshold voltage required for the input stage of the semiconductor integrated circuit device can be suppressed to a minimum.

6 9゛The sixth embodiment is an attempt to apply the second invention of the present invention to an NMOS type semiconductor integrated circuit device that performs low voltage operation, and in this sixth embodiment, the logic gate is , for example, is configured as shown in FIG.

Here, FIG. 9 is an example of an NMOS inverter,
In the figure, 91 is a signal input terminal, 92 is a power supply line, and 93 is an enhancement type nMO3 which is a load transistor.
, 94 and 95 are depletion type nMO3 which are load transistors, 96 is an enhancement type nMO3 which is a driving transistor, and 97 is a signal output terminal.

Note that in this NMOS inverter, nMO396 is a drive circuit section, nMOS95 is a first load circuit section, and nMOS 95 is a first load circuit section.
MOs 393 and 94 constitute a second load circuit section.

According to such an NMOS inverter, the presence of nMO394 reduces the drain voltage of nMO895 to V.
CC can be used for low voltage operation, e.g.
Vcc=1.5 [vl.

Also in this case, due to the presence of the nMO 393, even if manufacturing variations occur in the enhancement type nMOs 893 and 96 and the depletion type nMOs 894 and 95, variations in the threshold voltage v of the circuit can be suppressed to a small level.

Therefore, when constructing an NMOS type semiconductor integrated circuit device that operates at a low voltage, the semiconductor integrated circuit device of this sixth embodiment, that is, the NMOS type semiconductor integrated circuit device including the logic gate such as the NMOS inverter shown in the example of FIG. By applying this semiconductor integrated circuit device, it is possible to reduce the incidence of defective chips, that is, to improve yield.

7 10 The seventh embodiment is an attempt to apply the second invention of the present invention to a PMO8 type semiconductor integrated circuit device that performs low voltage operation, and in this seventh embodiment, the logic gate is For example, it is configured as shown in FIG.

Here, FIG. 1O shows an example of a PMOS inverter, in which 101 is a signal input terminal, 102 is a power supply line, and 10 is an example of a PMOS inverter.
3 is an enhancement type 9MO3, 104, 105 is a load transistor, 9MO3 is a depletion type, and 106 is an enhancement type 9MO3, 107 is a drive transistor.
is a signal output terminal. In this PMOS inverter, 9MOs 3106 constitutes a drive circuit section, 9MOs 105 constitutes a first load circuit section, and pMOs 3103 and 104 constitute a second load circuit section.

According to this PMOS inverter, the presence of 9MO8104 lowers the source voltage of pMO3105 to -V. Since the voltage can be set to C, low voltage operation can be achieved, for example, Vcc=1.5 [V].

Also in this case, even if manufacturing variations occur in enhancement type 9MO8103, 106 and depletion type pMO3104, 105 due to the presence of pMO3103, the threshold voltage V of the circuit
Fluctuations in T can be kept small.

Therefore, when configuring a PMO8 type semiconductor integrated circuit device that operates at a low voltage, the semiconductor integrated circuit device of the seventh embodiment, that is, the PMO8 type including logic gates such as the PMOS inverter shown in the example of FIG. By applying this semiconductor integrated circuit device, the incidence of defective chips can be reduced, that is,
Yield can be improved.

E1-4 In the above embodiments, only inverters and two-man type NAND circuits were mentioned as logic gates, but other logic gates such as NAND circuits with three or more manpower, NOR circuits, composite gate circuits, etc. Based on the same concept as the inverter and two-person type NAND circuit shown in Figures 1 and 3 to 10, the circuit is configured so that fluctuations in the threshold voltage of the circuit due to manufacturing variations can be suppressed to a small level. be able to.

[Effect of the invention] According to the present invention, the following effects can be obtained.

First, according to the semiconductor integrated circuit device (first invention) according to claim 1, even if manufacturing variations occur in one type of transistor and another type of transistor, the second load circuit section can be configured. The presence of one type of transistor can suppress fluctuations in the threshold voltage of the circuit, reduce the incidence of defective chips, and improve yield.

Next, according to the semiconductor integrated circuit device (second invention) according to claim 2, due to the presence of another type of transistor constituting the second load circuit section, it is possible to operate at a low voltage, and In this case as well, due to the presence of type - transistors constituting the second load circuit section, even if manufacturing variations occur between one type of transistor and the other type of transistor, fluctuations in the threshold voltage of the circuit can be prevented. It is possible to keep the size small, reduce the number of defective chips, and improve yield.

Furthermore, according to the semiconductor integrated circuit device according to claim 3, even if manufacturing variations occur between one type of transistor and another type of transistor, at least the threshold voltage required for the input stage of the semiconductor integrated circuit device can be maintained. It is possible to suppress fluctuations in the number of chips, reduce the number of defective chips, and improve yield.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a CMOS inverter used in the first embodiment of the present invention, and FIG. 2 is a circuit diagram showing a CMOS-N inverter used in the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing the essential parts of the second embodiment of the present invention; FIG. 4 is a circuit diagram showing the NMOS inverter used in the third embodiment of the present invention; The figure shows NMO3-N used in the third embodiment of the present invention.
A circuit diagram showing an AND circuit, FIG. 6 is a circuit diagram showing a PMOS inverter used in the fourth embodiment of the present invention, and FIG. 7 is a circuit diagram showing a PMOS inverter used in the fourth embodiment of the present invention.
A circuit diagram showing an AND circuit, FIG. 8 is a circuit diagram showing a CMOS inverter used in the fifth embodiment of the present invention, and FIG. 9 is a circuit diagram showing an NMOS inverter used in the sixth embodiment of the present invention. , FIG. 10 is a circuit diagram showing a PMOS inverter used in the seventh embodiment of the present invention, FIG. 11 is a circuit diagram showing a conventional CMOS inverter, FIG. 12 is a circuit diagram showing a conventional NMOS inverter, Fig. 13 is a circuit diagram showing a conventional PMOS inverter, Fig. 14 is a circuit diagram showing a conventional CMOS-NAND circuit, Fig. 15 is a circuit diagram showing a conventional NMO3-NAND circuit, and Fig. 16 is a circuit diagram showing a conventional PMOS-NAND circuit. FIG. 2 is a circuit diagram showing a NAND circuit. CMOS-NAND circuit used in the first embodiment Figure 2 Main part of the second embodiment Figure 3 NMOS NAND circuit used in the third embodiment PMO3-NAND circuit used in the fourth embodiment Fifth CMOS inverter used in the embodiment Figure 8 NMOS inverter used in the sixth embodiment Figure 9 PMOS inverter used in the seventh embodiment Figure 10 Conventional CMOS inverter Figure 11 Conventional NMOS inverter 12 Figure Conventional PMOS inverter Figure 13

Claims (2)

[Claims] (1) Between one voltage source and the other voltage source, a drive circuit section consisting of one type of MOS transistor, a first load circuit section consisting of another type of MOS transistor, and a first load circuit section consisting of one type of MOS transistor. A semiconductor integrated circuit device comprising a logic gate formed by hierarchically connecting a second load circuit section made of MOS transistors. (2) Between one voltage source and the other voltage source, a drive circuit section consisting of one type of MOS transistor, a first load circuit section consisting of another type of MOS transistor, and a first load circuit section consisting of one type of MOS transistor. MOS transistors and other types of M
A semiconductor integrated circuit device comprising a logic gate formed by hierarchically connecting a second load circuit section consisting of a parallel circuit of OS transistors.