JPH0317889A - Dynamic semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce a layout area and to attain high integration by comprising a dynamic semiconductor memory so as not to select a capacitor selected only for readout and write for the purpose of performing a refresh operation. CONSTITUTION:When the readout and write are performed, a transistor(TR) Q7 is turned on and a TR Q8 is turned off. Therefore, since no output of a word line driving circuit 12 is transmitted to a word line 2 or 4 when the same address is generated from a refresh address generating circuit 16, the refresh operation can be prohibited. Also, when the refresh operation is performed, the TR Q7 is turned off and the TR Q8 is turned on. Therefore, no output of a circuit 11 is transmitted to a word line 1 or 3 even when the same address is generated, and the word line is prevented from going to 'H', however, a bit line to be connected to a data line is switched with a bit line switching circuit 17. Thereby, the readout and write can be performed without interrupting refresh. In such a way, the capacitance of the capacitor can be reduced to the half, and the high integration can be attained by reducing the layout area.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a dynamic semiconductor memory device.

2. Description of the Related Art In recent years, with the development of electronic equipment, the capacity of semiconductor memory devices has been increasing. Dynamic type semiconductor memory devices that allow random access have a high degree of integration and are suitable for increasing capacity, but on the other hand, refresh operations are required, making the system complex.

On the other hand, the static type is not suitable for increasing the capacity, but it can be operated with a simple system, and pseudo-static type semiconductor memory devices using dynamic type storage elements are being developed.

A conventional dynamic semiconductor memory device will be explained below. FIG. 2 is a circuit diagram of a conventional dynamic semiconductor memory device. C3 is a capacitor, Q Is #
Q +s are parallel transistors whose sources are commonly connected to one end of the capacitor of C3. Word & I
I3 is a word line connected to the gate of Q+s, word line 6 is connected to the gate of QI6, and bit line 3 is connected to the gate of QC.
The bit lines 4 and 4 are bit lines connected to the drains of QCs, respectively. The bit line 3 and the bit line 4 have a sense amplifier 3 and a sense amplifier 4, respectively, and the bit line 4 is connected to a column address decoder via a transfer gate of QI7.

Word line 5 and word line 6 are connected to a row address decoder and a refresh address decoder, respectively.

Further, the signals of the row address decoder and the refresh address decoder are compared by an address comparator, and enter the bit line short circuit together with the write mode signal "W". As mentioned above, conventional dynamic semiconductor memory devices have two word lines and two bit lines for each capacitor, making it possible to perform refresh operations simultaneously with read and write operations. It has become.

The operation will be explained below. When writing data, word line 5 is selected by the row address decoder and set to “H”.
When the level is reached, the transistor QCs whose gate is connected to the word line 5 is turned on.

Then, when the bit line 4 is selected by the column address decoder, the transfer gate Ql7 is turned on and the data inputted onto the data line is written as a potential through the bit line 4 into the capacitor C3. Capacitor C3 has a memory function by holding an amount of charge which is the product of input potential and capacitance. When the word line 6 is selected by the refresh address decoder during such a write operation, an attempt is made to simultaneously perform a write operation and a refresh operation on the capacitor C3. For example, when writing data different from the stored data to a capacitor that is to be refreshed, a conflict occurs between the sense amplifier 3 that latched the stored data and the written data, resulting in data destruction. Therefore, when attempting to perform a write operation and a refresh operation on one capacitor at the same time, the address comparison circuit detects that the addresses match, the bit line short circuit shorts the bit lines, and the write operation is performed. Conflicts between operations and refresh operations are resolved. Next, in the case of reading, when the word line is selected by the row address decoder and becomes "H" level, the transistor Q+s connecting the gate to the word line 5 is turned on, and the capacitor C3 and the bit line 4 are connected. The potential held in the capacitor C3 and the bit line potential are brought into equilibrium by the capacitance ratio between the capacitor C3 and the bit line stray capacitance C3, causing a change in the bit line potential. This potential change is amplified by the sense amplifier 4.

Then, bit line 4 is selected by the column address decoder.
When is selected, transfer gate QI7 turns on,
Data on bit line 4 is read to the data line. During such a read operation, the word line 6 is selected by the refresh address decoder, and a read operation and a refresh operation are simultaneously performed on one capacitor.

Therefore, in the conventional dynamic semiconductor memory device, the capacitance of the capacitor is made large enough to ensure a sufficient signal amount even when the bit line stray capacitance Ca doubles. Therefore, even if it is attempted to simultaneously perform a read operation and a refresh operation on one capacitor, the operation can be performed without any problem.

Problems to be Solved by the Invention In the above-mentioned conventional technology, when data reading and refreshing operations are performed on the same capacitor, two transistors QCs and Q+s connected to one capacitor C3 turns on. At this time, the potential is balanced between the capacitance of capacitor C3 and the sum of the two bit line capacitances, so the potential change of the bit line is approximately 1 compared to when a read operation or a refresh operation is performed alone.
/2, and it is impossible to send sufficient signals to two bit lines. In order to send sufficient signals to two bit lines, a capacitor capacity approximately twice as large as that of a dynamic semiconductor memory device with one transistor and one capacitor is required.

Furthermore, when attempting to perform a refresh operation on the same capacitor at the same time as writing, in a conventional dynamic semiconductor memory device, writing is performed by shorting the bit lines. In this case as well, to write,
Since it is necessary to sufficiently transmit signals to the two bit lines, the driving capacity of the peripheral circuits must be designed to be large.

Such an increase in capacitance of a capacitor and an increase in the size of a drive circuit lead to an increase in layout area, which has been an obstacle to higher integration.

The present invention solves the above-mentioned conventional problems, and is better than conventional dynamic semiconductor memory devices by preventing the capacitors selected for reading and writing from being selected for refresh operations. The present invention provides a dynamic semiconductor memory device that can be designed with a small area.

Means for Solving the Problems In order to solve the above-mentioned problems, the dynamic semiconductor memory device of the present invention provides a dynamic semiconductor memory device that is capable of solving the problems when attempting to perform a refresh operation simultaneously with read and write operations for one dynamic memory circuit. , two word lines are “H” at the same time
A multiple selection prevention circuit has been installed to prevent this from occurring. Furthermore, a bit line switching circuit is provided to enable input/output from either of the two bit lines.

Effect: With this configuration, it is possible to prevent the capacitors selected for read and write operations from being selected for refresh operations at the same time, and the capacitance of the capacitor of each dynamic memory circuit can be reduced compared to that of conventional dynamic semiconductors. It becomes possible to design with approximately 172 storage devices.

Examples Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a dynamic semiconductor memory device of the present invention. C1 is a capacitor, Q+. Q2 is a parallel transistor whose sources are commonly connected to one end of the capacitor of CI. Word line 1 is a word line connected to the gate of Q1, and word line 2 is connected to the gate of Q2. Bit &111 is a bit line connected to the drain of Q2, and bit line 2 is connected to the drain of QI. The word line 1 is connected to a read line drive circuit 1 via a row address decoder and a multiple selection prevention circuit, and the word line 2 is connected to a word line drive circuit 2 via a refresh address decoder and a multiple selection prevention circuit. The multiple selection prevention circuit controls the transmission of the output of the word line drive circuit to the row address decoder or the refresh address decoder using a signal from the row address input circuit and a signal from the refresh address generation circuit.

Bits M1 and 2 have sense amplifier 1 and sense amplifier 2, respectively. Further, bit lines 1 and 2 are connected to a data line via a bit line switching circuit. The bit line switching circuit determines the bit line to be connected to the data line based on the output signal of the multiple selection prevention circuit.

The operation of the multiple selection prevention circuit and bit line switching circuit of the dynamic semiconductor memory device of the present invention will be explained below with reference to the drawings. The multiple selection prevention circuit is configured to prevent word line 2 or word line 3 from being selected by the refresh address decoder and going to "H" level at the same time that word line 1 or word line 2 is selected by the row address decoder. It is a circuit. Q when on standby
? ．． Although Qs is in the on state, no address is generated from the row address generation circuit, so no word line is generated. Next, when attempting to read or write, Q7 is turned on and Q8 is turned off. Therefore, if the same address is generated from the refresh address generation circuit, the output of the word line drive circuit 2 will be changed to the word line 2.
Otherwise, the refresh operation is prohibited because it is not transmitted to the word line 4. Next, during the refresh operation, Q7 is turned off and Q8 is turned on. Therefore, when the same address is generated from the row address input circuit, the output of the word line drive circuit 1 is not transmitted to the word line 1 or word line 3, so the word line is set to "H" for read and write operations. ”
It is prohibited to become

The bit line switching circuit is a circuit that switches bit lines connected to data lines. During read and write operations, Q9 in the bit line switching circuit is turned off and Q+o is turned on, so that the data line is connected to the bit line 2 and data is input/output through the bit line 2.

During refresh operation, Q9 is turned on and Q+o is turned off. As a result, the bit line connected to the data line is switched, and even if an address is generated from the row address input circuit during a refresh operation and a read or write operation is attempted, the word line is set to "H" by the multiple selection prevention circuit. Even if the bit line connected to the data line is prohibited, read and write operations can be performed without any problem by switching the bit line connected to the data line.

Effects of the Invention As described above, according to the present invention, by providing a multiple selection prevention circuit, capacitors selected for a data read or write operation are prohibited from being selected simultaneously for a refresh operation. can do. Also,
By providing a bit line switching circuit, when attempting to read or write data to a capacitor during a refresh operation, it becomes possible to perform the data read or write operation without interrupting the refresh operation. As a result, we have realized a dynamic semiconductor memory device that can be designed with approximately 1/2 the capacitance of a conventional dynamic semiconductor memory device, which allows for a smaller layout area and higher integration. can.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a dynamic semiconductor memory device of the present invention, and FIG. 2 is a circuit diagram of a conventional dynamic semiconductor memory device. 1...Word line 1, 2...Word line 2
, 3... Word line 3, 4... Word line 4, 5... Bit line 1, 6... Bit line 2, 7... ...Data lines 1, 8...Column address decoder, 9...Sense amplifier 1,
10...Sense amplifier 2, 11...Word line drive circuit l, 12...Word line drive circuit 2, 13...Row address decoder, 14...
...Refresh address decoder, 15...
... Row address input circuit, 16 ... Refresh address generation circuit, 17 ... Bit line switching circuit, 18 ... Dynamic storage circuit, 19
...Multiple selection prevention circuit, Q1 to Q8...
・N-channel MOS transistor, C1-C2...
...Capacitor, V1 ...Reference potential, Ca
... Bit line stray capacitance, 21 ... Column address decoder, 22 ... Row address decoder, 23 ... Refresh address decoder, 24 ...・Data lines 2, 25...Word lines 5, 26...Word lines 6, 27...
...Bit line 3, 28...Bit line 4, 29...
...Sense amplifier, 30...Sense amplifier 4, 31...Bit line short circuit, 32.
...Address comparison circuit, 33...Dynamic memory circuit, Q+s to Q+7...N channel MOS transistor, Q+s...P channel MOS} transistor, C3... ...Capacitor, Ca...Bit line stray capacitance.

Claims (1)

[Claims] a parallel first capacitor whose one end is connected to a reference potential; and a parallel first capacitor whose sources are commonly connected to one end of the capacitor.
a first word line connected to the gate of the first transistor, a second word line connected to the gate of the second transistor, and a drain of the first transistor; a first bit line connected to the second bit line, a second bit line connected to the drain of the second transistor, a first sense amplifier connected to the first bit line, and a second sense amplifier connected to the second bit line. Signals from the sense amplifier, the row address generation circuit, and the refresh address generation circuit are input, and the signals are connected to the first bit line and the second bit line via a bit line switching circuit that determines the bit line involved in data input/output. a column address decoder connected to the first bit line and the second bit line via the connected data line and the bit line switching circuit; and a column address decoder connected to the first word line and connected to the first word line. A word line drive circuit 1 to be driven and the word line drive circuit 1
a row address decoder connected to the word line 1 via a row address decoder for selecting a word line to be driven; a word line drive circuit 2 connected to a second word line and driving the second word line;
a refresh address decoder connected to the word line 2 via the word line drive circuit 2 and selecting a word line to be driven, and comparing addresses generated by the row address generation circuit and the refresh address generation circuit; 1. A dynamic semiconductor memory device comprising a multiple selection circuit that sends a signal to a row address decoder and a refresh address decoder so as not to simultaneously select two word lines connected to the same capacitor via a transistor.