JPH0317651U - - Google Patents
Info
- Publication number
- JPH0317651U JPH0317651U JP1989078566U JP7856689U JPH0317651U JP H0317651 U JPH0317651 U JP H0317651U JP 1989078566 U JP1989078566 U JP 1989078566U JP 7856689 U JP7856689 U JP 7856689U JP H0317651 U JPH0317651 U JP H0317651U
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- pair
- flop
- flip
- constituted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Memories (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989078566U JPH0317651U (en:Method) | 1989-07-03 | 1989-07-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989078566U JPH0317651U (en:Method) | 1989-07-03 | 1989-07-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0317651U true JPH0317651U (en:Method) | 1991-02-21 |
Family
ID=31621955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989078566U Pending JPH0317651U (en:Method) | 1989-07-03 | 1989-07-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0317651U (en:Method) |
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1989
- 1989-07-03 JP JP1989078566U patent/JPH0317651U/ja active Pending