JPH03175066A - Data buffer device - Google Patents

Abstract

PURPOSE:To receive data from a data sender as long as storage means has an empty area by providing informing means for informing a gist to a data sender if the empty area of the storage means is eliminated at the time of receiving data transmitted from the sender in a data buffer device. CONSTITUTION:If a buffer full state is determined in a start byte reception or data block reception, a lighting reception display lamp 13 is flashed to inform a user of interruption of reception thereby to inform the buffer full state. That is, a buffer full display lamp 16 is lit to inform the user of the buffer full state, an opposite computer control signal line -ERROR-C and an opposite computer control line PE-C are negated to inform avoid of 'no paper state' by a printer buffer to a computer. Further, the lamp 16 is deenergized to forcibly erase data block received until it becomes the buffer full state.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transmission device such as a computer,
For example, the present invention relates to a data buffer device installed between a data receiving device such as a printer for the purpose of efficiently transmitting and receiving a large amount of data to and from the data receiving device.

[Conventional technology]

A typical signal line for transmitting and receiving data between a computer and a printer is shown in FIG. In the figure, D
ATAO-DATA7 is a signal line carrying information of each bit constituting byte data (parallel data) sent from the computer to the printer, and is also a control signal line sent from the computer to the printer. -5TRO
When BE is in “Low state (asserted state), the above DATA
This indicates that valid data exists on the O-DATA7 signal line.

-ACKNLG is a control signal line sent from the printer to the computer, and when it is in the "Low" state (asserted state), it indicates that the byte data reception process has been completed and the next byte data is ready to be received. . In addition, when the control signal line BUSY sent from the printer is in the "High" state (asserted state), it indicates that it is impossible to receive byte data, and conversely, it is in the "Low" state (negate state).
Indicates that byte data reception is possible. 5
LCT is a control signal line sent by the printer and is “High”
state (asserted state) indicates that the printer is in the selected state. -ERROR is a control signal line sent by the printer, and when it is in the "Low" state (asserted state), it indicates that the printer is in an error state. PE is also a control signal line sent from the printer, and if this signal line is in a "High" state (asserted state) when the -ERROR signal line is asserted, it indicates that the printer is out of paper. . -INIT is a control signal line sent from the computer to the printer, and when set to "Low" state (asserted state), the printer is set to the initial state.

-AUTOFEEDXT is a control signal line sent from the computer to the printer, and when set to "Low" state (asserted state), the printer automatically performs one administrative action upon reception of the carriage return code.

However, this signal line -AUTOFEEDXT is monitored only in the initial state of the printer. Similarly, the control signal line -5LCTIN sent from the computer is also monitored only in the initial state of the printer, and is in the "Low" state (
(asserted state), the printer outputs DCI or DC3.
Ignore control codes.

Next, a general flow of transmitting and receiving print output data using the signal lines between the computer and the printer shown in FIG. 58 will be explained. FIG. 59 is a timing chart of main signal lines. The print output data transmission operation flow on the computer side is as shown in FIG.
” state to indicate that the transmission operation is not currently in progress, -AUT is set in step 5IO-2 and step 510-3.
Set the OFEEDXT signal line and the 13LCTIN signal line to H.
igh' or “Low” state, step 5
IO-4 and step 5 IO-5 sends a "Low" pulse to the -INIT signal line to initialize the printer. For actual byte data transmission operation, step 5 IO
-6, the printer is in the selected state, step 5
After confirming in advance that the printer is not in an error state at IO-7 and that the printer is ready to receive data at step 5IO-8, the byte data constituting the print output data is sent to DATAO-9 at step 5LO-9.
Send to DATA7 signal line. And step 5IO-
10 and step 510-11, a "Low" pulse is sent to the 1-8 TROBE signal line to send a byte to the printer.
Notify that data has been sent. After that, the computer monitors the -ACKNLG signal line in step 5IO-12, and when it becomes a "Low state (asserted state)", it determines that the transmission operation of one byte data is completed and sends a 5IO signal line.
At step -13, it is determined whether all the byte data constituting the print output data has been transmitted. If the print output data has not been completed, the process returns to step 5IO-6 and the byte data transmission operation is repeated again.

On the other hand, the flow of the print output data reception operation on the printer side is as shown in FIG. Then, -AUTO is set in step 5ll-2 and step 5ll-3.
Save the states of the FEEDXT signal line and -3LCTIN signal line. Then in step 5ll-4 -ACK
Set the NLG signal line to “High” state (negate state),
The 5LCT signal line is set to “High” state (asserted state) in step 5ll-5, and BUSY is set in step 5ll-6.
The signal line is set to "High" state (asserted state), the PE signal line is set to "Low" state (negate state) at step 5ll-7, and the -ERROR signal line is set to 'High' state (negate state) at step 5ll-8. , and notifies the computer that the printer is currently in the selected state and is not in an error state, but reception is not possible.For the actual byte data reception operation, step 5ll-9 to step 5ll- By 11-
While sending a 'Low' pulse to the ACKNLG signal line,
After setting BUSY to “Low” state (negate state) to indicate that Blink is ready for reception, step S
1-5 sent from the computer in 1-12
Monitor the TROBE signal line, and if it becomes "Low" state (asserted state), first, in step 5ll-13, BU
After setting the SY signal line to "High" state (asserting state) to inform the computer that the printer is currently processing reception and cannot receive the next byte data, the byte data is transferred in step 511-14. DATAO-DA
It reads from the TA7 signal line and performs entry operation or actual printing operation. After that, if no error occurs in step 5ll-15, the process returns to step 5ll-9 and restarts the reception operation of the next byte data. When an error occurs, in step 5ll-16, connect the -ERROR signal line to “
Set it to Low state (asserted state) and then proceed to step 5.
If the out-of-paper state is detected in step 11-17, the PE signal line is set to the "High" state (asserted state) in step 511-18, and then the reception operation is ended.

A conventional printer buffer device was used as shown in FIG. 62. In the figure, lOO is a computer which is a data sending device, 101 is a printer/buffer device main body, 102 is a printer which is a data receiving device, 1
03 is a cable that connects the computer and the printer buffer device, 104 is a cable that connects the printer and the printer/buffer device, 105 is a commercial AC power source, and 106 is an AC power cable.

That is, the conventional printer/buffer device 101 uses a computer 1001 as a data sending device and a printer 10 as a data receiving device to send and receive data.
2 using dedicated signal cables 103 and 104, and a dedicated AC power cable 106 for receiving commercial AC power.

After connecting in this manner, when print output data is output from the computer 100, which is the data sending device, via the dedicated cable 103, the printer/buffer device 102 receives this data and stores it in an internal buffer. After that, the data is sent to the printer 102, which is a data receiving device, via a dedicated cable 104.

The method of transmitting and receiving print output data at this time is exactly the same as the method of transmitting and receiving the print output data between the general computer and printer described above. In other words, when receiving print output data from a computer, which is a data sending device, the printer
The buffer device emulates the receiving operation of the general printer described above, and when transmitting print output data to the printer, which is the data receiving device, the printer buffer device emulates the sending operation of the general computer described above. It's emulating.

However, when emulating a general printer operation, the "out of paper" state of the printer is emulated by the internal buffer remaining capacity of the printer buffer device. In other words, the remaining internal buffer capacity of the printer buffer device is O.
When , it is “out of paper”.

In reality, the conventional printer buffer device simultaneously transmits and receives the print output data. The processing procedure is as shown in FIG. That is, first, in step 563-1, the internal buffer remaining capacity is determined. If remaining capacity = 0, control is performed in step 56.
The process moves to step 3-2, the PE signal line is set to "High", and then the process moves to step 563-6. On the other hand, if the remaining capacity≠O, the PE signal line is set to "Low" in step 563-3, and then it is determined in step 563-4 whether data has been transmitted from the computer. If data is transmitted here, the data is received in step 563-5 and stored in the internal buffer, and then the process moves to step 563-6. Here, data reception is performed by emulating the reception operation of the general printer described above.

Next, in step 563-6, it is determined whether the printer is in a receiving state. If the printer is not ready for reception, control immediately returns to step S63-1.

On the other hand, if the printer is ready to receive data, control moves to step 563-7, where it is determined whether there is data in the internal buffer.

If there is no data, control returns to step 563-4. On the other hand, if there is data, the control moves to step S63-8, and the print output data received from the computer and stored is transmitted to the printer in a first-in first-out manner from the beginning. Here, data transmission is performed by emulating the transmission operation of the general computer described above. Control then proceeds to step 563-
9, the print output data that has been sent to the printer is immediately erased from the internal buffer, the internal buffer is organized, and the internal buffer is freed for the next received data. After this, the control returns to step 563-1.
Go back and repeat the above process.

As described above, conventional printer buffer devices transmit and receive print output data.

(The following is a blank space) [Problem to be solved by the invention] However, while the conventional printer/buffer device is receiving and storing print output data sent from a computer, which is a data sending device, the printer, which is a data receiving device, is in a ready state. As long as
Because the paper is sent to the printer using the out-of-paper method, if the printer becomes in an "out of paper" error state, the printer buffer device immediately notifies the computer of the "out of paper" error state even if there is free space in the receiving buffer. This will prohibit sending from your computer.

Like the printer buffer device, which is the data buffer device that forms the basis of this invention, when print output data is being received and stored from the computer, it is not connected to the printer and is not sent at all. In the case of an inactive device, the receiving operation from the computer can continue until the storage means runs out of free space. However, when the storage space runs out, it is necessary to notify the computer to stop sending data.

Furthermore, even if the storage means runs out of free space and the data transmission operation from the computer is stopped due to error processing, the data up to the middle of the block that was being received is stored in the storage means of the data buffer device. .

Therefore, it is necessary to perform some processing on such data.

Therefore, the purpose of the present invention is to solve the above technical problems,
To provide a data buffer device capable of receiving and storing data from a data sending device, regardless of the state of the data receiving device, as long as there is free space in storage means of the data buffer device.

A further object of the present invention is to provide a data buffer device capable of erasing only the data of a block that has been accumulated up to a halfway point when the storage means of the data buffer device runs out of free space. That's true.

[Means and operations for solving the problem] In order to achieve the above object, a data buffer device according to the present invention includes a receiving device that receives data transmitted in blocks from a data transmitting device, and A storage means for storing received data in association with a block index which is identification data, a registration means for registering the block when all data included in one block has been stored, and data of the registered block. a transmitting means for transmitting the data to the data receiving device, and during the data receiving operation,
When the storage means runs out of free space for storing received data (buffer full state), the apparatus is characterized in that it includes notification means for notifying the data transmission device of this fact.

According to the present invention, when the storage means runs out of free space during the reception operation of data transmitted from the data sending device, the data receiving device can be operated by the data receiving device. Regardless of the state, as long as there is free space in the storage means of the data buffer device, data can be received from the data sending device.

Such a data buffer device may include display means for displaying a message when the buffer is full. Further, the registration means may be capable of registering a block in which intermediate data is stored as one block when the buffer becomes full, and the registration means may register the block index corresponding to the registered block. It may also include display means for displaying.

Further, another data buffer device according to the present invention is provided with an erasing means for erasing data of a block in which data is stored up to intermediate data when the buffer is in a full state, and when the buffer is in a full state, It is characterized by comprising a selection means for selecting and activating either the registration means or the deletion means.

In such a data buffer device, means for erasing a block containing data currently being received from the storage means in a state where there is no free space in the storage means;
A means for registering a block including data currently being received as one block in a state where the free space of the storage means is exhausted, and a means for erasing the block currently being received or said reception when the free space of the storage means is no longer available. By providing a selection means for selecting one of the registration operations for the blocks in the block, it is possible to avoid erasing all the data stored in the storage means, and to prevent data from being stored up to the middle when the storage means runs out of free space. It becomes possible to erase only the blocks containing the data that were not present.

The present invention has a first connector that can be directly fitted to a connector of a data sending device, and for receiving data from the data sending device while fitted with the connector, and a first connector that can be directly fitted to a connector of a data receiving device. It is possible to implement the present invention particularly preferably in a data buffer device comprising a second connector for transmitting data to a data sending device in a fitted state with the connector.

(The following is a blank space) [Examples] (I) Figures 1 to 57 show examples of the present invention.

FIG. 1 is an external view of a printer buffer according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. 1st
In the figure and FIG. 2, 1 is the printer buffer body;
2 is a printer port connector, 3 is a computer port connector, 4 is a reset button, 5 is a clear button, 6 is a reception start/end button, 7 is a reception interrupt button, 8 is a transmission start/end button There are 20 buttons in total, each numbered from 1 to 20, with 9 being a transmission interrupt button and 10 being a block index button. 11 is an all block selection button. 12 is a power indicator lamp, 13 is a receiving indicator lamp, 14 is a sending indicator lamp, 15 is a buffer empty indicator lamp, 16
17 is a buffer full indicator lamp, and 17 is a remaining buffer/unsent data capacity indicator lamp that can display an integer from 0 to 100. Reference numeral 18 indicates block index display lamps, of which there are 20 in total, each numbered from 1 to 20. One is a power switch.

FIG. 3 shows a block diagram of a printer buffer according to an embodiment of the present invention. In the figure, reference numeral 21 denotes a power supply section, which is composed of a battery, a regulator, and the like. 19 is a power switch that is connected to the power supply unit 21 and controls the power supply to the system; 12 is a power indicator lamp that is connected to the power supply unit 21 and indicates whether the power supply is on/off; and 22 is the operation control of the printer buffer. A CPU 23 is the central part of the CPU 22, and a bus 24 is connected to the CPU 22 and is used to exchange data with each functional block to be described later.
25 is a ROM in which an operation control program running on the CPU 22 is stored; 25 is a timer that allows the CPU 22 to recognize that a certain period of time has elapsed; 26;
is a printer port, and the data and control signal lines connected to the printer port connector 2 are
Writing is possible from the CPU 22. 27 is a computer port, which connects data and control signal lines to the computer port connector 3.
It has a function of notifying the CPU 22, using the reset interrupt signal line 28, that the -INIT C signal has become active.

28 is a reset interrupt signal line as described above.

29 is the input panel, where the reset and
Button 4, Clear button 5, Reception start/end button 6
, a reception interrupt button 7, a transmission start/end button 8, a transmission interrupt button 9, a block index button 10, and an all block selection button 11 are arranged. 30
is an input port, which allows the CPU 22 to read out the operation status (whether or not it is pressed) of each button on the input cover panel 29, and when the reset button 4 is pressed, the CPU 22 The reset interrupt signal line 28 has a function of notifying the user using the reset interrupt signal line 28.

31 is a display panel, which includes the above-mentioned receiving indicator lamp 13, sending indicator lamp 14, buffer empty indicator lamp 15, buffer full indicator lamp 16, remaining buffer/unsent data capacity indicator 17, and blocks.・
An index display lamp 18 is arranged. Reference numeral 32 denotes an output port, which enables the CPU 22 to write lighting settings (lighting/flashing/smoke-off) to each of the lamps on the display panel 31.

A main memory 33 is used partly as a storage location for a control parameter table to be described later, but mostly as a receiving buffer for print output data.

FIG. 4 is a diagram showing how the printer buffer 1 is used as an embodiment of the present invention.

The left side of the figure shows a usage pattern for receiving print output data from a computer, which is a data sending device. The printer buffer 1 is connected to the connector 41 via the computer port connector 3. After being connected in this way, the printer buffer 1 receives print output data output from the computer 40.

On the other hand, the right side of Figure 4 shows the usage of the operation of transmitting print output data to a printer, which is a data receiving device. In the figure, 42 is the printer that receives the print output data and actually prints it out. , 43 is a computer port equipped in the printer 42.
connector, and the printer buffer 1 is connected to the connector 4.
3 via the printer port 2. After being connected in this way, the computer 4
Print output data received from printer buffer 1 and stored in printer buffer 1 is transmitted from printer buffer 1 to printer 42, resulting in a printout from printer 42.

FIG. 5 shows the printer port 2 and the computer port of the printer buffer according to an embodiment of the present invention.
It shows how data and control signal lines are handled in each port 3.

As can be seen from this figure, all the signals input to each port are electrically pulled up so that they are in the "High" state when not connected (when not connected to a computer or printer). Also - AUTOFE
The two control signal lines for the computer port of EDXT C and -3LCTINC are monitored only at the time of initialization, and the information is stored in the main memory 33.

The control signal line for the computer port - INITC is treated as a reset signal line, and when a "Low" state is input from the computer, the reset interrupt signal line 28 is asserted and the CPU 22 is notified, and then the initialization operation begins. .

Among the output signal lines, the control signal line 5LCTC of the computer port is always outputted in a "High" state. Also, -INIT of the printer port
P, -AUTOFEEDXT P and -5LC
All three control signal lines of TIN P are output only at the start of a transmission operation.

FIG. 6 shows the concept of data blocks in a printer buffer according to an embodiment of the present invention.

In the figure, the data and block end codes shown in the upper row are
Blocking is when each piece of printout data sent from a computer is terminated by a predetermined block end code; in such cases, the printer buffer detects the block end code and prints out one data block. Consider it the end. That is, the print output data sent from the computer and the data blocks managed within the printer buffer have a complete one-to-l correspondence.

In the figure, the middle row shows data blocking due to a block end operation; in this case, the print output data sent from the computer is not terminated by the aforementioned block end code, and is based on the user's (operator's) predetermined procedure. The end-of-block operation according to the end-of-block operation causes the printer buffer to end one data block. As in the example shown here, the data block managed in the printer buffer may consist of multiple print output data, and unlike the case in the upper part of the figure, the print output data and data block are There is not a complete one-to-l correspondence.

The lower part of the figure shows data blocking when the receive buffer is full. In this case, the printer buffer detects that the receive buffer, which is its storage memory area, is full while receiving print output data. Then, the data block is terminated by a block interruption or termination operation according to a user's predetermined procedure.

In either case, the data block is
It is still a unit of print output data managed in a buffer.

FIG. 7 shows the contents of the main memory 33 in the printer buffer according to the embodiment of the present invention.

In the figure, the interrupt vector table is an area where pointers for CPU exception handling and external interrupt service routines are stored, and the control parameter table is an area where various parameters necessary for controlling the operation of the printer buffer are stored. , the stack area is literally the stack area for the CPU 22, and the receive buffer is the area that the printer buffer can use to store blocks of data that it receives from the computer. For convenience, the start address will hereinafter be referred to as MEMSTA and its size (number of bytes) as MEMMAX.

FIG. 8 shows an outline of the structure of the control parameter table provided on the main memory 33.

As is clear from the figure, the control parameter table is composed of four parts: an environment table, a block registration table, a reception order table, and a transmission layer table.

The environment table is a table composed of parameters representing an operating environment for controlling the operation of the printer buffer, and the block registration table is a table composed of parameters for each data block received and registered from the computer. , the reception order block is a table configured by parameters representing the reception order of data blocks received and registered from the computer, and the transmission layer block is a table configured by parameters representing the transmission order of data blocks sent to the printer. This is a table composed of

FIG. 9 shows in detail the structure of the environment table shown in FIG. 8.

In the figure, RBLOCKI is a 1-byte area in which the block index given to the next data block received from the computer or the block index of the data block currently being received from the computer is stored, ranging from 1 to 20. It can take any of the following values.

At initialization, "1" is set as a default value.

TBLOCKI is a 1-byte area that stores the block index of the next data block to be sent to the printer or the block index of the data block currently being sent to the printer, and can be any value from 1 to 20. can be taken. At initialization, "1" is set as a default value.

RBLOCKS is a 1-byte area in which the total number of data blocks currently registered and received from the computer is stored, and can take a value between 0 and 20. When this value is O, it means that there are no registered data blocks, and when it is 20, it means that the total number of registered data blocks has reached the maximum number of registered blocks. At initialization, it is cleared to "0". TBLOCKS is a 1-byte area that stores the total number of data blocks that have already been sent to the printer since the start of the sending operation, including the data block that is currently being sent to the printer, and can take a value between 0 and 20. , will never exceed the value of the registered block number RBLOCKS. That is, the following relationship holds: 0≦TBLOCKS≦RBLOCKS≦20. When this value is 0, it means that the printer buffer is not being sent to the printer, and the RB
When it matches the LOCKS value, the operating state is either that all registered data blocks have been sent to the printer, or that the last data block is being sent to the printer. It represents.

At initialization, it is cleared to "0".

UMEM is an area that can be used to store data blocks that the printer buffer receives from the computer, that is, a 3-byte (24-bit) length in which the size (total number of bytes) of the receive buffer shown in FIG. 7 is stored. In this area, the value MEMMAX is set at initialization.

RREM is a 3-byte (24-bit) memory that stores the remaining memory amount (number of bytes) obtained by subtracting the total number of bytes of the part where data blocks already received from the computer are currently stored from the total number of bytes of the receive buffer. )
In the length domain, it can take a value between O and the value of the receive buffer size UMEM (MEMMAX). This value is ME
At the time of MMAX, the remaining receive buffer amount is the maximum value, that is, “
It indicates that the buffer is empty, and when it is 0, it indicates that there is no remaining receive buffer, that is, the buffer is full.When initialized, the value MEMM is set.
AX is set.

TBLOCKSIZ is the data currently being sent to the printer.
The 3 bytes (2
This is a 4-bit) long area that can take values from 0 to the size (number of bytes) of the data block. When this value is O, it means that the data block is not being sent to the printer, and when it matches the size of the data block, the data block is not being sent to the printer. It indicates that it has finished.

It is cleared to O at initialization.

TSIZ is a 3-byte (24-bit) area in which the total size (number of bytes) of all data blocks to be sent to the printer is stored. When this value is O, it indicates that there is no data block to be sent to the printer. At initialization, it is cleared to O''.

TREM sends all data to be sent to the printer.
The 3 bytes (number of bytes) that store the remaining memory amount (number of bytes) after subtracting the total number of bytes and data that have already been sent to the printer from the total number of bytes of the block TSIZ (
24 bits) and can take values between O and the total number of byte data to be transmitted TSIZ. When this value matches the value of TSIZ, it means that not a single byte of data has been sent to the printer after the start of the sending operation, and when it is O, the sending operation of all data blocks to be sent has been completed. represents what has been done.

At initialization, it is cleared to "0".

5TATE is a 1-byte (8-bit) area in which the state of the control signal line of the computer port at the time of initialization is stored.

FIG. 1O shows the bit configuration of the initial state 5TATE of the control signal line of the computer port.

5LIN, which corresponds to bit -○ in the figure, has the control signal line,
-5LCTIN C status (“High” or “L”)
AFDXT corresponding to bit -1 has the state of the control signal line -AUTOFEEDXTC (“H
``high'' or ``low'') are stored respectively.Furthermore, 5 bits corresponding to bit-7 to bit-2 are undefined and unused.

FIG. 11 shows in detail the structure of the block registration table shown in FIG. 8.

In the figure, BLOCKADRI:1) (1≦i≦20) is
Stores the start address in the receive buffer of the data block whose block index is registered as i (or which is being received from the computer) 3
This is a byte (24 bit) long area, and BLOCKSI
Z (i) (1≦i≦20) is a 3-byte (24-bit) long area in which the size (number of bytes) of the data block is stored. BLOCKAD at initialization
The start address MEMSTA of the receive buffer is set as a default value in R(1), and BLOCKS
IZ (1) is cleared to O.

FIG. 12 shows in detail the contents of the reception order table shown in FIG. 8.

In the figure, RBLOCKSEQ (m) (1≦m≦20) is an area of 1 to 20, each of 1 byte, in which the value of the block index of the m-th data block registered for reception after the start of the reception operation is stored. Or it can take the value O. For example, RBLOCKSEQ[3) = 4 is 3
This indicates that the block index of the data block registered for reception is 4. A value of O indicates that there is no registered data block.

Due to the nature of this table representing the order, the RBLOC
When viewed in order from KSEQ (1), it is managed so that no valid data exists after the area with the value O.

That is, RBLOCKSEQ (N)≠0 and RBLO
If CKSEQ (N+1)=O, then RBLOCKSEQ (N+2]=RBL for all areas after that
OCKSEQ [N+31 =...=RBLOCKS
It is set so that EQ(20)=O.

In this case, the number of registered data blocks (the value of RBLOCKS in the environment table) is N.

Further, multiple values other than O are not set redundantly. At initialization, all areas are cleared to O. That is, RBLOCKSEQ Cm)=o (1≦m≦20)
It becomes.

FIG. 13 shows in detail the contents of the transmission order table shown in FIG. 8.

In the figure, TBLOCKSEQ [m] (1≦m≦20) is an area of 1 byte each in which the value of the block index of the m-th data block to be transmitted after the start of the transmission operation is stored. It can take a value of O. For example, TBLOCKSEQ[:3)=4 indicates that the block index of the third data block to be transmitted is 4. A value of 0 indicates that there is no block to be transmitted.

This table is TBLOC because it represents the order.
When viewed in order from KSEQ [1], it is managed so that no valid data exists after the area with the value O.

That is, TBLOCKSEQ (N)≠0 and TBLO
If CKSEQ [N+1] = O, then TBLOCKSEQ for all areas after that CN+2] 2 TB
LOCKSEQ CN+3)=...=TBLOCKS
It is set so that EQ(:20)=O.

The number of data blocks transmitted in this case (the value of TBLOCKS in the environment table) is N.

Further, multiple values other than O are not set redundantly. At initialization, all areas are cleared to 0. That is, TBLOCKSEQ (m)=0 (1≦m≦20)
It becomes.

(n) Next, the printer buffer operation control flow, which is the embodiment of the present invention explained above, will be explained in the 14th section.
This will be explained in detail with reference to FIGS.

FIG. 14 schematically shows the operation control of a printer buffer according to an embodiment of the present invention.

The outline of operation control is shown in Figure 14, when the power is turned on, when the reset button 4 is pressed during each operation, or when the control signal line -INIT C of the computer port is activated during reception operation. When this happens, the operation control of the printer buffer immediately moves to step S1 to perform an initialization operation. When the initialization operation in step S1 is completed, the process moves to step S2, where it enters an idle state and waits for an operation instruction. If the reception start/end button 5 is pressed here, step S3
and starts receiving operation. Further, when the transmission start/end button 6 is pressed in step S2, the process moves to step S4 and a transmission operation is started. Further, when the clear button 5 is pressed in step S2, the process moves to step S5 and a data block selection clear operation is started. Step S3. When the operation in either S4 or S5 is completed, the process returns to the idle state of step S2 and waits for the next operation instruction.

FIG. 15 is a flowchart showing an outline of operation control in the initialization operation of step Sl shown in FIG. 14. As shown in FIG. 15, the initialization operation described above is first performed in step 51-1 by connecting the computer to the port 27.
and the output side control signal line of each of the printer ports 26.

The output side control signal line and its status (“High
h” or “Low”) is as follows.

(1) Computer port control signal line - ACKNL
G C4-“High”EUSY C+”High
” PE C4-Low -ERRORC←“High” (2) Printer port control signal line -5 TROBE P←“High” -INIT P 4-”High” -AUTOFEEDXT P+-“High”-5L
CTIN P+"High" Here, (1) In the setting of the computer port control signal line, the printer buffer is not out of paper, but BUSYC is set to "High" to indicate to the computer that it is in a busy state. ing. On the other hand, (2) the setting of the printer port control signal line indicates that the printer buffer is not sending print output data to the printer.

Next, proceed to step 5L-2 (against computer)
27 (7) Input 111 m signal line - AUTOFEEDX
TC and -5LCTIN C status (“High”
or "Low") and stores the information in 5TATE in the environment table (FIG. 9). That is, AFDXT←−AUTOFEEDXT C3LIN
Perform the operation ←-3LIN C.

Next, the process proceeds to step 51-3, and settings for each display lamp on the display panel 31 are performed. Display lamps and their display states to be set here (“on”, “blinking”, or “off”)
is as follows.

Receiving indicator lamp 13←“off” Sending indicator lamp 14←“off” Buffer empty indicator lamp 15←“on” Buffer full indicator lamp 16←“off” Remaining buffer/
Unsent data capacity display lamp 17 ← “100%” Block index display lamp 18 ← “All lights off” The above display status indicates to the user that neither transmission nor reception is currently being performed, and that the reception buffer Indicates that the is empty.

Next, the process advances to step 51-4 to initialize the control parameter table (FIG. 8). The parameters of the control parameter table set here and their setting values are as follows.

(1) Environment table (Figure 9) RBLOCKI←“1” 0CKI←“1” RBLOCKS 4-”O' TBLOCKS 4-”O” UMEM 4-“MEMMAX” RREM←“MEMMAX” 0CKSIZ 4-”O 'TSIZ 4-“0” TREM 4-’O” (2) Block registration table (Figure 11) BLOCKA
DH(1)←“MEMSTA”BLOCKADR(2)
~ [20] ← “0” BLOCKSIZ (1) ~ [20
]←″O″(3) Reception order table (Figure 12) RBLOCKSEQ C1) ~ [20]←″′0″(4
) Transmission order table (Figure 13) TBLOCKSEQ [1] to [20] ← “0” However, the value for 5TATH in the environment table has already been set in step 51-2, so the initial value setting is It is excluded from the target.

With this, the initialization operation in step S1 is completed.

FIG. 16 is a flowchart of operation control in the idle state in step S2 shown in FIG. 14. In the idle state, as shown in FIG. 16, it is first detected in step 52-1 whether or not the reception start/end button 6 has been pressed, and if it has been pressed, the process moves to step S3 and a reception operation is performed. . If not pressed, step 5
2-2, it is detected whether the transmission start/end button 8 has been pressed or the strain force Z is detected, and if the transmission start/end button 8 has been pressed, the process moves to step S4 and a transmission operation is performed. If it has not been pressed, the process moves to step 52-3, and it is detected whether or not the clear button 5 has been pressed. If it has been pressed, the process moves to S5 and a data block selection clear operation is performed. If the button has not been pressed, the process returns to step 52-1. That is, it waits until any one of the reception start/end button 6, transmission start/end button 7, or clear button 5 is pressed. However, if the reset button 4 is pressed, the interrupt sequence immediately moves to the initialization operation of step S1.

FIG. 17 shows an outline of the operation control in the reception operation step S3 shown in FIG. 14. In this reception operation step S3, as shown in FIG. 17, reception operation conditions are first determined in step 53-1.

FIG. 18 is a flowchart of the operation control in this receiving operation condition determination step 53-1. As can be seen from the detailed flow shown in FIG. 18, here the number of registered blocks and the remaining capacity of the reception buffer are determined. In step 53-1-1 of determining the number of registered blocks, the number of registered blocks RBLOCKS is less than the maximum number of registrations 20;
That is, it is determined that RBLOCKS<20, and further, in step 53-1-2 for determining the remaining capacity of the reception buffer, it is determined that the remaining reception buffer capacity is not O, that is, RREM>0. If both of these two conditions are satisfied, the control moves to step 53-2, and if either of these conditions is not satisfied, the receiving operation step S3 is ended.

Returning to FIG. 17, in step 83-2, the receiving lamp 13 is turned on to notify the user that the receiving operation has started, and the process proceeds to step 53-3.

Figure 19 shows the start byte reception step 5 shown in Figure 17.
3-3 is a flowchart of operation control.

In step 53-3, the first byte data of the data block of block index i is received. The byte data reception operation is as shown in Figure 19.
Assertion of CKNLG C (step 53-3-1)
→Negate BUSY C (step 53-3-2)
→-ACKNL, negate G C (step 53-
3-3) → Detection of assertion of -3 TROBE C (Step 53-3-5) → Assertion of BUSY C (Step 53-3-6) → Read byte data from DATAOC-DATA7C Step 53-3-7) This is done in this sequence. The byte data d read in step S-3-3-7 is stored in step 53-3-8.
At memory address B L OCK A D H
It is stored in the area within the reception buffer indicated by (i). Thereafter, in step 53-3-9, one is added to the data block size BLOCKSIZ[i). In the determination in step 53-3-10, if the byte data d stored in step 53-3-8 is the first byte data stored in the receive buffer,
That is, at the time of step 53-3-10, the value of the remaining receive buffer amount RRE M is the receive buffer size U M E
If it is equal to the value of M, which is the so-called "buffer empty state," then at least the buffer is no longer in the "buffer empty state" by storing the byte data d in step 53-3-8, so step 53-3-11 At this point, the buffer empty indicator lamp 15 is turned off. Step 53-3-12
Then, 1 is subtracted from the remaining reception buffer amount RREM.

In the following step 53-3-13, the remaining receive buffer amount RR
The ratio of the EM reception buffer to the size UMEM is displayed as a percentage on the remaining buffer/unsent data capacity display lamp 17. Here, the percentage is calculated using the following formula.

Finally, in step 53-3-14, the remaining receive buffer amount RR is
It is determined whether EM has become O, that is, a "buffer full state". If the buffer is full, proceed to step 53-4; otherwise, proceed to step 53.
The start byte reception at -3 is determined to be normal and the process moves to step 53-5. Also, in step 53-3-4, 3 TROBE C assertion detection step 53-3
If reception start/end button 6 is pressed before -5,
It is considered that the reception operation is stopped, and B is determined in step 53-3-15.
After asserting USY C, the process moves to step 53-6, where the lit receiving indicator lamp 13 is turned off, and the receiving operation step S3 ends.

Referring again to FIG. 17, in the start byte reception 53-3, after normal reception as described above, control is transferred to step 53-5, where the block index display lamp 18 corresponding to block index i is blinked. , informs the user that the data block with block index i is currently being received. Then step 53
-Move to 7.

FIG. 20 is a flowchart of operation control in the data block receiving step 53-7 shown in FIG. 17. In step 53-7, the data block with block index i is received. As shown in FIG. 20, the byte data reception operation is as follows: -ACKNLG C assertion (step S3-7-1) → BUSY C negation (step 53-7-2) → -ACKNLG C negation (step 53-7-2) 7-3) → -5 TROBE
C assertion detection (step 53-7-6) → BUS
Assertion of YC (step 537-7) → DATA
The sequence of reading byte data from OC-DATA7C is performed in steps 53-7-8). For the byte data d read in step S-3-7-8, it is determined in step 53-7-9 whether or not the code is "EOF" (=OBH) indicating the end of the data block. , "EOF", it is assumed that the reception of the data block with the block index i currently being received has been completed, and the process moves to step 53-8.

If it is not “EOF”, step 53-7-10
The byte data d read in step 53-7-8 is stored at the memory address BLOCK ADR.
(i)+BLOCKSIZ (i) is stored in the area in the reception buffer. Then, step 53-7-
11 the size of the data block BLOCKSI
1 is added to Z ('i), step 53-7-12
1 is subtracted from the remaining reception buffer amount RREM at .

In the following step 53-7-13, the remaining receive buffer amount RR
The ratio of the EM reception buffer to the size UMEM is displayed as a percentage on the remaining buffer/unsent data capacity display lamp 17. The formula for calculating the percentage is the same as in step 53-
It is the same as that used in 3-13. Finally step 5
At 3-7-14, it is determined whether the remaining reception buffer amount RREM is O, that is, the "buffer full state". If the buffer is full, the process moves to step 53-4; otherwise, the process returns to step 53-7-1 to receive the next byte of data. Also -3TRO
If the reception start/end button 6 is pressed in step 53-7-4 before BEC assertion detection step 33-7-6, it is assumed that the reception operation is stopped, and step 537-
After asserting BUSY C at step S3-
10 to erase the data block being received. Similarly, if the reception interruption button 7 is pressed in step 53-7-5, it is assumed that the reception operation is interrupted, and step 53
After asserting BUSY C at -7-16, the process moves to step S3-11.

If the block end code "EOF" is received in the data block receiving step 53-7, control moves to step 83-8, where the received data block is registered.

FIG. 21 is a flowchart of operation control at the received data block registration step 53-8 shown in FIG. 17. Here, as shown in FIG. 21, first step 53-
After adding 1 to the registered block number RBLOCKS in step 8-1, the block index i of the registered data block is stored in the reception order table in step 53-8-2. At that time, the reception order table RBLOCKSEQ [
The storage positions (1 to 20) in 1) to [20] are the registered block number RBLO that has been added in step 53-8-1.
CKS value, and the storage area is RBLOCKSEQ (
RBLOCKS). Further, block index i is a value stored in RBLOCKI.

In other words, the operation here is RBLOCKSEQ CRBLOCKS) 4-RBL
It can be expressed as OCKI. Then step 53-
At step 8-3, the block index display lamp 18 corresponding to the blinking block index i is turned on to notify the user that the data block with block index i has been registered, and then the process moves to step 53-9. do.

FIG. 22 is a flowchart of operation control in the next block index setting step 53-9 shown in FIG. 17.

In step 53-9, the block index RB given to the next data block received from the computer is
Configure LOCKI. As shown in FIG. 22, first, in step 53-9-1, the currently registered data
It is determined that the number of blocks RBLOCKS is less than the maximum number of registrations 20, and if the condition is not satisfied, step 53-
6, and the reception operation is immediately terminated. If the conditions are satisfied, the process proceeds to step 53-9-2, where "1" is substituted as the initial value of the candidate unused block index X. Thereafter, in step 53-9-3, it is determined whether the data block with block index X has already been registered or not.
KSIZ (x)] is O. O
In this case, the data block with block index
Set KA'DR(x).

The start address value set here is the start address BLOCKAD of the data block with block index i that was last received in step 53-7.
The sum of R[i] and its size BLOCKSIZ (i) is used. That is, BLOCKADRCx) ←BLOCKADR[i]+
BLOCKSIZ (i). This means that the next received data block is stored in the receive buffer following the last registered data block. After the start address setting step 53-9-5, the process proceeds to step 53-9-6, where X is finally stored in the block index RBLOCKI given to the next data block to be received. On the other hand, in the determination at step 53-9-3, BLOCKSI
Z [If xl is not O, the data block with block index X has already been registered, so proceed to step 53-9-4, add 1 to the candidate block index Step 53-9 again
-Repeat the judgment of 3. In this method, since it is known from the determination in step 53-9-1 that there is at least one block index that is not used, a block index X for an unregistered data block is always obtained. As described above, in step 53-9-6, the block index RBL of the data block newly received from the computer
Once OCKI is set, return to step 53-3 again.
Receives the first byte of a new data block.

If the reception start/end button 6 is pressed in the data block reception step 53-7, step S
Control passes to step 3-10, where the data block being received is forcibly erased.

FIG. 23 is a flowchart of operation control in the received data block erasing step S3-10 shown in FIG. 17. Here, first, in step 53-10-1, the size BLOCKSIZ [i) of the data block of the block index i that has been received in step S37 up to now is added to the remaining receive buffer amount RREM to obtain the value of the remaining receive buffer amount RREM. is returned to the state at the start of reception of the data block with block index i. Next, the remaining reception buffer amount RR restored in step 53-10-2
The ratio of the EM reception buffer to the size U M E M is displayed as a percentage on the remaining buffer/unsent data capacity display lamp 17 . The formula for calculating the percentage is the same as that used in step 53-3-13. Next, the remaining receive buffer amount RRE restored in step 53-10=3
It is determined whether the value of M is equal to the value of the receiving buffer size UMEM, which is the so-called "buffer empty state", and if the buffer is empty, the buffer empty indicator lamp 15 is turned on in step 53-10-4. and step 53
-10-5, the received data block erasure is completed by clearing the size BLOCKSIZ [:i] of the data block of block index i that has been received in step 53-7 to O, and step 53- At 10-6, the block index display lamp 18 corresponding to the blinking block index i is cleared, and the user is informed of the data of the block index i.
After indicating that the block has been erased, step 53-
The reception operation ends by proceeding to step 6.

If the reception interrupt button 7 is pressed in the data block reception step 53-7, the process proceeds to step S3-1.
Control is transferred to 1, where the receiving indicator lamp 13 is lit.
After blinking to inform the user that the reception operation is being interrupted, the process advances to step S3-12.

FIG. 24 is a flowchart of operation control in instruction waiting S3-12 shown in FIG. 17.

Step S3-12 is a state of waiting for an operation instruction when the reception operation is interrupted, and waits until one of the operation instruction buttons is pressed as shown in FIG. When reception interrupt button 7 is pressed (step 53-12-1)
, the control moves to step S3-13, and if the reception start/end button 6 is pressed (step 53-12-2)
Control moves to step S3-14 and clear button 5 is pressed.
If is pressed (step 53-12-3), control moves to step S3-16.

When the reception interruption button 7 is pressed while waiting for an operation instruction at the time of interruption in step S3-12, it is treated as restarting the reception operation (cancellation of interruption), and the process moves to step S3-13, where the reception indicator lamp 13 is blinking. After lighting up to inform the user that reception operation has resumed, step 53-
7 and continues receiving the data block of block index i again.

When the reception start/end button 6 is pressed while waiting for an operation instruction at the time of interruption in step S3-12, step S3
The control is transferred to -14, where the data received so far is
Register the block.

FIG. 25 is a flowchart of operation control in reception data block registration S3-14 shown in FIG. 17. The flow here is the received data block registration step 5.
3-8, 1 is added to the number of registered blocks RBLOCKS as shown in FIG. 25 (step 53-1).
4-1), reception order table (RBLOKSEQ [RB
LOCK]) to block index i (=RBL
OCKI), and (step 53-14-2), the block corresponding to the blinking block index i is stored.
After the index display lamp 18 is turned on (step 53-14-3), the process moves to step S3-15.

FIG. 26 is a flowchart of operation control in the next block index setting step S3-15 shown in FIG. 17.

In step S3-15, the block index R given to the next data block received from the computer is
Configure BLOCKI. The flow here is similar to that of the next block index setting step 53-9, and as shown in FIG. -15-1) If the conditions are not met, the process moves to step 53-6 and the reception operation is promptly ended. If the conditions are satisfied, "1" is assigned as the initial value of the candidate unused block index X (step 53-15-2), and it is determined whether the data block with block index X has already been registered. Step 53-15-3). If not registered, start address BLOCK in reception buffer.
Set ADH(x) (step 5315-5), store X in block index RBLOCKI (step 5315-5);
Step 53-15-6). On the other hand, if it is determined in step 53-15-3 that the block has been registered, 1 is added to the candidate block index X (step 53-15
-4), repeat the determination in step 53-15-3 again. Once the block index RBLOCKI of the data block newly received from the computer is set in this way, the process advances to step S3-17.

On the other hand, if the clear button 5 is pressed in the state of waiting for an operation instruction at the time of interruption in step S3-12 in FIG.
The control is transferred to -16, where the data received so far is
Performs forced erasure of blocks. FIG. 27 is a flowchart of operation control in received data block erasure S3-16 shown in FIG. 17.

The flow here is similar to that of the received data block erasing step S3-10, and as shown in FIG. In step 53-16-1), the remaining buffer/unsent data capacity display lamp 1 indicates the ratio of the restored remaining receive buffer amount RREM to the receive buffer size UMEM as a percentage.
Step 53-16-2), Step 53
-16-3, it is determined whether the buffer is empty, and if the buffer is empty, the buffer empty indicator lamp 15 is turned on in step 53-16-4. Then, the block index i received up to now in step 53-7
Clear the size of the data block to O (step 53-16-5), and set the blinking block index i to
After clearing the block index indicator lamp 18 corresponding to (step 53-166), step S3-
Proceed to step 17.

FIG. 28 shows the instruction waiting step S3-1 shown in FIG. 17.
7 is an operation control flowchart.

Step S3-17 is a state of waiting for an operation instruction after the receiving operation interruption process, and waits until one of the operation instruction buttons is pressed as shown in FIG. When the reception start/end button 6 is pressed (step 53-
17-1), the receiving operation is considered to be stopped, step 53-
The process moves to step 6 and the receiving operation ends. On the other hand, reception interrupt button 7
If is pressed (step 53-17-2), it is treated as restarting the reception operation, and the process moves to step S3-18, where the flashing reception indicator lamp 13 is turned on and the user is notified that the reception operation has resumed. After informing the
-3 and write the first byte of the new data block.
Receive data.

In FIG. 17, the start byte receiving step 53-3
Alternatively, if it is determined in the data block receiving step 53-7 that the buffer is full,
The control moves to step 53-4, where the lit receiving indicator lamp 13 is made to blink to inform the user that the receiving operation is being interrupted, and then the process proceeds to step S3-19.

FIG. 29 shows the flow of operation control in the buffer full state notification step S3-19 shown in FIG. 17.

In step S3-19, a buffer full state is notified. As shown in FIG. 29, first step 53-19-
In Step 1, the buffer full indicator lamp 16 is turned on to notify the user that the buffer is full, and in Step 53-19-2, the computer control signal line PE C is turned on.
By asserting the computer control signal line -ERRORC in step 53-19-3, the computer is informed that the printer buffer is in the "out of paper state". Then step S3-20
Move to.

FIG. 30 shows the instruction waiting step S3-2 shown in FIG. 17.
2 is a flowchart of operation control at 0.

Step S3-20 is a state of waiting for an operation instruction when the buffer is full, and waits until one of the operation instruction buttons is pressed as shown in FIG. 30. When the reception start/end button 6 is pressed (step 53-2O
-1), the control moves to step S3-21, and the clear
When button 5 is pressed (step 53-2O-2)
, control moves to step S3-23.

When the reception start/end button 6 is pressed while waiting for an operation instruction when the buffer is full in step S3-20, control moves to step S3-21, where the data that was being received until the buffer is full is... Register the block.

FIG. 31 is a flowchart of operation control in the received data block registration step S3-21 shown in FIG. 17.

The flow here is similar to that of the received data block registration step 53-8, and as shown in FIG. 31, 1 is added to the registered block number RBLOCKS (step 53
-2l-1), receiving table (RBLOCKSEQ
l:RBLOcKs)) with block index i
(=RBLOCKI) is stored in step 53-2l-.
2) After lighting up the block index display lamp 18 corresponding to the blinking block index i (
Step 53-2l-3), the process moves to step S3-22.

FIG. 32 is a flowchart of operation control in the next block index setting step S3-22 shown in FIG. 17.

In step S3-22, the block index R given to the next data block received from the computer is
Configure BLOCKI. The flow here is similar to that of the next block index setting step 53-9, and as shown in FIG. -22-1) If the conditions are not met, the process moves to step 53-6 and the reception operation is promptly terminated.

If the conditions are satisfied, "1" is assigned as the initial value of the candidate unused plot index X (step 53-22-2), and the data block with the block index X is already registered. Step 53-22-3) to determine whether or not the block has been registered. If it has not been registered, set the start address BLOCKADRCX) in the receive buffer (Step 53-225), and store X in the block index RBLOCKI (Step 53). -22
-6). On the other hand, if the determination at step 53-22-3 indicates that the block has been registered, 1 is added to the candidate block index X (step 53-22-4), and the determination at step 53-22-3 is repeated again. . Once the block index RBLOCKI of the data block newly received from the computer is set in this way, the process moves to step 53-6, and the receiving operation is immediately ended.

When the clear button 5 is pressed while waiting for an operation instruction when the buffer is full in step S3-21, control moves to step S3-23, where notification of the buffer full state is stopped.

FIG. 33 is a flowchart of the operation control in step S3-23 of stopping notification of buffer full state shown in FIG. 17.

As shown in FIG. 33, first, in step 53-23-1, the computer control signal line -ERRORC is connected to the
By negating the computer control line PEC in step 3-23-2, the computer is informed of the printer.
After informing the user that the buffer has avoided the "out of paper state" and further turning off the lit buffer full indicator lamp 16 in step 53-23-3, the user is informed that the buffer is no longer in the full state. In order to forcibly erase the data blocks that have been received until the buffer becomes full, the received data block erase step S3-
Move to 16.

The above is the flow of the receiving operation step S3.

FIG. 34 schematically shows the operation control in the transmission operation S4 shown in FIG. 14. Transmission operation step S4
First, in step 54-1, transmission operating conditions are determined.

FIG. 35 is a flowchart of operation control in the transmission operation condition determination step 54-1 shown in FIG. 34.

As can be seen from FIG. 35, the number of registered blocks and the printer port control signal line 5LCTP are determined here. Step 54-1 of determining the number of registered blocks
In -1, it is determined whether the number of registered blocks RBLOCKS exceeds O, that is, RBLOCKS>0, and then in the determination step S4- of 5LCTP P.
In step 1-2, it is determined that 5LCTP is in the negated state, that is, 5LCTP is "Low". If both of these two conditions are satisfied, the control moves to step 54-2, and if either is not satisfied, The transmission operation step S4 is completed.

In step 54-2, preparations for a transmission operation are made.

FIG. 36 shows the transmission operation preparation step 5 shown in FIG. 34.
4-2 shows the flow of operation control in step 4-2. As can be seen from FIG. 36, first step 54-2-
Step 1 turns off the remaining buffer/unsent data capacity display lamp 17, and step 54-2-2 flashes the transmitting display lamp 14 to notify the user that the transmission operation has started. Next, in step 54-2-3, the total number of transmission data blocks TBLOCKS is cleared to 0, and in step 54-2-
4 is the printer port control signal line - 3LCTIN
The value of 5LIN stored in step 51-2 is outputted to P, and the value of AFDXT stored in step 5L-2 is outputted to the printer port control signal line -AUTOFEEDXTP in step 54-2-5.

That is, steps 54-2-3 to 4-2-5 TBLOCKS 4-O -8LCTIN P 4-5LIN -AUTOFEEDXT P, AFDXT are performed.

Then, in step 54-2-6, the printer control signal line -INIT P is asserted, and in step 54-2-7
By negating -INIT P at
Sends a pulse signal to initialize the printer connected to the printer port.

Next, the control moves to step 54-3 and enters a transmission block selection input waiting state.

FIG. 37 is a flowchart of operation control at the transmission block selection input waiting step 54-3 shown in FIG. 34.

That is, step 54-3 of waiting for transmission block selection input.
Now, as shown in FIG. 37, the process waits until one of the operation instruction buttons is pressed.

When the transmission start/end button 8 is pressed (step 5)
4-3-1), the end of the transmission operation and the control proceed to step S4-16, and the transmission operation ends.

Also, if clear button 5 is pressed (step 54)
-3-2), the control moves to step 4-4 and the transmission order table is erased. Also, if any of the 20 block index buttons 10 is pressed (
Step 54-3-3), control moves to step 54-5, and a transmission selection block is determined. (For convenience, the block index corresponding to the block index button 10 pressed in step 54-3-3 is assumed to be X.) Also, when the all block button 11 is pressed (
Step 54-3-4) Control proceeds to step 54-6, where all received blocks are registered. If the interrupt button 9 is pressed (step 54-3-5), control proceeds to step 54-7, where the transmission order table is determined.

When the clear button 5 is pressed in the transmission block selection input waiting step 54-3, control proceeds to step 54.
-4, the transmission order table TBLOCKSEQ [
i) Erasure of (i=1. 2. . . , 20) is performed.

FIG. 38 is a flowchart of operation control in the transmission order table erasing step 54-4 shown in FIG. 34.

As can be seen from FIG. 38, from step 54-4-1 to step 54-4-4, TBLOCKSEQ (t)←O(i=1.2...
20), the transmission order table is cleared to 0. After this, control returns again to step 54-3.

When the block index button 10 is pressed in the transmission block selection input waiting state step 84-3, control moves to step 34-5, where the block index X selected for transmission is determined.

FIG. 39 shows the flow of operation control in the transmission selection block determination step 54-5 shown in FIG. 34.

As can be seen from Figure 39, the judgment conditions are
The data block referenced by index X must be registered for reception. That is, the size of the data block BLOCKSIZ (xl is 1 (byte) or more) BLOCKSIZ (x)>O (step 54-5-
1) and that the data block referenced by block index X has not been registered for transmission, that is, the transmission order table TBLOCKSEQ (il (i=1.2.
...20) The data block index X is not registered in TBLOCKSEQ (i) ≠x (i=
1.2. ..., 20) (Steps 54-5-2 to 54
-5-5).

If either condition is not satisfied, control returns to step 54-3 again to wait for a transmission block selection input.

On the other hand, if both of these conditions are met, control moves to step 54-6, and block index X is registered in the transmission order table.

FIG. 40 shows the flow of operation control in the transmission selection block registration step 54-6 shown in FIG. 34.

In step 54-6, the block index X selected for transmission is registered in the transmission order table. Fourth
As can be seen from Figure 0, here, in order to know the block index X selected for transmission, it is first set as the initial value of the transmission order i in step 54-6-1 in order to know which block index X was selected after the transmission operation. Assign “1”. Next, in step 54-6-2, the i-th area TBL of the transmission order table is
Determine whether the content of OCKSEQ [i) is “0”. If it is “O”, block index
-6-4, and if it is not "O", "1" is added to the transmission order i in step 54-6-3 to search the transmission order table one after another, and then again in step 54-6-2. Repeat the judgment. In the transmission order i search method from step 54-6-1 to step 54-6-4, the number of block indexes registered in the transmission order buffer is 19 or less as determined in step 54-5. Therefore, there is always an i such that TBLOCKSEQ[:1)=0.

In step 54-6-4, the block selected for transmission is
Register index X in the i-th area of the transmission order table. That is, execute TBLOCKSEQ C1)=x. Control then moves to step 54-6-5, where the block index display lamp 18 corresponding to the block index X selected for transmission is flashed, indicating to the user that the data block with block index X has been selected for transmission. Let me know. After this, the control returns to step 54-3 again and enters a transmission selection input waiting state.

When the all block selection button 11 is pressed in the transmission block selection input waiting state step 54-3, control shifts to $4-7, and all block indexes registered for reception are registered in the transmission order table.

FIG. 41 is a flowchart of operation control in the all block registration step 54-7 shown in FIG. 34.

As can be seen from FIG. 41, here, by copying the contents of the reception order table to the transmission order table, block indexes that have been registered for reception are registered in the transmission order table according to the order in which they were received. The block index display lamps corresponding to all the data blocks currently registered for reception are flashed to inform the user that all the data blocks currently registered for reception are currently selected for transmission. That is, in step 54-7-1, a convenient counter "i" representing the order is set.
” is assigned “1” as an initial value, and the following step 54-
7-2, the i-th area RBLOC3E of the reception order table
Read out the contents of Q (i) and write it as X for convenience. In other words, the block index corresponding to the data block of reception order i is X.

In step 54-7-3, the step 54-7-2
It is determined that the block index X read out is not O. If not O, step 54-7-4
and moves to the i-th area RBLOCK of the reception order table.
Copy the contents of SEQ [i) to the i-th area TBLOCKSEQ (i) of the transmission order table.

Then, the process proceeds to step 54-7-5, where the block index display lamp 18 corresponding to the lit block index After adding "1" to the order i, the control is returned to step 54-7-2. On the other hand, if the determination in step 54-7-3 is O, it means that the valid data in the reception order table has ended, so the operation in step 54-7 is ended and the control returns to step 54-3. Then, the device enters the state of waiting for transmission block selection input.

When the interrupt button 9 is pressed in the transmission block selection input waiting state step 54-3, control proceeds to step 54.
-8, and the transmission order table is determined. The determination is made in the first area TBLOCKSEQ of the transmission order table (
1] is determined to be O or not. In other words, if TBLOCKSEQ (1, 1≠0) is satisfied, at least one block index is registered in the transmission order table, so the control moves to step 54-9 to perform a transmission operation. , if the above conditions are not met, there is currently no block index registered in the transmission order table, so the control returns to step 54-3.
It returns to the state of waiting for transmission block selection input.

FIG. 42 shows the transmission operation start step 5 shown in FIG. 34.
4-9 is a flowchart of operation control.

In step 54-9, a transmit operation is initiated. As can be seen from FIG. 42, in step S4-91 the block/index display lamp 18 is completely extinguished, and in step 54-9-2, the total number of transmission data/block sizes TS is
Clear IZ with O, then step 54-9-3
Now, a convenient counter "i" representing the transmission order is set and "1" is assigned as an initial value, and then step 54-9-4
The i-th area TBLOCKSEQ of the transmission order table is
Read the contents of (i) and set it as X for convenience. In other words, the block corresponding to the data block with transmission order i
The index will be X. Next, in step 54-9-5, it is determined that the block index X read in step 54-9-4 is not O. If it is not 0, the control moves to step 54-9-6 and the block index display lamp 18 corresponding to the block index X is turned on. And then step 54-9-
7, the data block size of block index X is added to the total number of transmit data block sizes TSIZ.
KSIZ Cx] and set again, step 54-
After adding 1 to the transmission order i to select the next data block in the transmission order at step 9-8, step 54-9-4 is performed again.
Return control to.

On the other hand, if the determination at step 54-9-5 is O,
Since this means the end of valid data in the transmission order table, the control moves to step 54-9-9.

Block index display lamps 18 corresponding to all data blocks currently registered for transmission in this way
is turned on to inform the user of the indexes of all data blocks selected for transmission, and the total number of sizes of data blocks currently registered for transmission is set in TSIZ. Next, in step 54-9-9,
Untransmitted byte data amount TR of set TSIZ contents
Copy to EM.

This is because not even one byte of data has been sent to the printer yet, so TSIZ=TREM.

Next, in step 54-9-10, the transmission data block
The data block index to be transmitted first is set in index TBLOCK I. In other words, the contents of the data block index TBLOCKSEQ (1) that was selected for transmission first are stored as TBLOC.
Set to KI. Next, in step S54-9-11, the currently blinking transmitting indicator lamp 14 is turned on, and the control proceeds to step S4-10.

FIG. 43 is a flowchart of operation control in the data block transmission step S4-10 shown in FIG. 34.

In step S4-10, the block index TB
LOCK I data block is transmitted. Fourth
As you can see from Figure 3, Pico first performs step 54.
-10-1 = total number of transmit data blocks TBLOCKS
Add 1 to . Next, in step 54-10-2, the block index indicator lamp 18 corresponding to the block index position OCK I is blinked to inform the user that the data block with the block index TBLOCK I is currently being transmitted, and the next Step 54-
Number of transmitted bytes T of the data block being transmitted in 10-3
Clear BLOCKSIZ with O. If the transmission start/end button 8 is pressed here (step 54-1
O-4), the transmission operation is considered to be stopped, and control proceeds to step S.
The process moves to 4-17 and the transmission operation is stopped. Further, when the interrupt button 9 is pressed (step 54-1O-5), control moves to step S4-15, and a transmission interrupt input waiting state is entered. If neither button is pressed, control moves to step 54-10-6 and checks the state of the printer control signal line to determine whether the printer connected to the printer boat is in an error state. Determine by. Judgment conditions are PE P or negated state,
That is, PE P= “Low (Step 54-1O-6) SELECT P is in the asserted state, that is, 5ELECT P= “High” (Step 5
4-1O-7) and -ERRORP are in the asserted state, that is, -ERRORp=“Low (Step S4-
10-8). If all the above conditions are met,
Control passes to step 54-10-9. On the other hand, if any of the conditions is not satisfied, the control proceeds to step S4-1.
The process moves to step 5 and enters a state of waiting for a transmission interruption input. Step 5
In step 4-10-9, it is determined whether the printer connected to the printer port is in a receiving state by checking the BUSY P of the printer port control signal line. If BUSY P is asserted here,
This means that the printer is not able to receive data.
Control moves to step 54-1O-10, and a wait state is entered for a unit time. After this, the control returns to step 54-10-9 and repeats the determination. In this way, the printer waits until the printer becomes ready to receive data. On the other hand, BUSY
If P is in the negated state, it means that the printer is ready to receive data, so the control goes to step 54-1O-
The process moves to step 11, and data transmission is performed.

54-1O-11 transfers the byte data stored in the receive buffer to the printer/port control signal line DAT.
Send to AOP NDATA7 P. The address of the byte data to be transmitted here is the start address of the data block of block index TBLOCK I currently being transmitted BLOCKADR[TBLOCK
I] and the number of transmitted bytes TBL of the data block being transmitted
It is obtained by the sum of OCKSIZ. In other words, the address where the byte data to be sent is stored is BLOCKADR(TBLOCK I) + 0C
The byte data represented by KSIZ and stored at this address is sent to the printer port control signal line.

Then, immediately after this, the printer control signal line -8TRO
BE P(7)7Sert (Step 54-1O-12
), -8 TROBE P negate (step 5
4-1O-13) is performed and a Low pulse signal is transmitted to the printer. Since the transmission of 1 byte of data is completed here, in step 54-1O-14, the number of transmitted bytes TBLOCKS of the data block currently being transmitted is
One is added to IZ, and one is subtracted from the untransmitted byte data amount TREM in step 54-1O-15.

In the subsequent step 54-1O-16, the ratio of the amount of untransmitted byte data to the total number TSIZ of the TREM transmission data block size is displayed as a percentage on the remaining buffer/untransmitted data capacity display lamp 17. Here, the percentage is calculated using the following formula.

When TREM=0, unsent data ratio=O When TREM≠0, control then moves to step 54-1O-17, and determines whether there is still unsent data in the data block currently being transmitted. do. The determination is based on the size of the data block currently being transmitted BLOCKSIZ(TBLOCK
This is done by comparing the contents of I) with the contents of the data block being transmitted/transmitted byte count TBLOCKSIZ. That is, BLOCKSIZ [TBLOCK I) ≠TBL
If OCKSIZ, it means that there is still unsent data, so control returns to step 54-10-4 and starts transmitting the next byte of data. On the other hand, B.L.O.
CKSIZ (TBLOCK I) = TBLOC
In the case of KSIZ, it means that all the data in the data block being transmitted has been transmitted, so control ends the transmission of the data block and moves to step S4-11.

In step S4-11, data block transmission termination processing is performed. That is, the block index display lamp 18 corresponding to the blinking block index TBLOCK I is extinguished to notify the user that the transmission of the data block of the block index TBLOCK I has been completed.

The process then moves to S4-12, where the next transmission data block is selected.

Figure 44 shows the next block selection S4-12 shown in Figure 34.
2 is a flowchart of operation control in FIG.

As can be seen from FIG. 44, first step 54-12-1 TE transmission order table (7) TBLOCKS
+1st area TBLOCKSEQ [TBLOCKS
+1] and set it as X for convenience. Next, in step 54-12-2, it is determined whether the read block index X is O or not. If not O, then X is the index of the data block to be transmitted next, control is transferred to step S4-12-3, and T representing the index of the data block to be transmitted is
Store block index X in BLOCK I. Thereafter, control is returned to step S4-10 to begin transmitting the next data block. Meanwhile step 5
If X is 0 in the judgment in 4-12-2, this means that all data blocks registered in the transmission order table have been transmitted and there is no next transmission data block, so the control is skipped. The process moves to S4-13 and enters a state of waiting for an input to interrupt the transmission operation.

FIG. 45 shows the transmission operation interruption input S shown in FIG. 34.
4-13 is a flowchart of operation control.

In step S4-13, as can be seen from FIG. 45, first, in step 54-13-1, the transmitting display lamp 14, which is currently lit, is blinked to inform the user that the transmitting operation is interrupted. After this, it waits until any of the operation buttons is pressed. If the transmission start/end button 8 is pressed here (step 54-1
3-2) It is assumed that the transmission operation has been canceled and the control moves to step S4-17. Further, when the interrupt button 9 is pressed (step 54-13-3), the control is performed in step S4.
-14, and preparations for retransmission are made.

FIG. 46 shows the retransmission preparation step S4 shown in FIG.
-14 shows the flow of operation control.

As can be seen from FIG. 46, first, in steps 54-14-1 to 54-14-4, TBLOCKSEQ (i) IO (i=1.2.
..., 20) to clear the transmission order table to O. Next, in step 54-14-5, the total number of transmission data blocks TBLOCKS is cleared to O, and in step 54-14-6, the remaining buffer/untransmitted data capacity display lamp 17 is extinguished. Then step 541
From step 4-7 to step 54-14-IO, the block index display lamps corresponding to all the data blocks currently registered for reception are turned on to inform the user of the indexes of all the registered data blocks. That is, in step 54-14-7, a convenient counter "j" representing the reception order is set to "l" as an initial value.
”, and in the following step 54-14-8, the contents of the j-th area RBLOCKSEQ (il) of the reception order table are read out and set as X for convenience. In other words, the reception order j
The block index corresponding to the data block is X. Next, in step 54-14-9, it is determined whether the block index read in step 54-14-8 is O. If it is not O, the control is transferred to step 54-14-10, and the block index display lamp 18 corresponding to the block index X is lit. and then step 54-14
-11, 1 is added to the reception order j to select the next data block in the reception order, and then step 54-14-
Return control to 8. On the other hand, if X is O in the determination at step 54-14-9, it means the end of valid data in the reception order table, so the control at step S4-14 is ended and the control is returned to step 54-3. The system enters the transmission selection input waiting state again.

If the interrupt button 9 is pressed in the data block transmission step S4-10, or if an error state of the printer connected to the printer boat is detected in step S4-10, the control proceeds to step S4-10. The process moves to step 15 and enters a transmission interruption input waiting state.

Figure 47 shows S4-, which has the transmission interrupt input shown in Figure 34.
15 shows the flow of operation control in step 15.

As can be seen from FIG. 47, first, in step 54-15-1, the transmitting display lamp 14, which is currently lit, is blinked to notify the user that the transmission is being interrupted. After this, it waits until any of the operation buttons is pressed. If the transmission start/end button 8 is pressed here (step 54-15-2), it is assumed that the transmission operation has been canceled and the control proceeds to step S4-17. Also, if clear button 5 is pressed (step 54-
15-3) Control moves to step S4-16 to skip data block transmission during transmission suspension. Also, if the interrupt button 9 is pressed (step 54-15-4)
, the control moves to step 54-15-5, turns on the blinking transmitting indicator lamp 14, and returns the control to step S to restart the transmission of the data block whose transmission was interrupted.
Return to 4-10.

When the clear button 5 is pressed in step S4-15 in the transmission interrupt input waiting state, control proceeds to step S4-15.
16, data block transmission is skipped during transmission suspension. This processing is performed by calculating how many bytes of data have not been transmitted in the data block whose transmission has been interrupted, and subtracting that value from the amount of untransmitted data bytes TREM.

To determine the amount of untransmitted data in a transmission interrupted data block, use the size B of the transmission interrupted data block.
LOCKSIZ l"TBLOCK Subtract the number of transmitted bytes TBLOCKSIZ of the data block being transmitted from the IE. That is, BLOCKSIZ (TBLOCK I) - TBL
All you have to do is calculate OCKSIZ.

Therefore, here, TREM+TREM-(BLOCKSIZ CTBLO
CK I )-TBLOCKSIZ). Thereafter, control is transferred to 34-10, and transmission of the transmission interrupted data block is resumed.

If the transmission start/end button 8 is pressed in the data 1 block transmission step S4-10, if the transmission start/end button 8 is pressed in the transmission operation interruption input waiting state 34-13, or if the transmission interruption If the transmission start/end button 8 is pressed in the input waiting state S4-15, control moves to step S4-17 and transmission is stopped.

FIG. 48 shows the transmission stop step S4- shown in FIG. 34.
17 is a flowchart of operation control in step 17.

As you can see from Figure 48, here we will start with 54-1.
TBLOCKSEQ from 7-1 to 34-17-4
By executing (i]=O (i=1.2...,20), the transmission order table is cleared to O.Next, in step 54-17-5, the remaining reception buffer amount RREM
The ratio of the receive buffer to the size UMEM is displayed as a percentage on the remaining buffer/unsent data capacity display lamp 17. The formula for calculating the percentage is the above-mentioned reception operation step 5.
It is the same as that used in 3-3-13. Next, in steps 54-17-6 to 54-17-10, the block index display lamps corresponding to all the data blocks currently registered for reception are lit, and the user is asked to check all the registered data blocks. Inform the index of. The method of this processing is exactly the same as the processing from step S4-14-7 to step 54-14-11 of the retransmission preparation step S4-14. This post-processing moves to step S4-18. In step S4-18, the transmitting indicator lamp 14 is extinguished and all transmitting operations are completed.

FIG. 49 schematically shows the operation control in the data block selective clear operation step S5 shown in FIG. 14. The selective clearing operation step S5 is the 49th
The process is carried out according to the flow shown in the figure. That is, first, in step 55-1, the number of registered blocks is determined. Since the data block selective clear operation step S5 described below targets data blocks currently registered for reception from the computer, it is necessary that the number of registered blocks is at least 1 or more. .

That is, in this registered block number determination step 55-1, RBLOCKS is determined for the registered block number RBLOCKS.
Determine whether KS>0 is satisfied, and if so, proceed to step 5.
5-2, and if the conditions are not met, the data
The block selective clearing operation step S5 is completed.

FIG. 50 is a flowchart of operation control at block index input waiting step 55-2 shown in FIG. 49.

Step 55-2 is a state of waiting for input of a block index to be erased, and waits until one of the operation instruction buttons is pressed as shown in FIG. If clear button 5 is pressed (step 55-2-
1) This is regarded as an instruction to end the selective clearing operation of the data block, and the operation step S5 is immediately terminated. In addition, there are 20 block index buttons 1
0 is pressed (step 55-2-2
), the control moves to step 55-3, and for convenience, the block index pressed in step 55-2-2 is
(Let the block index corresponding to button 10 be X), if the all block selection button 11 is pressed (step 55-2-3), control moves to step 55-4.

In step 55-3, it is determined whether the data block referred to by the block index X input using the block index button 10 in the block index input waiting step 55-2 is registered. Determination is based on the size of the data block BLOC
This is done depending on whether KSIZ [x) is 1 (byte) or more. That is, if BLOCKSIZ (x)>0 is satisfied, the data block with block index X is currently registered, and the process advances to step 55-5 to perform an erase operation.

On the other hand, if the condition is not met, the data block with block index
Control is returned to 5-2.

In step 55-5, the block index display lamp 18 corresponding to the lit block index X is blinked to inform the user that the data block with block index X is currently selected for erasure. After that, the process advances to step 55-6.

FIG. 51 is a flowchart of the operation control at the erase operation confirmation waiting step 55-6 shown in FIG. 49.

Step 55-6 is a state of waiting for confirmation of the erase operation, and the fifth
As shown in FIG. 1, the process waits until either the block index button 10 or the clear button 5 corresponding to block index X is pressed. If block index button 10 of block index X is pressed (step 55-6-1),
This is regarded as an instruction to cancel the erase operation for the data block with block index This is regarded as an instruction to execute an erase operation on the block, and the process moves to step 55-8.

In step 55-7, the block index display lamp 18 corresponding to the flashing block index X is turned on to inform the user that the data block of block index X is not targeted for erasure. Waiting for block index input again Step 5
Control is returned to 5-2.

If the clear button 5 is pressed in the erase operation confirmation waiting state step 55-6, control moves to step 55-8, where the data block of block index X is erased.

FIG. 52 is a flowchart of operation control in the data block erase step 55-8 shown in FIG. 49.

Here, as shown in FIG. 52, first, the data block with the block index
In order to know whether it is a block, step 55-8-
1'' is substituted as the initial value of the reception order m determined by 1.

Next, in step 55-8-2, it is determined whether the contents of the m-th area RBLOCKSEQ [m] of the reception order table match the block index X selected for erasure, and if they match, The process proceeds to step 55-8-4 assuming that m is the reception order of the data block with the block index After adding 1 to , the determination in step S5-82 is repeated again. This step 55-8-1 to step 5
The data block with the block index
Since it is known that the data block is currently registered by 5-3, the reception order m for the data block of block index X can be obtained without fail. Subsequent step 55-8
-4, for some data blocks received later in reception order than the data block with block index In preparation for the operation to shift the storage position in the receive buffer and fill the area where the data block with block index A convenient counter "n" representing the reception order for the data block is provided, and its initial value is m +
Substitute 1. Here, the maximum value that reception order n can take is the total number of data blocks RB currently registered in the reception buffer.
LOCKS, the range of possible values for this reception order n is considered to be m + l≦n≦RBLOCKS, but the block index to be erased
If the data block of is the last data block in the reception order, that is, m = RBLOcKs, then there is no data block that was received after the data block of block index X in the reception order. Therefore, the operation for correcting the storage position described below is not necessary. In step 55-8-5, it is determined whether the storage position of the data block needs to be corrected or not based on whether the reception order n is less than or equal to the number of registered blocks RELOCKS. If the conditions are met, the process proceeds to step 55-8-6; if not, the process proceeds to step 55-8-14. The data of block index X to be erased mentioned above.
If the block is the last data block in the receiving order, the judgment condition of step 55-8-5 is not satisfied, and the process immediately moves to step 55-8-14.

In step 55-8-6, in order to obtain the block index y'' given to the data block of reception order n, the n-th area RBLOCKSEQ of the reception order table is
Read the contents of (n). Subsequent step 55-8-7
Now, a convenient counter "i" is provided to count the byte data stored in each data block of block index y in reception order n, and O is substituted as its initial value. Thus, in step 55-8-8, each byte of data constituting the data block with block index y is divided into BLOCK, which is the size of the data block with block index X to be erased.
Perform an operation to transfer SIZ (x) (bytes) forward (in the lower address direction) within the receive buffer.

The address of the area where the byte data to be transferred is stored is obtained by the sum of the start address BLOCKADH [y] of the data block with block index y and the counter i, and the new storage area (transfer destination) address is the above-mentioned address. Size of data block with block index X to be erased from transfer source address BLOCKS
It is IZ minus [X]. In other words, the transfer source address is expressed as BLOCKADR(y)+i, and the transfer destination address is expressed as BLOCKADR(y)-BLOCKSIZ(x)
It is represented by +i. In step 55-8-9, 1 is added to counter i to point to the next byte data, and in step 55-8-10, it is determined whether all byte data constituting the data block of block index y has been transferred. In order to determine whether the counter i is the size of the data block with block index y BLOCKS
It is determined whether it is less than IZ [y). If the condition is met, there is still byte data to be transferred, so the process returns to step 55-8-8 to transfer the byte data; if the condition is not met, all byte data is transferred. Since the transfer has ended, the process advances to step 55-8-11. In step 55-8-11, the size of the data block of the block index X to be erased is subtracted from the start address BLOCKADHOr) of the data block of the block index y whose transfer has been completed, and is reset. In the following step 55-8-12, the reception order of the transferred data block with block index y is shifted forward by one in the reception order table. That is, RBLOCKSEQ (n-1) ←RBLOCKSE
Perform Q (n). Step 55-8 described above
-6 to step 55-8-12, one piece of data received later in reception order than the data block with index
This means that the storage position of the data block with reception order n, which is a block, has been corrected, but in step 55
-8-13, 1 is added to the reception order n in order to correct the storage position of the next data block in the reception order, and then the process returns to step 55-8-5. When the storage positions have been corrected for all data blocks up to the last data block in the receiving order, step 55-8
Since the determination condition at -5 is no longer satisfied, the process moves to step 55-8-14. If the data block with block index X to be erased is the last data block in reception order, or all data blocks received after the data block with block index After the storage position of the block has been corrected as described above, the control moves to step 55-8-14, where the last received in the reception order that has lost its meaning (has become an empty area) Area RBLOCKSEQ of the reception order table where the block index for the data block
Clear (RBLOCKS) with O.

Next, in order to determine whether the buffer full state can be avoided by erasing the data block with block index Determine whether or not. If the condition is met, block index X
Since the buffer is not full even before erasing the data block, the process advances to step 55-8-19. If the condition is not met, the buffer full state is avoided by erasing the data block with block index 55-8-17, computer control signal line P
Informing the computer that the printer buffer has avoided the "out of paper" condition by negating each of E.C., and clearing the lit buffer full indicator lamp 16 in step 55-8-18 After notifying the user that the buffer is full, the process proceeds to step 55-8-19. Step 5S-8-
19, the block to be erased to the remaining receive buffer amount RREM ◆Size of data block of index X BLO
Add CKSIZ (x) and reset. In the following step 55-8-20, the receive buffer size U of the remaining receive buffer amount RREM corrected in step 55-8-19 is determined.
The ratio to MEM is displayed as a percentage on the remaining buffer/unsent data capacity display lamp 17. Step 55-8-
In step 21, it is determined whether or not the buffer becomes empty due to the modification of the remaining receiving buffer amount RREM in step 55-8-19, based on whether the value of the remaining receiving buffer lRREM is equal to the value of the receiving buffer size UMEM; If the conditions are satisfied, that is, if the buffer becomes empty, the buffer empty indicator lamp 15 is turned on in step 55-8-22, and the process proceeds to step S5-8-23. On the other hand, if the conditions are not satisfied, the process immediately moves to step 55-8-23. In step 55-8-23, the size BLOCKSIZ (x
) to O. In the following step 55-8-24, 1 is subtracted from the registered block number RBLOCKS, thereby completing the data block erasing step 55-8 and proceeding to step 55-9.

When the erasure for the data block of block index X in step 55-8 is completed, step 5
Control is transferred to 5-9, where the block index display lamp 18 corresponding to the blinking block index
After informing that the data block has been erased, the process advances to step S5-10.

FIG. 53 is a flow chart of operation control in the next block index setting step S5-10 shown in FIG. 49.

In step S5-10, the receiving operation will be performed again in step S3.
The block index RBLOCKI to be given to the next data block received from the computer is set in preparation for the case where the next data block is received from the computer.

As shown in FIG. 53, first in step 55-10-1, the number of blocks RBLOCKS currently registered is O.
If the condition is satisfied, step 5
The process moves to step 5-1o-2, and if the condition is not satisfied, the process moves to step 55-10-4. Currently registered data/
If there is no block, step 55-- to give "1" as a default value to the block index given to the data block to be registered for reception first, as set in the initialization operation step SL.
1o-2 is the start address of the data block with block index "l" BLOCKADH [13 is the start address of the receive buffer MEMST
A and set the block index R to be given to the next received data block in step 55-10-3.
Store 1 in BLOCKI. Meanwhile step 55-10
If it is determined as -1 that there are several currently registered data blocks, control proceeds according to the flow of the next block index setting step 53-9 in the receiving operation step S3. First step 55-10-
In step 4, "l" is assigned as the initial value of the candidate unused block index X. Then step 55-1
0-5, it is determined whether the data block with block index X is currently registered or not based on whether its size (BLOCKSIZCX) is 0. If O, the data block with block index X is considered unregistered, step 55-10-7.
Proceed to.

On the other hand, if it is not 0, the data block with the block index -10-5
Repeat the judgment. In this method, since at least one unused block index exists due to the data block erasing step 55-8, a block index X for an unregistered data block is always obtained. If an unused block index X is found in this way, step 55-10
-7, in order to obtain the block index y corresponding to the last data block in the reception order among the several data blocks currently registered in the reception buffer, the RBLOCKSth area RBL of the reception order table is
Read the contents of OCKSEQ (RBLOCKS).

In the following step 55-10-8, the start address B of the data block with the unregistered block index
Start address BLOCKADH[y] and its size BLOCK of the data block with block index y that was last registered for reception in LOCKADR[:x)
SIZ Set the sum of [Y]. That is, BLOCKADR(x) ←BLOCKADR[:y:
Perform the operation l +BLOCKSIZ Cyl. After this, in step 55-10-9, the block index RBLOCKI given to the next received data block.
Store X in .

Step 55-10-3 or Step 55-10-
Block index RBLOC of a data block newly received from the computer in any of 9.
Once the KI is set, the process returns to step 55-1, and unless the total number of registered data blocks is O, the data block is
Repeat block erase operation.

Waiting for block index input step 55-2
If the all block selection button 11 is pressed in step 35-4, the control moves to step 35-4, where the blocks corresponding to all currently registered data blocks that are lit are selected.
The index display lamp 18 is flashed to inform the user that all registered data blocks are currently selected for deletion.

FIG. 54 is a flowchart of operation control in step 55-4 of all registered block index display 18 blinking shown in FIG. 49.

As shown in FIG. 54, the flow is such that a convenient counter "m" representing the reception order is set, "1" is assigned as an initial value at step 55-4-1, and the reception order is set at step 85-4-2. m-th area of the daple RBLOCKSEQ [m]
Read the contents of and set it as X for convenience.

In other words, the block index corresponding to the data block of reception order m is X. In step 55-4-3, the block read out in step 55-4-2 is
It is determined that index X is not O. If it is not O, the process moves to step 55-4-4, the block index display lamp 18 corresponding to the lit block index After adding 1 to the reception order m to select , the control returns to step 55-4-2.

On the other hand, if the determination in step 55-4-3 is O, it means that the valid data in the reception order table has ended, and therefore the operation in step 55-4 is ended. After the block index display lamps 18 for all currently registered data blocks are blinked in this way, the process proceeds to step S5-11.

FIG. 55 is a flowchart of the operation control at the erase operation confirmation waiting step S5-11 shown in FIG. 49.

Step S5-11 is a wait state for confirmation of the closing operation.

As shown in FIG. 55, the process waits until either the all block selection button 11 or the clear button 5 is pressed. If the all block selection button 11 is pressed (step 55-1l-1), this is regarded as an instruction to cancel the erase operation for all data blocks, and step S5
-12, and if the clear button 5 is pressed (step 55-1l-2), it is regarded as an instruction to execute the erase operation for all data blocks, and step S5-
Move to 13.

FIG. 56 is a flowchart of the operation control in step S5-12 for displaying all registered blocks and indexes 18 shown in FIG. 49.

In step S5-12, the blinking block index display lamps 18 corresponding to all currently registered data blocks are lit to inform the user that no data blocks are targeted for erasure. The flow here is basically the same as that of the all registered block index display blinking step 55-4, and as shown in FIG. 56, the initial value "l" is substituted for the reception order m and step 55-12- 1), read the block index X corresponding to the data block of reception order m 55-12-2), confirm that the block index X is not O, step 55-123);
If not O, the block index display lamp 18 corresponding to the blinking block index X is turned on (step 55-12-4), and 1 is added to the reception order m (step 55-12-5). , step 55-1 again
Return to 2-2. On the other hand, the determination in step 55-12-3 is 0.
If so, the operation at step S5-12 is ended. When the block index display lamps 18 for all currently registered data blocks are lit again, control is returned to step 55-2 for waiting for block index input.

When the clear button 5 is pressed in the erase operation confirmation waiting state step S5-11, control moves to S5-13, where all currently registered data blocks are erased.

Figure 57 shows the all data block erase S shown in Figure 49.
5-13 is a flowchart of operation control. Here, as shown in FIG. 57, first step 55-13-1
area RBLOCKSEQ of all reception order tables in
(1) ~RBLOCKSEQ (Clears 203 with 0. Next, step 55-1 determines whether this erase operation avoids a buffer full condition.
In step 3-2, it is determined whether the current remaining reception buffer amount RREM is 0 or more.

If the conditions are met, it means that the buffer is not full even before this erase operation, and the process advances to step S5-13-6. If the conditions are not met, this erase operation will avoid the buffer full state, so step 5
Proceed to 5-13-3 and here the computer control signal line-
In step 55-13-4, the computer control signal line PEC is negated to notify the computer that the printer buffer has avoided the "out of paper condition", and further in step 55-13.
At step 5, the lit buffer full indicator lamp 16 is turned off to notify the user that the buffer is no longer full, and then the process proceeds to step 55-13-6. Step 55
-13-6, the content of the empty buffer state, that is, the size of the receive buffer UMEM, is substituted for the remaining receive buffer amount RREM, as in the initial case. Subsequent step 55-13-
At step 7, "100%" is displayed on the remaining buffer/unsent data capacity display lamp I7 as a ratio of the remaining receiving buffer amount RREM to the receiving buffer size UMEM. After turning on the buffer empty indicator lamp 15 in step 55-13-8, in step 55-13-9 all data block sizes BLOCKSIZ C1] to BLOCK are turned on.
Clear SIZ (20) with Q. Subsequent step 55-
At step 13-10, the number of registered blocks RBLOCKS is cleared with O, and all data blocks are erased step S5-1.
Step 3 is completed and the process moves to step S5-14.

In step S5-14, all block index display lamps 18 are turned off to notify the user that all data blocks have been erased, and then the process proceeds to the next block index setting step S5-10.

In step S5-10, as described above, a block index RBLOCKI to be given to the next data block to be received from the computer is set in preparation for the case where the receiving operation step S3 is performed again in the future. However, in this case, there is no currently registered data block, so as shown in Figure 53, RBLOCKI
is set to the default value “1” (step 55-1O
-3) Also, the start address MEMSTA of the receive buffer is set to the start address BLOCKADR[1] of the data block with the block index "1" (step 55-1O-2).

Thereafter, the process moves to step 55-1, where the number of registered blocks is determined, but in this case, the currently registered data
Since there is no block, the data block selective clearing operation step S5 is immediately terminated.

The above is the data block selective clearing operation step S
This is the flow of step 5.

The above is the flow of operation control of the printer buffer according to the embodiment of the present invention.

(Margin below) (m) In the printer buffer which is the embodiment of the present invention described above, the start byte reception step 53-3, the data block reception step 53-7, and the blinking step 53 of the receiving indicator lamp 13. -4, buffer full status notification step 53-9
By providing this, it is possible to receive print output data from the computer regardless of the state of the printer as long as there is free space in the main memory 33 of the printer buffer.

Also, instruction waiting step S3-20, buffer full status notification stop step S3-23, received data block deletion step S3-16, received data block registration step S3-21, next block index setting step S3-22, and clearing. By providing the button 5 and the reception start/end button 6, all of the print output data stored in the main memory 33 is not erased, and prints that are only stored halfway because the main memory 33 runs out of free space can be saved. It becomes possible to erase only blocks containing output data.

〔Effect of the invention〕

As explained above, according to the present invention, when the data buffer device receives data transmitted from the data transmitting device and the storage means runs out of free space, a notification is sent to the data transmitting device to that effect. By providing the means, it is possible to receive data from the data sending device as long as there is free space in the storage means of the data buffer device, regardless of the state of the data receiving device.

Also, an erasing means for erasing from the reception buffer a block containing data that was currently being received when the storage means ran out of free space, and a block containing data that was currently being received when the storage means ran out of free space. A registration means capable of registering the block as one block, and a selection means for selecting either erasure of the block being received or registration of the block being received when there is no free space in the storage means. All outputs accumulated in the storage means are
It becomes possible to finally erase only the data of a block that has been accumulated only halfway because the storage means has run out of free space without erasing the data.

(Margin below)

[Brief explanation of drawings]

FIG. 1 is an external view of a printer buffer according to an embodiment of the present invention, FIG. 2 is a plan view of a printer buffer according to an embodiment of the present invention, and FIG. 3 is a block diagram of a printer buffer according to an embodiment of the present invention. , FIG. 4 is a diagram showing how the printer buffer is used in the embodiment of the present invention, and FIG. 5 is a diagram showing the handling of data and control signal lines at each port of the printer buffer in the embodiment of the present invention. , FIG. 6 is a conceptual diagram of data blocks in the printer buffer according to the embodiment of the present invention, FIG. 7 is a diagram showing the contents of the main memory 33 in the printer buffer according to the embodiment of the present invention, and FIG. A schematic diagram of the configuration of the control parameter table. Figure 9 is a diagram of the configuration of the environment table shown in Figure 8.
The figure is a bit configuration diagram of the initial state 5TATE of the control signal line of the computer port, Figure 11 is a configuration diagram of the block registration table shown in Figure 8, and Figure 12 is a diagram of the reception order table shown in Figure 8. 13 is a diagram showing the contents of the transmission order table shown in FIG. 8, FIG. 14 is a flowchart of operation control in the printer buffer Sl according to the embodiment of the present invention, and FIG. 16 is a diagram showing the contents. is the idle state step S2 shown in FIG.
17 is a schematic diagram of the operation control in the receiving operation step S3 shown in FIG. 14, and FIG. 18 is a flowchart of the operation control in the receiving operation condition determination step 53-1 shown in FIG. 17. Flowchart of control; FIG. 19 is a flowchart of operation control in the start byte reception step 53-3 shown in FIG. 17; FIG. 20 is a flowchart of operation control in the data block reception step 53-7 shown in FIG. 17. 21 is a flowchart of the operation control in the received data block registration step 53-8 shown in FIG. 17, and FIG. 22 is a flowchart of the operation control in the next block index setting step 53-9 shown in FIG. 17. Flowchart of operation control. FIG. 23 is a flowchart of operation control in the received data block erasing step S3-10 shown in FIG. 17. FIG. 24 is a flowchart of operation control in the instruction waiting step S3-1 shown in FIG. 17.
25 is a flowchart of the operation control in step 2, and FIG. 25 shows the received data block registration step S3-14 shown in FIG.
26 is a flowchart of operation control in the next block index setting step S3-15 shown in FIG. 17. FIG. 27 is a flowchart of operation control in the next block index setting step S3-15 shown in FIG. Flowchart of the operation control in -16, Figure 28 is the instruction waiting step S3-1 shown in Figure 17.
7, FIG. 29 is a flowchart of operation control at buffer full status notification step S3-19 shown in FIG. 17, and FIG. 30 is a flowchart of operation control at step S3-2 for waiting for instructions shown in FIG.
FIG. 31 is a flowchart of operation control at step 0, and FIG. 31 shows the received data block registration step S3-21 shown in FIG. 17.
32 is a flowchart of operation control in the next block index setting step S3-22 shown in FIG. 17. FIG. 33 is a flowchart of operation control in the next block index setting step S3-22 shown in FIG. A schematic diagram of the flow control of the operation control in S3-23, FIG. 35 is a flowchart of the operation control in the transmission operation condition determination step 54-1 shown in FIG. 34, and FIG. 37 is a flowchart of operation control in the operation preparation step 54-2, FIG. 37 is a flowchart of operation control in the transmission block selection input waiting step 54-3 shown in FIG. 34, and FIG. 38 is a flowchart of operation control in the transmission block selection input step 54-3 shown in FIG. A flowchart of the operation control in the order table erasing step 54-4, FIG. 39 shows the transmission selection block determination step 54- shown in FIG.
FIG. 40 is a flowchart of operation control at transmission selection block registration step 54-6 shown in FIG. 34; FIG. 41 is a flowchart of operation control at step 54 of registering all blocks shown in FIG.
The flowchart of operation control in 4-7, Figure 42 is
4 is a flowchart of the operation control at the transmission operation start step S4-9 shown in FIG. 4, FIG. 43 is a flowchart of the operation control at the data block transmission step S4-10 shown in FIG. Next block selection step S shown in the figure
4-12, the flowchart of the operation control in FIG. 45 is the transmission operation interruption input waiting step S4-1 shown in FIG. 34.
The flowchart of the operation control in step 3, FIG. 46, is the retransmission preparation step S4- shown in FIG. 34.
The flowchart of operation control in 14, FIG. 47 is the flowchart of operation control in 34
48 is a flowchart of the operation control in the transmission abort step S4-17 shown in FIG. 34, and FIG. 50 is a flowchart of the operation control in the block index input waiting step 55-2 shown in FIG. 49; FIG. A flowchart of operation control at the erase operation confirmation waiting step 55-6 shown in FIG. 49, and FIG. 52 is a flowchart of the operation control at the data block erase step 55-8 shown in FIG.
53 is a flowchart of operation control in the next block index setting step S5-10 shown in FIG. 49. FIG. 54 is a flowchart of operation control in the next block index setting step S5-10 shown in FIG. A flowchart of the operation control at the blinking step 55-4, FIG. 55 is a flowchart of the operation control at the erase operation confirmation waiting step S5-11 shown in FIG. 49, and FIG. 56 is a flowchart of the operation control at the erase operation confirmation waiting step S5-11 shown in FIG. 49.・Index display 1
A flowchart of the operation control in the 8-point light step S5-12, FIG. 57 is a flowchart of the operation control in the all data block erase step S5-13 shown in FIG. 49, and FIG. Figure 59 is a timing chart of the main signal lines for data transmission and reception between a general computer and a printer, and Figure 60 is a diagram showing the signal lines for data transmission and reception between a general computer and a printer. FIG. 61 is a flowchart of the print output data transmission operation on the computer side for data transmission and reception. FIG. 62 is a flowchart of the print output data reception operation on the printer side for data transmission and reception between a general computer and printer. FIG. 63 is a flowchart of the print output data transmission/reception operation in the conventional printer/buffer device. 1 is the printer buffer body, 2 is the printer port connector, 3 is the computer port connector, 4 is the reset button, 5 is the clear button, 6 is the reception start/end button, 7 is the reception interrupt button , 8 is the transmission start/end button, 9 is the transmission interrupt button, 10 is the block index button, 11 is the all block selection button, 12 is the power indicator lamp, 13 is the receiving indicator lamp, 14 is the transmitting indicator lamp , 15 is a buffer empty indicator lamp, 16 is a buffer full indicator lamp, 17 is a remaining buffer/unsent data capacity indicator lamp, 18
is the block index display lamp, 19 is the power switch, 21 is the power supply section, and 22 is the CPU. 26 is a printer port, 27 is a computer port, 29 is an input panel, 31 is a display panel, and 33 is a main memory. 7 ・ ・ ・ ・ 2 1 0 STATE
ur+defined AT"DX'r"
Lxu bu ° [ ] I can i-bufu the rough and I want you to draw Y! Sword holder material 1 "1 Yong tape) Shimi 2 'DG 7 sharpening 3-no 2 53-1'7 Fig. 32

Claims (7)

[Claims] (1) A receiving means for receiving data transmitted in blocks from a data transmitting device; an accumulating means for accumulating the received data in association with a block index, which is block identification data, for each block; A registration means for registering the block when all included data has been accumulated; a transmission means for transmitting the data of the registered block to the data receiving device; A data buffer device comprising: notification means for notifying a data sending device of this fact when the storage device runs out of free space (buffer full state). (2) The data buffer device according to claim 1, further comprising display means for displaying when the buffer is in the full state. (3) In the data buffer device according to claim 1 or 2, when the buffer becomes full, the registration means is capable of registering a block in which intermediate data is stored as one block. A data buffer device characterized by: (4) The data buffer device according to any one of claims 1 to 3, further comprising display means for displaying the block index corresponding to the registered block. buffer device. (5) In the data buffer device according to any one of claims 1 to 4, when the buffer is in a full state, erasing erases data in a block in which intermediate data has been stored. A data buffer device comprising: means. (6) The data buffer device according to claim 5, further comprising selection means for selecting and activating either the registration means or the deletion means when the buffer becomes full. A data buffer device comprising: (7) The data buffer device according to any one of claims 1 to 6, which is capable of being directly fitted with a connector of a data sending device, and is capable of receiving data from the data sending device while fitted with the connector. The present invention includes a first connector for receiving data, and a second connector that can be directly mated with a connector of a data receiving device and that transmits data to a data transmitting device while being mated with the connector. Characteristic data buffer device.