JPH0317419B2 - - Google Patents
Info
- Publication number
- JPH0317419B2 JPH0317419B2 JP59167655A JP16765584A JPH0317419B2 JP H0317419 B2 JPH0317419 B2 JP H0317419B2 JP 59167655 A JP59167655 A JP 59167655A JP 16765584 A JP16765584 A JP 16765584A JP H0317419 B2 JPH0317419 B2 JP H0317419B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- receiving circuit
- power
- output
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 15
- 230000008878 coupling Effects 0.000 claims description 14
- 238000010168 coupling process Methods 0.000 claims description 14
- 238000005859 coupling reaction Methods 0.000 claims description 14
- 230000000295 complement effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000007599 discharging Methods 0.000 description 6
- 230000001052 transient effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Circuits Of Receivers In General (AREA)
- Mobile Radio Communication Systems (AREA)
Description
【発明の詳細な説明】
発明の属する技術分野
本発明は、携帯形の移動無線機等の動作用の電
力を間欠的に供給することにより、待受け時にお
けるバツテリの消費電力の節減を図るようにした
間欠受信回路に関する。[Detailed description of the invention] Technical field to which the invention pertains The present invention aims to reduce battery power consumption during standby by intermittently supplying power for operating a portable mobile radio device, etc. The present invention relates to an intermittent reception circuit.
従来技術
第５図は、従来の間欠受信回路の一例を示す図
であり、受信回路１には電源スイツチ４を介して
間欠的に動作電源が供給される。電源スイツチ４
は、制御端子２３から入力される制御信号によつ
て周期的にオン、オフ制御されて、電源端子２４
から入力される電源を間欠的に受信回路１に供給
する。受信回路１は、電源が供給されたとき受信
入力端子２０から入力された信号を受信して受信
回路の出力端子２１に出力し、該信号は結合コン
デンサ２および負荷抵抗３から構成されるコンデ
ンサ結合回路を介して負荷端子２２に出力され
る。すなわち、受信信号は間欠的に負荷端子２２
に出力される。負荷端子２２の信号をモニタして
いて、自己が呼ばれている場合は、電源スイツチ
４を連続的にオンとして受信回路１を連続動作さ
せて通信を行なう。上述の間欠受信回路は、待受
け時の消費電力が少なくてすむため、移動機等に
使用されている。2. Prior Art FIG. 5 is a diagram showing an example of a conventional intermittent receiving circuit, in which operating power is intermittently supplied to the receiving circuit 1 via a power switch 4. As shown in FIG. Power switch 4
is periodically turned on and off by a control signal input from the control terminal 23, and the power supply terminal 24
The receiving circuit 1 is intermittently supplied with power input from the receiving circuit 1. The receiving circuit 1 receives a signal input from a receiving input terminal 20 when power is supplied, and outputs it to an output terminal 21 of the receiving circuit. It is output to the load terminal 22 via the circuit. That is, the received signal is intermittently transmitted to the load terminal 22.
is output to. The signal at the load terminal 22 is monitored, and if it is called, the power switch 4 is turned on continuously to operate the receiving circuit 1 continuously to perform communication. The above-mentioned intermittent reception circuit is used in mobile devices and the like because it consumes less power during standby.
しかし、上述の従来回路を、デジタル信号を受
信する回路に適用したときは、以下に述べるよう
な欠点がある。今、受信入力端子２０に無変調の
信号が入力されていて、電源スイツチ４が第６図
Ａに示すようにオン、オフされたとき、受信回路
１の出力端子２１の直流電圧波形が同図Ｂに示す
ように変化するものとすると、電源オン時の受信
回路の出力端子２１の電圧V2と、電源オフ時の
受信回路の出力端子２１の電圧V3（通常は０であ
る）との電圧差V1によつて結合コンデンサ２が
充電または放電される。従つて、負荷端子２２の
電圧波形は同図Ｃに示すようになる。すなわち、
入力信号が無変調であるにも拘らず、負荷端子２
２には過渡的な充放電波形が出力される。 However, when the above-described conventional circuit is applied to a circuit that receives digital signals, there are drawbacks as described below. Now, when an unmodulated signal is input to the receiving input terminal 20 and the power switch 4 is turned on and off as shown in FIG. 6A, the DC voltage waveform of the output terminal 21 of the receiving circuit 1 is Assuming that the voltage changes as shown in B, the voltage V 2 at the output terminal 21 of the receiving circuit when the power is on and the voltage V 3 at the output terminal 21 of the receiving circuit when the power is off (usually 0) The coupling capacitor 2 is charged or discharged by the voltage difference V 1 . Therefore, the voltage waveform of the load terminal 22 becomes as shown in FIG. That is,
Although the input signal is unmodulated, the load terminal 2
2, a transient charging/discharging waveform is output.
従つて、第７図Ａに示すようなデジタル波形に
よつて変調された信号が受信入力端子２０から入
力され、電源が同図Ｂに示すようにオン、オフさ
れた場合は、受信回路の出力端子２１の信号電圧
波形は同図Ｃに示すようになり、負荷端子２２の
信号電圧波形は同図Ｄに示すようになる。すなわ
ち、第６図Ｃに示したような過渡的な充放電電圧
波形にデジタル信号が重畳された電圧波形とな
る。一方、デジタル信号の検出器としては、一般
にゼロクロスコンパレータが使用されている。す
なわち、信号レベルが正のとき“１”と判定し、
信号レベルが負のとき“０”と判定する検出器で
ある。従つて、第７図Ｄに示すような信号をゼロ
クロスコンパレータで検出したときは、電源がオ
ンされてから時間Ｔの間をすべて“１”と判定
し、判定を誤つてしまうという欠点がある。この
ため、受信信号を正確に判定することができず、
例えばアドレス信号による呼出し等を検出するこ
とが困難となる。 Therefore, when a signal modulated by a digital waveform as shown in FIG. 7A is input from the receiving input terminal 20 and the power is turned on and off as shown in FIG. 7B, the output of the receiving circuit The signal voltage waveform at the terminal 21 is as shown in C in the figure, and the signal voltage waveform at the load terminal 22 is as shown in D in the figure. In other words, the voltage waveform becomes a transitional charging/discharging voltage waveform as shown in FIG. 6C, in which a digital signal is superimposed. On the other hand, a zero-cross comparator is generally used as a digital signal detector. That is, when the signal level is positive, it is determined as "1",
This is a detector that determines "0" when the signal level is negative. Therefore, when a zero-cross comparator detects a signal such as that shown in FIG. 7D, there is a drawback that all signals are determined to be "1" during the time T after the power is turned on, resulting in an erroneous determination. For this reason, it is not possible to accurately determine the received signal,
For example, it becomes difficult to detect calls based on address signals.
発明の目的
本発明の目的は、上述の従来の欠点を解決し、
電源オン時には直ちに正確に受信信号を検出する
ことができる間欠受信回路を提供することにあ
る。OBJECT OF THE INVENTION The object of the invention is to solve the above-mentioned conventional drawbacks and
An object of the present invention is to provide an intermittent reception circuit that can accurately detect a received signal immediately when the power is turned on.
発明の構成
本発明の間欠受信回路は、間欠的に電源が供給
される受信回路と、該受信回路に間欠的に電源を
供給するための電源スイツチとを備えて、前記受
信回路の出力信号をコンデンサ結合によつて負荷
に供給するようにした間欠受信回路において、前
記受信回路に供給される電圧を分圧する分圧器
と、該分圧器の出力電圧と前記受信回路の出力と
の差を増幅する差動増幅器とを備えて、該差動増
幅器の出力をコンデンサ結合によつて負荷に供給
することを特徴とする。Composition of the Invention An intermittent receiving circuit of the present invention includes a receiving circuit to which power is intermittently supplied, and a power switch for intermittently supplying power to the receiving circuit, and which outputs an output signal of the receiving circuit. In an intermittent reception circuit configured to supply a load to a load through capacitor coupling, the voltage divider divides the voltage supplied to the reception circuit, and the difference between the output voltage of the voltage divider and the output of the reception circuit is amplified. A differential amplifier is provided, and the output of the differential amplifier is supplied to a load through capacitor coupling.
発明の実施例
次に、本発明について、図面を参照して詳細に
説明する。Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.
第１図は、本発明の一実施例を示す回路図であ
る。すなわち、電源端子２４から電源スイツチ４
を通して受信回路１に電源を供給し、電源スイツ
チ４は制御端子２３から入力される制御信号によ
つて周期的にオン、オフ制御される。受信回路１
の出力端子２１は抵抗８を介して差動増幅器７の
＋入力に入力される。一方電源スイツチ４の出力
を抵抗１３と抵抗１２からなる分圧器に入力さ
せ、該分圧器の分圧出力端子２５を抵抗９を介し
て差動増幅器７の−入力に入力させる。また、差
動増幅器７の＋入力は抵抗１０によつて接地さ
れ、差動増幅器７の−入力は抵抗１１によつて差
動出力端子２６に接続されている。抵抗８および
９の抵抗値は、いずれもR1であり、抵抗１０と
１１の抵抗値は、共にR2である。今、電源オン
時における受信回路１の出力電圧の直流分がV2
であるとすれば、分圧出力端子２５の電圧がV2
になるように分圧器を調整しておく。差動増幅器
７は、受信回路の出力端子２１と分圧出力端子２
５の電圧差を増幅して差動出力端子２６に出力す
る。そして、差動出力端子２６を結合コンデンサ
２と負荷抵抗３からなるコンデンサ結合回路を介
して負荷端子２２に出力させる。 FIG. 1 is a circuit diagram showing one embodiment of the present invention. That is, from the power terminal 24 to the power switch 4
Power is supplied to the receiving circuit 1 through the power supply switch 4, and the power switch 4 is periodically controlled on and off by a control signal inputted from the control terminal 23. Receiving circuit 1
The output terminal 21 of is inputted to the +input of the differential amplifier 7 via the resistor 8. On the other hand, the output of the power switch 4 is inputted to a voltage divider consisting of a resistor 13 and a resistor 12, and the divided voltage output terminal 25 of the voltage divider is inputted via a resistor 9 to the negative input of the differential amplifier 7. Further, the +input of the differential amplifier 7 is grounded through a resistor 10, and the -input of the differential amplifier 7 is connected to a differential output terminal 26 through a resistor 11. The resistance values of resistors 8 and 9 are both R1 , and the resistance values of resistors 10 and 11 are both R2 . Now, when the power is on, the DC component of the output voltage of receiving circuit 1 is V 2
, the voltage at the divided voltage output terminal 25 is V 2
Adjust the voltage divider so that The differential amplifier 7 has an output terminal 21 of the receiving circuit and a divided voltage output terminal 2.
5 is amplified and output to the differential output terminal 26. Then, the differential output terminal 26 is outputted to the load terminal 22 via a capacitor coupling circuit consisting of a coupling capacitor 2 and a load resistor 3.
次に、本実施例の動作について、第１図および
第２図を参照して説明する。第２図は、本実施例
の各部信号を示すタイムチヤートである。今、受
信入力端子２０から第２図Ａに示すようなデジタ
ル信号が入力され、受信回路１の電源が同図Ｂに
示すようにオン、オフされるものとする。受信回
路１に電源が供給される期間においては、受信回
路の出力端子２１の信号波形は同図Ｃに示すよう
に、電圧V2を中心とする矩形波の信号となり、
受信回路１に電源が供給されない期間の電圧は通
常０となる。一方、分圧出力端子２５の電位も電
源スイツチ４がオンの期間はV2であり、電源ス
イツチ４がオフの期間は０となる。従つて、電源
スイツチ４がオンの期間では、受信回路の出力端
子２１の中心電圧（直流電圧成分）V2と分圧出
力端子２５の電圧差はなく、差動増幅器７は受信
回路１の出力信号中のデジタル信号に対応する部
分のみを増幅する。従つて、差動出力端子２６に
は、直流出力は現れず、同図Ｄに示すようにデジ
タル信号部分のみが出現する。従つて、結合コン
デンサ２には過渡的な充放電電流は流れず、負荷
端子２２の信号波形は同図Ｅに示すように、歪の
ないデジタル信号となり、ゼロクロスコンパレー
タによつて正確に判定することが可能となる。 Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. FIG. 2 is a time chart showing signals of various parts in this embodiment. Now, it is assumed that a digital signal as shown in FIG. 2A is inputted from the receiving input terminal 20, and the power of the receiving circuit 1 is turned on and off as shown in FIG. 2B. During the period when power is supplied to the receiving circuit 1, the signal waveform at the output terminal 21 of the receiving circuit becomes a rectangular wave signal centered on the voltage V2 , as shown in FIG.
The voltage during a period when power is not supplied to the receiving circuit 1 is normally zero. On the other hand, the potential of the divided voltage output terminal 25 is also V2 during the period when the power switch 4 is on, and is 0 during the period when the power switch 4 is off. Therefore, while the power switch 4 is on, there is no voltage difference between the center voltage (DC voltage component) V 2 of the output terminal 21 of the receiving circuit and the voltage divided output terminal 25, and the differential amplifier 7 outputs the output of the receiving circuit 1. Amplify only the part of the signal that corresponds to the digital signal. Therefore, no DC output appears at the differential output terminal 26, and only a digital signal portion appears, as shown in FIG. Therefore, no transient charging/discharging current flows through the coupling capacitor 2, and the signal waveform at the load terminal 22 becomes an undistorted digital signal as shown in Figure E, which can be accurately determined by the zero-cross comparator. becomes possible.
しかし、例えば、大地から浮いた電源から受信
回路１に電源を供給し、そのオン、オフ制御を片
線のオン、オフで行なうような場合は、電源スイ
ツチ４をオフした状態で、受信回路の出力端子２
１に一定の残留電圧V3が出力されることがある。
このようなときは、電源オン時に分圧出力端子２
５に出力される電圧がV2−V3（＝V1）となるよ
うに設定すれば、差動出力端子２６の直流電圧成
分は電源オン時にはkV3（ただし、ｋは差動増幅
器７の電圧利得）となり、電源オフ時にもkV3と
なるから、上述と同様に結合コンデンサ２に過渡
的な充放電電流を流さないで、負荷端子２２には
デジタル信号のみを取出すことができる。 However, for example, when power is supplied to the receiving circuit 1 from a power source floating above the ground, and its on/off control is performed by turning on and off one wire, the receiving circuit is Output terminal 2
1, a constant residual voltage V 3 may be output.
In such a case, when the power is turned on, the divided voltage output terminal 2
5, the DC voltage component of the differential output terminal 26 is kV 3 (k is the voltage of the differential amplifier 7 ) when the power is turned on. Since the voltage gain is kV 3 even when the power is turned off, only a digital signal can be taken out to the load terminal 22 without causing any transient charging/discharging current to flow through the coupling capacitor 2, as described above.
第３図は、本発明の他の実施例を示す回路図で
あり、第４図はその各部信号を示すタイムチヤー
トである。第一の実施例において、分圧出力端子
２５の電位を電源オンの期間にV2に設定すると、
この期間での差動増幅器出力端子２６の直流電圧
は０となる。一方、電源オフの期間では分圧出力
端子２５の電圧は０であるので、受信回路１の残
留電圧V3が差動増幅器で増幅されて、出力端子
２６の直流電圧はkV3（ただし、ｋは差動増幅器
７の電圧利得）となる。このため、電源オンの期
間の直流電圧０と電源オフの期間の直流電圧kV3
との間でステツプ状に変わり、過渡的な充放電電
流が結合コンデンサに流れ、電源オンの期間での
ゼロクロスコンパレータによるデイジタル信号の
判定に誤差が生じるという不都合が生じる。本実
施例は、この不都合を解消するものであり、電源
端子２４から電源スイツチ４を通して受信回路１
および抵抗１３，１２からなる（第１の）分圧器
に電源を供給することは前述の実施例と同様であ
るが、電源端子２４からスイツチング素子５を通
して抵抗１５と１４からなる第２の分圧器に接続
し、制御端子２３から入力される制御信号をイン
バータ６で反転させてスイツチング素子５をオ
ン、オフ制御させることにより、電源スイツチ４
とスイツチング素子５を相補的にオン、オフさせ
る。そして、上記第２の分圧器の出力を分圧出力
端子２５に接続し、受信回路１に電源を供給しな
い期間に受信回路の出力端子２１に出力される残
留電圧V3を上記第２の分圧器の出力電圧によつ
てキヤンセルするように設定する。なお、前記第
１の分圧器の出力は、電源オン時の受信回路１の
直流出力電圧V2に設定する。従つて、今、受信
入力端子２０から第４図Ａに示すようなデジタル
信号が入力され、受信回路１の電源が同図Ｂに示
すようにオン、オフされるものとすると、受信回
路の出力端子２１の信号波形は同図Ｃに示すよう
に、受信回路１に電源が供給される期間において
は電圧V2を中心とする矩形波の信号となり、受
信回路１に電源が供給されない期間には残留電圧
V3となる。一方、分圧出力端子２５の電位は、
同図Ｄに示すように、電源スイツチ４がオンの期
間V2であり、電源スイツチ４がオフの期間はV3
となる。従つて、電源スイツチ４がオンの期間で
は、受信回路の出力端子２１の中心電圧（直流電
圧）V2と分圧出力端子２５の電圧差はなく、差
動増幅器７は受信回路１の出力信号中のデジタル
信号信号に対応する部分のみを増幅する。また、
電源スイツチ４のオフ期間には受信回路の出力端
子２１と分圧出力端子２５の電位差はなく、差動
出力端子２６には、直流出力は現れない。従つ
て、差動出力端子２６の信号波形は、同図Ｅに示
すように電源オン期間、オフ期間ともに直流成分
のないデジタル信号部分のみが出現する。従つ
て、電源オン、オフ期間にかかわらず。差動出力
端子２６の直流成分は0Vであるので、結合コン
デンサ２には過渡的な充放電電流は流れず、負荷
端子２２の信号波形は同図Ｆに示すように、歪の
ないデジタル信号となり、ゼロクロスコンパレー
タによつて正確に判定することが可能となる。す
なわち、電源オフの期間に受信回路１の出力に残
留電圧が発生するような場合でも、負荷コンデン
サ２に充放電電流が流れることがなく、かつ、第
一の分圧器の出力電圧を受信回路１の残留電圧が
ある／なしに関わらす、常にV2に固定的に設定
可能であるという利点がある。 FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 is a time chart showing signals of various parts thereof. In the first embodiment, when the potential of the divided voltage output terminal 25 is set to V 2 during the power-on period,
The DC voltage at the differential amplifier output terminal 26 during this period becomes zero. On the other hand, during the power-off period, the voltage at the divided voltage output terminal 25 is 0, so the residual voltage V 3 of the receiving circuit 1 is amplified by the differential amplifier, and the DC voltage at the output terminal 26 is kV 3 (kV 3 is the voltage gain of the differential amplifier 7). Therefore, the DC voltage during the power-on period is 0 and the DC voltage during the power-off period is kV 3
A transient charging/discharging current flows through the coupling capacitor, causing an inconvenience in that an error occurs in the judgment of the digital signal by the zero-cross comparator during the power-on period. This embodiment solves this problem, and connects the receiving circuit 1 from the power terminal 24 through the power switch 4.
The power is supplied to the (first) voltage divider consisting of the resistors 13 and 12 in the same way as in the previous embodiment, but the second voltage divider consisting of the resistors 15 and 14 is supplied from the power supply terminal 24 through the switching element 5. By connecting the control signal input from the control terminal 23 to the inverter 6 and controlling the switching element 5 on and off, the power switch
The switching element 5 is turned on and off in a complementary manner. Then, the output of the second voltage divider is connected to the divided voltage output terminal 25, and the residual voltage V 3 outputted to the output terminal 21 of the receiving circuit during the period when power is not supplied to the receiving circuit 1 is outputted to the second voltage divider. Set to cancel depending on the output voltage of the voltage generator. Note that the output of the first voltage divider is set to the DC output voltage V 2 of the receiving circuit 1 when the power is turned on. Therefore, if a digital signal as shown in FIG. 4A is input from the receiving input terminal 20 and the power of the receiving circuit 1 is turned on and off as shown in FIG. 4B, the output of the receiving circuit will be As shown in Figure C, the signal waveform of the terminal 21 becomes a rectangular wave signal centered on the voltage V2 during the period when power is supplied to the receiving circuit 1, and becomes a rectangular wave signal centered on the voltage V2 during the period when the receiving circuit 1 is not supplied with power. residual voltage
It becomes V3 . On the other hand, the potential of the divided voltage output terminal 25 is
As shown in figure D, the period when the power switch 4 is on is V2 , and the period when the power switch 4 is off is V3.
becomes. Therefore, while the power switch 4 is on, there is no voltage difference between the center voltage (DC voltage) V 2 of the output terminal 21 of the receiving circuit and the voltage divided output terminal 25, and the differential amplifier 7 receives the output signal of the receiving circuit 1. Only the part corresponding to the digital signal inside is amplified. Also,
During the off period of the power switch 4, there is no potential difference between the output terminal 21 of the receiving circuit and the voltage divided output terminal 25, and no DC output appears at the differential output terminal 26. Therefore, in the signal waveform of the differential output terminal 26, only a digital signal portion without a DC component appears during both the power-on period and the power-off period, as shown in FIG. Therefore, regardless of whether the power is on or off. Since the DC component of the differential output terminal 26 is 0V, no transient charging/discharging current flows through the coupling capacitor 2, and the signal waveform of the load terminal 22 becomes a distortion-free digital signal as shown in Figure F. , it becomes possible to make accurate determinations using a zero-cross comparator. In other words, even if a residual voltage occurs in the output of the receiving circuit 1 during the power-off period, no charge/discharge current flows to the load capacitor 2, and the output voltage of the first voltage divider is transferred to the receiving circuit 1. It has the advantage that it can always be fixedly set to V 2 regardless of whether there is a residual voltage or not.
発明の効果
以上のように、本発明においては、受信回路の
出力電圧の直流成分をキヤンセルするための分圧
器を備えて、前記受信回路の出力と上記分圧器の
出力電圧の差を差動増幅器で増幅することによつ
て受信回路の出力から直流成分を除去した信号を
出力するように構成したから、間欠的電源供給に
よつて結合コンデンサに過渡的な充放電電流が流
れることを防止し、入力デジタル信号を正確に判
定することが可能となるという効果を有する。Effects of the Invention As described above, the present invention includes a voltage divider for canceling the DC component of the output voltage of the receiving circuit, and converts the difference between the output voltage of the receiving circuit and the output voltage of the voltage divider into a differential amplifier. Since the configuration is configured to output a signal with the DC component removed from the output of the receiving circuit by amplifying it with This has the effect of making it possible to accurately determine the input digital signal.
第１図は本発明の一実施例を示す回路図、第２
図は上記実施例の各部信号を示すタイムチヤー
ト、第３図は本発明の他の実施例を示す回路図、
第４図は上記実施例の各部信号を示すタイムチヤ
ート、第５図は従来の間欠受信回路の一例を示す
回路図、第６図は上記従来例の無変調信号入力時
の各部信号を示すタイムチヤート、第７図は上記
従来例のデジタル信号入力時の各部信号を示すタ
イムチヤートである。
図において、１：受信回路、２：結合コンデン
サ、３：負荷抵抗、４：電源スイツチ、５：スイ
ツチング素子、６：インバータ、７：差動増幅
器、８〜１５：抵抗、２０：受信入力端子、２
１：受信回路の出力端子、２２：負荷端子、２
３：制御端子、２４：電源端子、２５：分圧出力
端子、２６：差動出力端子。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a time chart showing various signals of the above embodiment, and FIG. 3 is a circuit diagram showing another embodiment of the present invention.
Fig. 4 is a time chart showing the signals of each part of the above embodiment, Fig. 5 is a circuit diagram showing an example of a conventional intermittent reception circuit, and Fig. 6 is a time chart showing the signals of each part of the above conventional example when an unmodulated signal is input. FIG. 7 is a time chart showing signals of various parts when digital signals are input in the conventional example. In the figure, 1: receiving circuit, 2: coupling capacitor, 3: load resistor, 4: power switch, 5: switching element, 6: inverter, 7: differential amplifier, 8 to 15: resistor, 20: receiving input terminal, 2
1: Output terminal of receiving circuit, 22: Load terminal, 2
3: Control terminal, 24: Power supply terminal, 25: Voltage division output terminal, 26: Differential output terminal.
Claims (1)
信回路に間欠的に電源を供給するための電源スイ
ツチとを備えて、前記受信回路の出力信号をコン
デンサ結合によつて負荷に供給するようにした間
欠受信回路において、前記受信回路に供給される
電圧を分圧する分圧器と、該分圧器の出力電圧と
前記受信回路の出力との差を増幅する差動増幅器
の出力をコンデンサ結合によつて負荷に供給する
ことを特徴とする間欠受信回路。 ２ 間欠的に電源が供給される受信回路と、該受
信回路に間欠的に電源を供給するための第一の電
源スイツチとを備えて、前記受信回路の出力信号
をコンデンサ結合によつて負荷に供給するように
した間欠受信回路において、前記受信回路に供給
される電圧を分圧する第１の分圧器と、前記第一
の電源スイツチと相補的にオン・オフされる第二
の電源スイツチと、該第二の電源スイツチに接続
された第２の分圧器とを備えて、前記受信回路に
電源を供給する期間は前記第１の分圧器の出力電
圧と前記受信回路の出力との差を増幅する差動増
幅器の出力をコンデンサ結合によつて負荷に供給
し、前記受信回路に電源を供給しない期間は前記
第２の分圧器の出力電圧と前記受信回路の出力と
の差を増幅する差動増幅器の出力をコンデンサ結
合によつて負荷に供給することを特徴とする間欠
受信回路。[Scope of Claims] 1. A receiver circuit comprising: a receiving circuit to which power is intermittently supplied; and a power switch for intermittently supplying power to the receiving circuit; The intermittent receiving circuit includes a voltage divider that divides the voltage supplied to the receiving circuit, and a differential amplifier that amplifies the difference between the output voltage of the voltage divider and the output of the receiving circuit. An intermittent receiving circuit characterized in that an output is supplied to a load through capacitor coupling. 2. A receiving circuit that is intermittently supplied with power and a first power switch for intermittently supplying power to the receiving circuit, the output signal of the receiving circuit being connected to a load by capacitor coupling. A first voltage divider that divides the voltage supplied to the receiving circuit; a second power switch that is turned on and off complementary to the first power switch; a second voltage divider connected to the second power switch, and amplifies the difference between the output voltage of the first voltage divider and the output of the reception circuit during the period when power is supplied to the reception circuit. The output of the differential amplifier is supplied to the load through capacitor coupling, and during the period when power is not supplied to the receiving circuit, the differential amplifier amplifies the difference between the output voltage of the second voltage divider and the output of the receiving circuit. An intermittent receiving circuit characterized in that the output of an amplifier is supplied to a load through capacitor coupling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59167655A JPS6146633A (en) | 1984-08-10 | 1984-08-10 | Circuit of intermittent reception |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59167655A JPS6146633A (en) | 1984-08-10 | 1984-08-10 | Circuit of intermittent reception |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6146633A JPS6146633A (en) | 1986-03-06 |
| JPH0317419B2 true JPH0317419B2 (en) | 1991-03-08 |
Family
ID=15853780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59167655A Granted JPS6146633A (en) | 1984-08-10 | 1984-08-10 | Circuit of intermittent reception |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6146633A (en) |
-
1984
- 1984-08-10 JP JP59167655A patent/JPS6146633A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6146633A (en) | 1986-03-06 |
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