JPH031740A - Data transmission circuit - Google Patents

Abstract

PURPOSE:To prevent the deviation of a tuning frequency based on a change in the ambient temperature by providing the reception circuit side with a couple of switched capacitor filters(SCF) separating a transmission signal into two reception signals different in frequency. CONSTITUTION:A couple of SCFs 22, 23 are provided to a reception circuit 5 to separate the frequency of a received FSK (frequency transit modulation) signal 21S and the sampling clocks 42S, 43S of the SCFs 22, 23 are obtained by utilizing a crystal oscillator 11 and programmable counters 12, 13. Thus, the SCFs 22, 23 acting like a resistor equivalently do not include a resistance or inductance element having a large temperature dependency and the sampling clocks 42S, 43S are kept easily and accurately to a degree from a multiple of 50-100 of the tuning frequency of the SCF. Thus, the data transmission circuit of the FSK system with high frequency selectivity whose frequency selectivity change is less than 1% over a wide temperature range is obtained without complicating the circuit constitution.

Description

Detailed Description of the Invention [Field of Industrial Application] This invention uses a frequency shift keying method (hereinafter referred to as FSX) to transmit data between a pair of transmission devices that are interconnected using bare cables or distribution lines as transmission paths. This invention relates to data transmission circuits (abbreviated as ``systems''), and particularly to circuit configurations of transmission devices.

[Conventional technology]

FIG. 5 is a block diagram showing the general configuration of a data transmission circuit, and FIG. 6 is a time chart showing the principle of the FSK system. In Figure 1, IA and IB are different locations A and B.
A data transmission device arranged in The transmission devices iA and iB are connected to each other as line 2 to perform one-way communication.

In the F'SK type data transmission circuit, as shown in FIG.
The transmission circuit 4 encodes the data signal corresponding to the
At A, the H signal has a frequency f2sThe L signal has a frequency fl and the amplitude V is equal to each other, and is multiplexed into an F'SK signal of a multiplexed frequency that satisfies the condition fl)f2, and the transmission line 2
The received signal is transmitted to the receiving circuit 5B on the transmission device 1B side via the transmitter 1B. Receiving circuit 5B receiving this signal receives FSK signal station wave number component element 1 and f! The signal is demodulated into a demodulated data signal on the receiving side by the demodulation circuit and outputted to the CPU 3B. -! Further, the function of the demodulation circuit may be provided in the CPU 6B, and the same applies to transmission from the transmission device 1B side.

By the way, in the conventional device, the receiving circuit separates frequency component 1 in the FSX signal by fxft, but fl+f2
There is a known configuration in which two sets of LC filters or active filters are provided which are respectively tuned to each other, and a CPU determines which filter has a voltage via a demodulation circuit.

[Problems to be Solved by the Invention] The two sets of LC filters or active filters used in the conventional device are adjusted to tune to the frequency 1- or f2, respectively, at room temperature of about 23°C. However, these filter circuits use C and R elements, and each filter has different temperature characteristics, so one filter is used. There is a problem in that it is difficult to accurately maintain f2, and the frequency selectivity Q and gain H of the filter change as the ambient temperature changes. Such a change causes a large difference in the level of two frequency-separated received signals that should originally have the same amplitude v2.Depending on the magnitude of the amplitude V2, whether a 0-level signal or a level signal is received is determined. This poses a problem in that the CPU, which judges whether the data is accurate or not, makes an erroneous judgment.

An object of the present invention is to improve the circuit configuration of a receiving circuit.
The objective is to completely prevent shifts in the tuning frequency due to changes in ambient temperature and to avoid misjudgment of received data signals.

[Means to solve all problems]

In order to solve all of the above-mentioned problems, according to the present invention, a pair of transmission devices coupled via a transmission line is provided with a transmission circuit and a reception circuit each controlled by a microprocessor, and a logic 0, 1 is coded. In a data transmission circuit using a frequency shift keying method, which converts a converted data signal into two corresponding frequency signals and transmits the same, the transmitting circuit includes one crystal oscillator and its output frequency is set to 0. It is equipped with a pair of counter circuits that divide two frequency signals corresponding to the frequency, and is controlled by a sampling clock generated by the pair of counter circuits to separate the transmitted signal into received signals of the two frequencies. A pair of switched capacitor filters are provided on the receiving circuit side.

[Effect]

The above means is a switched capacitor filter (hereinafter referred to as SC).
(abbreviated as F') is not a circuit that can be equivalently regarded as a resistance by combining a capacitor and an analog switch, but it is a circuit that forms an active RC filter by this equivalent resistance and a separate capacitor, and its frequency selectivity Q is determined by the period of the sampling clock for tuning supplied to SCF', and the frequency of the sampling clock must be kept accurately at about 50 or 100 times the total tuning frequency f1 or f2, and the ambient temperature. -50℃ to +80℃
Frequency selectivity Ql is about 1% even if it changes over a wide range.
It was constructed with a focus on having performance that can be maintained under the following changes.During transmission, the accurate lock generated by the crystal oscillator is controlled by a pair of programmable counters whose frequency division ratio is controlled by the CPU. and f2, and put the F'SK signal on the transmission line from the transmitting circuit, and at the time of reception, the SCF sampling clock of 2ff, (1) is set in the receiving circuit of the FSK signal. , by changing the frequency division ratio of the programmable counter, the received FSKS is reduced.
It is possible to obtain a receiving circuit that can perform frequency separation by keeping the selectivity Q for the intermediate signal frequency component element 1 + f2 within an error range of 1% or less over a wide temperature range, and therefore a data transmission circuit with high transmission and reception efficiency of data signals. is obtained.

〔Example〕

The present invention will be explained below based on examples.

FIG. 1 is a block diagram showing a circuit according to an embodiment of the present invention, and shows one of two transmission devices connected via a transmission line 2. In FIG. However, since the circuit configurations of the two transmission devices are the same, the transmitting circuit and the receiving circuit will be explained below using the transmitting circuit and the receiving circuit shown in the figure as a representative.

In the figure, 4 is a transmitting circuit controlled by the CPU 3, and 5 is a receiving circuit that processes signals from the CPUK. The transmitting circuit 4 includes a crystal oscillator 11 that outputs 12.24 MH2O and 11S. Programmable counters 12 and 16 receive the clock 118 and division ratio setting signals 323 and 338 from the CPU and output signals 128 and 133' with frequencies f and fl, respectively, and gate signals 358 and 36St from the CPU, respectively. A pair of AND gates 15 and 16, which are turned on in response to the signal and pass the signal 12S or 13S, and an OR gate 1
A transmission modulation section 18.7 sequentially receives signals 12S and 13St- via signals 12S and 13St, shapes them into a sine wave, and outputs them as an FSK signal 18S. and a transmission coupling unit 19 that modulates the FSX signal 18Se signal with the voltage of the distribution line 2 as a transmission line and outputs it as a transmission F'SK signal 4S.

On the other hand, the receiving circuit 5 includes a receiving coupling section 21 that receives the transmitted FSK signal 4S modulated by the voltage of the power distribution line 2, demodulates it into a received PSK signal 218, and matches the impedance thereof,
It is composed of a pair of switched capacitor filters (SCF') 22 and 23 that separate the SK signal 21S into two received signals 228 and 238 having frequencies fl and f2, and the CPU 3 receives the received signals 228 and 233 based on the amplitude V. The data is transmitted by converting the signal into a demodulated data signal corresponding to logical 0 and 1 based on the determination.

Fig. 2 is an explanatory diagram of the operation of the main part of the transmitting circuit, Fig. 3 is an explanatory diagram of the operation of the main part of the receiving circuit, and Fig. 4 is a time chart of the transmitting circuit and the receiving circuit. The operation will be explained. In FIG. 2, a 12°24 MHz clock 118 generated by a crystal oscillator 11
is the frequency f by the programmable color/res 12 set to a division ratio of 1700 by the signal 328 from the CPU.
! is 12.24MHz÷1700=7200Hz frequency signal 123 and signal 33S, the division ratio is 1800.
The frequency f1 is set to 12.
24MHz÷1800=6800Hz frequency signal 13
8 and a frequency signal 12S (lt, AND
The one frequency multiple 138 of the gate 15 is input to the AND gate 16, respectively. The AND gate 16 is turned on for a period corresponding to one bit Ic by a gate signal 368 corresponding to the H level of the encoded data signal shown in FIG.
Frequency f.

=6800H2 (7) Frequency signal 138t-output, A
The ND gate 15 is kept on for a period corresponding to the sylla bit by a gate signal 358 corresponding to the L level of the data signal, and outputs a frequency signal 12S with a frequency fx=7200H2. The two frequency signals 12S and 133 are sent to the transmission modulator 18 via the OR gate 17 as shown in FIG. 1, and as shown in FIG. K data signal L level, H
Multi-page frequency ft=7200Hz$ and f*=6
Receiving side F'SK signal 18 of sine wave modulated at 80QHz
S, and the distribution line 2 as a transmission line is connected at the transmission Ig coupling part 19.
It is converted into a transmission F'SK signal modulated by the commercial frequency voltage of , and is transmitted to the reception circuit 5 which is actually located at a remote location via the arrangement line 2, and is transmitted to the reception coupling section 2 of the reception circuit 5.
1, the commercial frequency component is removed and the receiving side F'SK signal 218 is demodulated.

The pair of SCF's 22 and 23 in the receiving circuit 5 receives sampling clocks 428 and 43 generated by the pair of programmable counters 12 and 13 in the transmitting circuit 4, as shown in FIG.
3 controls the respective tuning frequencies f1 and f2. In other words, the tuning frequency of FSX is changed from -50℃ to +
Its frequency selectivity Q is 1 over a wide temperature range of 80℃.
To keep the error within %, K is the tuning frequency Ex
Sampling clocks 428, 438' and corresponding to 50 to 100 times t or f2 are required. Therefore, by setting the frequency division ratio of the programmable counter 12 to 64, which corresponds to 1/50th of the frequency division ratio of 1700 at the time of full transmission, and setting the frequency division ratio of the counter 13 to 36, the filters 22 and 23 can be Analog switch with respective tuning frequency f1 = 720QHz and fz = 6800Hz
(The original clock 423,438 with a frequency of 360 KHz and 34 Q KHz corresponding to D% = 50 times
As shown in Figure 4, SCF'
From 23 onwards, only the tuning frequency fz=6800Hz component has a large amplitude V, and the f2 tuned reception/reception signal 23 has a high gain H.
S is obtained, and from SCF'22 the tuning frequency f1==7
A high f1 tuned reception/reception signal 228 with a high gain H in which only the 200 Hz acid component has a large amplitude vl is obtained.

Therefore, the CPU 3 receives the two received signals 238 and 2.
2S'e By performing demodulation with discrimination based on the amplitude V, a received data signal (not shown) similar to the encoded data signal shown in the top row of FIG. 4 can be obtained.

〔Effect of the invention〕

As described above, this invention provides a pair of SCF's in the receiving circuit to perform frequency separation of the received FSX signal, and also performs frequency separation of the received FSX signal.
The CF sampling clock was configured to be obtained using a crystal oscillator and a programmable counter in the transmitting circuit. As a result, the SCF, which functions isometrically as a resistor in combination with a capacitor and an analog switch, does not contain any highly temperature-dependent resistance or inductance elements, and therefore has a wider current flow than conventional devices using LC filters or active filters. By using one crystal oscillator and a pair of programmable counters in the transmitter circuit, the sampling clock necessary to maintain the frequency selectivity of the SCF accurately is obtained. Since the tuning frequency can be easily and accurately maintained at about 50 to 100 times the tuning frequency of SCF',
It is possible to provide a highly selective SK type data transmission circuit with a change in frequency selectivity reduced to 1% or less over a wide performance range from -50°C to +80°C without complicating the circuit configuration. , the frequency discrimination performance of the received signal is improved by improving the frequency selectivity and the gain H, so that the logic 0. This provides the advantage of preventing erroneous judgments of data signals encoded by the Lebel code.

In addition, since the tuning frequency of the scF can be easily determined by setting the frequency division ratio of the programmable counter, there is no need for fine adjustment of the filter circuit in conventional equipment, resulting in time-saving and labor-saving effects by shortening the adjustment time. effect.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of Jin's invention;
Figure 3 is an explanatory diagram of the operation of the main parts of the embodiment transmitting circuit, Figure 3 is a diagram explaining the operation of the main parts of the embodiment reception circuit, Figure 4 is a time chart of the main parts of the embodiment circuit, and Figure 5 is the data FIG. 6 is a block diagram showing the general configuration of the transmission circuit, and a time chart showing the principle of the FSK system. iA, 1B...Data transmission device, 2...Transmission line, 3
A, 3B... Microprocessor (CPU), 4 A
.

Claims (1)

[Claims] 1) A pair of transmission devices connected via a transmission line each include a transmitting circuit and a receiving circuit controlled by a microprocessor, and transmit data signals encoded as logic 0 and 1 to two corresponding frequency signals. In a frequency modulation type data transmission circuit that transmits data by changing to
, a pair of counter circuits that divide the frequency into two frequency signals corresponding to one level, and the transmission signal is controlled by a sampling clock generated by the pair of counter circuits to separate the transmission signal into reception signals of the two frequencies. 1. A data transmission circuit comprising: a pair of switched capacitor filters on the receiving circuit side.