JPH03171753A - Production system of semiconductor element - Google Patents
Production system of semiconductor elementInfo
- Publication number
- JPH03171753A JPH03171753A JP31097689A JP31097689A JPH03171753A JP H03171753 A JPH03171753 A JP H03171753A JP 31097689 A JP31097689 A JP 31097689A JP 31097689 A JP31097689 A JP 31097689A JP H03171753 A JPH03171753 A JP H03171753A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- semiconductor
- host computer
- reading
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000012545 processing Methods 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000001459 lithography Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 2
- 238000003754 machining Methods 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 15
- 235000012431 wafers Nutrition 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は、半導体素子の生産システムに係わり、特に、
安定した特性や品質が得られるものである.
(従来の技術)
半導体素子の製造に当たっては,例えばシリコン半導体
ウエーハ(以後基板と記載する)に受動素子や能動素子
を追込んでから,個々の素子に分断する方式が採用され
ている。ところで半導体素子の組立工程は、かなり古い
時期から自動化が進められていたのに対して、半導体基
板に受動素子や能動素子を追込む工程の自動化は、前者
に比べればかなり新しい時期にスタートしている.その
前提としては,各種の素子を追込むのに必要な基礎的デ
ータの集積が整ったために進められて、省力化に大きく
貢献している.この結果、極めて正確に制御・維持され
た清浄度のもとに設置された製造ラインには、最も大き
なゴミの発生源である人間が関与する頻度が極端に少な
くなっており、最近のように集積度が増大した半導体素
子の歩留り向上にも寄与するところが極めて大きい.一
方.半導体素子に必要な単結晶の寸法も向上されて製造
ラインに投入されるものは、5インチや6インチのサイ
ズ(Size)の外により大形のものも登場して,生産
性の向上に大きく役立っているのが現状である.
ところで,省力化された製造ラインでは、コンピュータ
制御方式が採用されており、被処理半導体基板は,ロフ
ト単位(半導体基板25〜50枚が1ロット)で処理さ
れ、加工単位もロット単位である.また、このコンピュ
ータ制御方式では、コンピュータに結ばれた測定器が設
置されており,その結果からコンピュータが求めた加工
条件により所定の特性値を持った半導体素子が製造され
ている。従って,特性値の測定も半導体素子を追込んだ
1〜数枚の半導体基板即ちロット内のl〜数枚を測定し
、代表値とする方式が採られている。また、製造装置用
の加エデータもロット単位で設定している。[Detailed description of the invention] [Object of the invention] (Industrial application field) The present invention relates to a production system for semiconductor devices, and in particular,
Stable characteristics and quality can be obtained. (Prior Art) In manufacturing semiconductor devices, for example, a method is used in which passive devices and active devices are placed on a silicon semiconductor wafer (hereinafter referred to as a substrate) and then the wafer is divided into individual devices. By the way, while the process of assembling semiconductor elements has been automated for quite some time, the automation of the process of adding passive and active elements to semiconductor substrates started at a much newer time than the former. There is. The premise is that the basic data required to develop various elements has been accumulated, and this has greatly contributed to labor savings. As a result, production lines, which are set up with extremely precisely controlled and maintained cleanliness levels, have far less human interaction, which is the biggest source of waste, and It also greatly contributes to improving the yield of semiconductor devices with increased integration. on the other hand. As the dimensions of the single crystals required for semiconductor devices have improved, the size of the single crystals that are put into production lines is now larger than 5 inches or 6 inches, which has greatly improved productivity. The current situation is helpful. By the way, the labor-saving manufacturing line employs a computer control system, and the semiconductor substrates to be processed are processed in units of lofts (25 to 50 semiconductor substrates in one lot), and the processing unit is also in units of lots. Furthermore, in this computer control method, a measuring instrument connected to a computer is installed, and semiconductor elements having predetermined characteristic values are manufactured according to processing conditions determined by the computer from the results. Therefore, the characteristic values are measured by measuring one to several semiconductor substrates on which semiconductor elements are mounted, that is, one to several semiconductor substrates in a lot, and using the results as representative values. Additionally, processing data for manufacturing equipment is also set on a lot-by-lot basis.
(発明が解決しようとする課題)
このように従来の製造システムでは、バッチ処理が採用
されており、ロフトを代表する特性データは僅か数点で
決められるために個々の半導体基板の特性を代表しない
,しかも実際の半導体素子の製造工程は、複数の処理工
程を経なければならず最終的には,単一工程に生じるバ
ラツキが増幅されることになり、個々の特性に大きな差
が生じることになる.
本発明は、このような事情により威されたもので、特に
、半導体素子を追込む半導体基板の特性値を個々に管理
して,次工程にフィードバック(Feed Back)
することにより最終の素子特性の変動を最小に抑制する
ことを目的とするものである。(Problem to be solved by the invention) In this way, conventional manufacturing systems employ batch processing, and the characteristic data representing the loft is determined at only a few points, so it does not represent the characteristics of each individual semiconductor substrate. Moreover, the actual manufacturing process for semiconductor devices requires multiple processing steps, and in the end, variations that occur in a single process are amplified, resulting in large differences in individual characteristics. Become. The present invention was developed under these circumstances, and in particular, it is a method for individually managing the characteristic values of a semiconductor substrate on which semiconductor elements are mounted and feeding them back to the next process.
The purpose of this is to minimize fluctuations in the final device characteristics.
(課題を解決するための手段)
半導体素子の特性を測定する測定器と、この半導体素子
を半導体基板に追込む製造用装置をオンライン接続した
コンピュータを備えた半導体素子の生産システムにおい
て、各測定器及び製造装置に半導体基板枝葉番号を読取
る装置を設け,半導体基板単位の特性資料を記録したコ
ンピュータで製造装置における加工条件を決定してから
加工する点に本発明に係わる半導体素子の生産システム
の特徴がある.
(作 用)
本発明に係わるシステムでは、各処理工程後に稼働させ
る特性測定器に半導体基板Nα(以後番号と記載する)
の読取装置を付属させて、測定結果の特性及び半導体基
板番号をホストコンピュータに登録する。これ以降にあ
っても被処理半導体基板の番号を読取り以前の工程の特
性値の狙い値を基にして予め用意されたアルゴリズム(
Algorithm)により半導体基板の処理条件を設
定する。被処理半導体基板をバッチ(Batch)処理
する場合には,特性値によるクラス分け及び予め判明し
ている位置による特性値の傾向により場所を決めて処理
して補正し、枝葉処理装置にあっては、各半導体基板毎
に行う。これら一連の補正処理は、コンピュータの演算
処理による.
(実施例)
以後第1図乃至第3図を参照して本発明に係わる実施例
を説明する.即ち、製造装置及びコンピュータを利用す
る一連の処理工程は、適正在庫を前提とするものである
.
第1図には、本発明の概要を示したが、測定器・製造装
置3は,中間コンピュータ2を介してホストコンピュー
タ1に接続する.測定器・製造装置3には、半導体基板
番号の読取装w4を付属させる.図中矢印は、被処理半
導体基板の流れつまり処理の順序を表わしており、ホス
トコンピュータ1と中間コンピュータ2は、LANで接
続し、中間コンピュータ2及び測定器・製造装fi3は
l対1の通信主にSECS (Semiconduct
er EquipmentComunication
Standard) I、■により接続している, (
SECS− Iがこれに相当する)また,半導体基板番
号の読取装1114は,8I!定器・製造装I13また
は中間コンピュータ2に接続されているが、第1図では
、測定器・製造装!!3に接続した状態が示されている
.
処理手順の一例として多結晶珪素抵抗形或工程により説
明すると.先ず.製造装113aにより半導体基板に多
結晶珪素をデポ(Deposition)後、測定器3
bにより膜厚を測定するが,被処理半導体基板番号を読
取装置4により読取り、測定結果を中間コンピュータ2
を介してホストコンピュータlに転送・保存する.その
フォーマット(Format)の例を第2図に示したが
、半導体基板をウエーハ(Wafer)と記載した.
この例に明らかなように、品種名、ロットNα、工程名
、ロット代表値、ウエーハ&1及び特性値が表示されて
おり当然被処理半導体基板番号毎に測定して特性値を表
示する.しかし、製造装l13における処理後の特性値
の傾向即ちバラツキの傾向によっては,必ずしも全半導
体基板を測定しなくても良い。(Means for solving the problem) In a semiconductor device production system equipped with a computer that is online connected to a measuring device that measures the characteristics of a semiconductor device and a manufacturing device that drives the semiconductor device onto a semiconductor substrate, each measuring device A feature of the semiconductor device production system according to the present invention is that the manufacturing equipment is equipped with a device that reads the semiconductor substrate branch number, and the processing conditions in the manufacturing equipment are determined by a computer that records the characteristic data of each semiconductor substrate before processing. There is. (Function) In the system according to the present invention, a semiconductor substrate Nα (hereinafter referred to as a number) is attached to a characteristic measuring device operated after each processing step.
A reading device is attached, and the characteristics of the measurement results and the semiconductor substrate number are registered in the host computer. Even after this, the number of the semiconductor substrate to be processed is read and an algorithm (
The processing conditions for the semiconductor substrate are set using the algorithm. When processing semiconductor substrates in batches, the locations are determined and corrected based on the classification based on characteristic values and the tendency of the characteristic values based on the position known in advance. , for each semiconductor substrate. These series of correction processes are performed by computer processing. (Embodiments) Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3. In other words, a series of processing steps that utilize manufacturing equipment and computers are based on the premise of appropriate inventory. FIG. 1 shows an outline of the present invention, and a measuring instrument/manufacturing device 3 is connected to a host computer 1 via an intermediate computer 2. The measuring instrument/manufacturing equipment 3 is attached with a semiconductor board number reading device w4. The arrows in the figure represent the flow of semiconductor substrates to be processed, that is, the order of processing.The host computer 1 and the intermediate computer 2 are connected via LAN, and the intermediate computer 2 and the measuring instrument/manufacturing equipment fi3 communicate on a one-to-one basis. Mainly SECS (Semiconductor)
erEquipmentCommunication
Standard) I, connected by ■, (
SECS-I corresponds to this) Also, the semiconductor board number reading device 1114 is 8I! Although it is connected to the measuring instrument/manufacturing equipment I13 or the intermediate computer 2, in FIG. ! 3 is shown connected. As an example of the processing procedure, we will explain it using a polycrystalline silicon resistor type process. First of all. After depositing polycrystalline silicon onto a semiconductor substrate using the manufacturing equipment 113a, the measuring device 3
The film thickness is measured by b, the number of the semiconductor substrate to be processed is read by the reader 4, and the measurement result is sent to the intermediate computer 2.
Transfer and save it to the host computer via . An example of the format is shown in FIG. 2, where the semiconductor substrate is referred to as a wafer. As is clear from this example, the product name, lot Nα, process name, lot representative value, wafer &1, and characteristic values are displayed, and of course the characteristic values are measured and displayed for each semiconductor substrate number to be processed. However, depending on the tendency of the characteristic values after processing in the manufacturing equipment 113, that is, the tendency of variation, it is not always necessary to measure all the semiconductor substrates.
次にイオン注入装[3cにより所定の導電型の不純物例
えばAsを多結晶珪素層の所定の場所にイオン注入後、
測定器3dによりρSを測定する.この工程でも測定器
3bによる処理と同様な手順により行うが、パラツキが
少ない場合には、全半導体基板でなくロットから数枚例
えば3枚測定してその平均値をロフト代表値としてホス
トコンピュータlに保存する。Next, after ion implantation of an impurity of a predetermined conductivity type, for example, As, into a predetermined location of the polycrystalline silicon layer using an ion implantation device [3c],
Measure ρS using measuring device 3d. This step is also carried out using the same procedure as the processing using the measuring device 3b, but if there is little variation, measure several wafers, for example three, from the lot rather than all the semiconductor wafers, and use the average value as the loft representative value and enter it into the host computer l. save.
次にリソグラフイ(Ij thography)装fi
3eによりドープド(Doped)多結晶珪素層をパタ
ーニングするが、被処理半導体基板毎の露光条件を変更
して抵抗値を制御する。その手順は、半導体基板番号を
読取装w4で読取後、ホストコンピュータ1にこの番号
を転送する.このホストコンピュータ1では、式R =
p s−L/ T−vを利用する.ここでR:狙った
抵抗値、ρs:3dでの測定値、L:設計値、T:3b
で測定した半導体基板磁に対応した値、W:パターン幅
である.
この式から狙った値Wを決定するが、Wを得るための露
光量は、第3図に示す方法による。第3図は、縦軸にパ
ターン寸法が、横軸に露光量を採り,両者の関係を示す
直線Aが示されている.この直線Aは経験則から決定さ
れる係数と理論値を考慮して決められたもので、所望の
パターン幅W値から露光量が直線Aにより決定される。Next, lithography equipment
3e, the doped polycrystalline silicon layer is patterned, and the resistance value is controlled by changing the exposure conditions for each semiconductor substrate to be processed. The procedure is to read the semiconductor board number with the reading device w4 and then transfer this number to the host computer 1. In this host computer 1, the formula R =
Use ps-L/T-v. Here, R: target resistance value, ρs: measured value at 3d, L: design value, T: 3b
A value corresponding to the semiconductor substrate magnetic field measured in W: pattern width. A target value W is determined from this formula, and the exposure amount for obtaining W is determined by the method shown in FIG. In FIG. 3, the vertical axis represents the pattern dimension, the horizontal axis represents the exposure amount, and a straight line A indicating the relationship between the two is shown. This straight line A is determined by considering coefficients determined from empirical rules and theoretical values, and the exposure amount is determined by the straight line A from the desired pattern width W value.
また、能動素子及び受動素子の一方か双方更には抵抗な
どを備えた半導体素子は、益々集積度を向上する傾向に
あるのに伴って、微細加工及び寸法制御に関する要求が
厳しくなるのでボジ型レジストが使用され、本発明でも
ポジ型レジストを使用するものである.
このようにして形成された抵抗値bを従来例aと比較し
た図を第4図に示した。この図は,n個のシリコン半導
体基板に形威した多結晶珪素からなる抵抗値測定結果を
棒グラフにより示しているが,明らかに本発明による抵
抗値bの方が従来例aより偏りが少ない上に得られる抵
抗値も大きい.aの図では、紙面の左から5番目の棒グ
ラフが狙った抵抗値のセンター値であり,bでは,紙面
の左から3番目の棒グラフが狙った抵抗値のセンター値
である.この図面からも本発明の有効性が証明されたと
考えることができる.
〔発明の効果〕
従来技術では、ロフトの代表値としてその特性値を補正
して処理するために、ロフト間のバラッキがあまり大き
くならず、また,センター値としては狙った値に近ずく
が、ロフト内のバラツキ即ち被処理半導体基板間のそれ
は補正されていない.このために関連する処理のバラツ
キは,最終処理のバラツキを増幅する結果となるのに対
して、本発明システムでは、被処理半導体基板毎に補正
するために処理工程によるバラッキを増加させず、その
結果例えば抵抗値のバラッキが従来の172以下に減少
した.
このように正確な抵抗値が得られることにより半導体集
積回路に最近求められている苛酷な要求を満足する結果
となり、その特性向上に資するところが大きい.In addition, as semiconductor devices equipped with one or both of active elements and passive elements, as well as resistors, etc., are becoming increasingly integrated, requirements regarding microfabrication and dimensional control are becoming stricter. is used, and the present invention also uses a positive resist. FIG. 4 shows a comparison of the resistance value b formed in this manner with that of the conventional example a. This figure shows the resistance value measurement result of polycrystalline silicon formed on n silicon semiconductor substrates as a bar graph, and it is clear that the resistance value b according to the present invention is less biased than the conventional example a. The resistance value obtained is also large. In figure a, the fifth bar from the left on the paper is the center value of the targeted resistance value, and in b, the third bar from the left on the paper is the center value of the targeted resistance value. This drawing can also be considered to prove the effectiveness of the present invention. [Effect of the invention] In the conventional technology, since the characteristic value is corrected and processed as a representative value of the loft, the variation between lofts does not become so large, and the center value approaches the target value, Variations within the loft, that is, variations between semiconductor substrates to be processed, are not corrected. For this reason, related processing variations result in amplification of final processing variations, whereas in the system of the present invention, variations due to processing steps are not increased and are corrected for each semiconductor substrate to be processed. As a result, for example, the variation in resistance value has been reduced to 172 or less than the conventional value. Obtaining accurate resistance values in this way satisfies the severe requirements recently placed on semiconductor integrated circuits, and greatly contributes to improving their characteristics.
第1図は,本発明のシステムの概略を示す図、第2図は
、本発明に利用するホストコンピュータのデータファイ
ルフォーマット例、第3図は、処理条件決定方法を示す
図,第4図は、本発明の効果を従来例と比較して示す図
である。
1:ホストコンピュータ、
2a〜2e;中間コンピュータ、
38〜3e:測定器及び製造装置、
48〜4e:半導体基板読取装置.FIG. 1 is a diagram showing an outline of the system of the present invention, FIG. 2 is an example of the data file format of a host computer used in the present invention, FIG. 3 is a diagram showing a method for determining processing conditions, and FIG. , is a diagram showing the effects of the present invention in comparison with a conventional example. 1: Host computer, 2a to 2e; Intermediate computer, 38 to 3e: Measuring instrument and manufacturing device, 48 to 4e: Semiconductor substrate reading device.
Claims (1)
を半導体基板に追込む製造用装置をオンライン接続した
コンピュータを備えた半導体素子の生産システムにおい
て、各測定器及び製造装置に半導体基板枝葉番号を読取
る装置を設け、半導体基板単位の特性資料を記録したコ
ンピュータで製造装置における加工条件を決定してから
加工することを特徴とする半導体素子の生産システム。In a semiconductor device production system equipped with a computer that is online connected to a measuring device that measures the characteristics of a semiconductor device and a manufacturing device that drives the semiconductor device onto a semiconductor substrate, each measuring device and manufacturing device is assigned a semiconductor substrate branch number. 1. A production system for semiconductor devices, which is equipped with a reading device and is characterized in that the processing conditions for the manufacturing device are determined using a computer that records characteristic data of each semiconductor substrate before processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31097689A JPH03171753A (en) | 1989-11-30 | 1989-11-30 | Production system of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31097689A JPH03171753A (en) | 1989-11-30 | 1989-11-30 | Production system of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03171753A true JPH03171753A (en) | 1991-07-25 |
Family
ID=18011660
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31097689A Pending JPH03171753A (en) | 1989-11-30 | 1989-11-30 | Production system of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03171753A (en) |
-
1989
- 1989-11-30 JP JP31097689A patent/JPH03171753A/en active Pending
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