JPH03169082A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To micronize it and also to enable high-speed operation by making the control gate electrode of a memory transistor and the selective gate electrode of a selective transistor common. CONSTITUTION:This has a memory transistor 6 and a selective transistors 3 being arranged in matrix shape on the semiconductor substrate of first conductivity type. And a tunnel region 8 and a lead transistor region 10 are made, shearing the polycrystalline semiconductor upper layer of a floating gate electrode 14 and a selective gate electrode 4 formed through an interlayer insulating film and separating the lower layer electrically with an element isolating field oxide film 18. That is, since a memory transistor 6 and a selective transistor 3 are made continuously, separation allowance and a connection impurity diffusion layer can be omitted. Hereby, micronization becomes possible, and they can be integrated highly, and at the same time the increase of the channel resistance by the connection impurity diffusion layer can be suppressed, and an element capable of high speed operation can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read-only nonvolatile semiconductor memory device (EEFROM) that can be electrically written and rewritten.

(Prior art) Figure 5(a). (b) and (C) are the generally known conventional EEFROM cell FLOTEX (Floa
FIG. 2 is a plan view, a cross-sectional view, and an equivalent circuit diagram showing a TigGate Tunnel Oxide (TigGate Tunnel Oxide) structure. In these figures, 1 and 2 are p-type silicon (Si) substrates 2.
The drain and source regions of a double diffusion structure are formed on the surface of the transistor 8 with the selection transistor 3 and the memory transistor 6 sandwiched therebetween. The selection transistor 3 has a connection impurity diffusion layer 5 as a source formed on the surface of the St substrate 28 separated from the drain region 1, and a selection gate silicon oxide (SiO2) film 13 with a thickness of about 400 nm on the Si substrate 28 between them. It consists of a select gate polycrystalline silicon (p-S i ) film (hereinafter simply referred to as a select gate electrode) 4 with a gate length of about 2 μm formed through a gate electrode. The memory transistor 6 includes a tunnel impurity diffusion layer 9 as a drain formed on the surface of the Si substrate 28 separated from the source region 2, and a thin tunnel oxide silicon film formed on a part of the surface of the tunnel impurity diffusion layer 9. Floating gate p-Si layer (hereinafter simply referred to as floating gate electrode) 1 formed on St substrate 28 via memory gate silicon oxide film 17 including film 16
4. Consists of a control gate p-St layer (hereinafter simply referred to as a control gate electrode) 7 formed thereon via a glabellar insulator @15. Reference numeral 8 denotes a tunnel region of the memory transistor 6 in which electrons are injected and emitted through the tunneling silicon oxide film 16 by a tunnel effect (Fowler-Nordheim tunneling phenomenon); 10, electrons are injected into the floating gate electrode 14 in the tunnel region 8; The read transistor regions 11 and 12 of the memory transistor 6, which turn on and off the read current according to the level of the threshold voltage seen from the control gate electrode 7, which changes depending on the presence or absence of electrons, are connected to the bit line 23 and the source line 24. 3a is another selection transistor, which is connected to the word line 25.
A signal from the control gate line 22 is supplied to the control gate electrode 7 of the memory transistor 6 by the selection gate 4a connected to the memory transistor 6.

The conventional EEFROM cell stores data by utilizing the fact that the threshold voltage seen from the control gate electrode 7 of the memory transistor 6 differs depending on whether or not electrons are accumulated in the floating gate electrode 14. The memory transistor 6 performs writing by applying a high voltage of 18 to 20 V between the drain of the tunnel region 8 and the control gate electrode 7 and injecting high-energy electrons generated near the drain into the floating gate electrode 14. ．． Further, the polarity of the high voltage applied between the drain and the control gate electrode 7 is reversed, and electrons from the floating gate electrode 14 are emitted for erasing. moreover,
When the control gate electrode 7 of the memory transistor 6 is grounded by the selection gate electrodes 4, 4a of the selection transistors 3, 3a connected to the decoder output of the word line 25 selection,
When electrons are injected into the floating gate electrode 14, the threshold is in a high state (enhancement state), and the read transistor region 10 is turned off and no current flows; When it is in the on state), it turns on and current flows. The state of the memory transistor 6, that is, the written information is determined by detecting the presence or absence of current, and data is read from the bit line 23. writing. The potentials applied to each element during erasing and reading are shown in Table 1 below.

Table 1 [Problems to be Solved by the Invention] The conventional EEFROM cell as described above has the following problems.

(1) Memory transistor 6 and selection transistor 3
Since the transistors are formed separately, a separation margin is required to separate each element region, which hinders miniaturization. 5, which increases the on-resistance of the memory transistor 6 during reading.

(2) Since the potential applied to the drain of the memory transistor 6 is lower than the potential applied to the bit line 23 by the threshold voltage of the selection transistor 3, the write efficiency of the memory transistor 6 decreases accordingly, causing depletion (always on). Current driving power decreases.

(3) Select transistor 3 is used for writing. Since it is shared during erasing and reading, a special structure such as a gate length and a double-diffused drain is required, and the structure and arrangement cannot be optimized for reading due to the arrangement of the tunnel impurity diffusion layer 9, making it difficult to perform high-speed reading operations. It was preventing the development of

This invention was made to solve the above-mentioned problems, and it provides a readout device that can be miniaturized, easily highly integrated, write and read at high speed, and that can be written and rewritten electrically. The purpose is to obtain a dedicated nonvolatile semiconductor memory device.

[Means to solve the problem]

Nonvolatile semiconductor memory device (EEFROM) according to the present invention
) is a semiconductor memory device having a memory transistor and a selection transistor arranged in a matrix on a semiconductor substrate of a first conductivity type. Sharing the polycrystalline semiconductor upper layer of the electrode,
The lower layer is electrically isolated by an element isolation field oxide film to form a tunnel region and a read transistor region.

Further, a tunnel impurity diffusion layer formed on the surface of the first conductivity type semiconductor substrate below the tunnel region of the memory transistor, and a polycrystalline semiconductor layer below the selection gate electrode of the selection transistor connected in series with the read transistor region. a word line impurity diffusion layer formed on the substrate surface on the tunnel region side thereof and a second conductivity type connecting impurity diffusion layer formed on the substrate surface connecting the tunnel impurity diffusion layer and the word line impurity diffusion layer; , a tunnel electrode line that is directly electrically connected parallel to the bit line direction.

[Function] In the EEPROM configured as above, since the control gate electrode of the memory transistor and the selection gate electrode of the selection transistor are common, connection impurity diffusion is performed to electrically connect the channel region of the selection transistor and the channel region of the memory transistor. This eliminates the need for layers, allowing for miniaturization and high-speed operation. Since the read transistor region of the memory transistor is separated from the tunnel region, it is possible to form a self-aligned read transistor region, and there is no need for a photolithography overlay margin.

In addition, since the tunnel electrode line is provided separately from the read transistor area so that it does not go through the selection transistor, it is possible to apply the potential of the write/erase bit line directly to the tunnel area via the tunnel electrode line. There is no reduction in the threshold voltage of the transistor. Furthermore, since the selection transistor can be made read-only, it is possible to optimize the gate length and drain structure of the selection transistor for reading. Furthermore, since the tunnel impurity diffusion layer is separated from the read transistor region, the selection transistor and memory transistor can be separated. It is possible to lower the channel resistance between the drain and source to which the potential of the read bit line of the series transistor cell consisting of the read transistor region is applied, and to increase the mutual conductance.
Read operations become faster.

〔Example〕

1(a) to Cf> show an embodiment of the present invention.
FIG. 2 is a plan view of a PROM cell, an equivalent circuit diagram thereof, and a sectional view taken along lines Ic, Id, Ie, and If. Figure 1 (C). (d). (e) and (f) are Ic in Figure 1 (a)
-Ic line, Id-Id line, Ie-Ie line and If-
It is a sectional view taken along the If line. In these figures, 1
2 is a lead transistor region 1 of a selection transistor 3 and a memory transistor 6 on the surface of a p-type Sl substrate 28.
Drain region and source region formed on both sides of 0, 3
is a selection transistor, which is sandwiched between its drain region 1 and the lead transistor region 10 of the memory transistor 6;
A gate length of 1.2 is formed on the St substrate 28 between them via a selection gate silicon oxide film 13 with a film thickness of about 400.
It consists of a selection gate electrode 4 of about .mu.m.

The memory transistor 6 is sandwiched between the source region 2 and the selection transistor 3, and has a film thickness of 3 on the St substrate 28 between them.
A floating gate electrode 14 is formed through a memory gate silicon oxide film 17 of approximately 0.00 mm, and a glabellar insulating film 15 of approximately 250 mm (converted to Si 0 2 film thickness) is formed thereon. Read transistor region 1 consisting of a selection gate electrode 4 and a common control gate electrode 7
0 and the lead transistor region 10 of which is adjacent to the device isolation field silicon oxide film 18 through the
An n-type tunnel impurity diffusion layer 9 with a concentration of about 1×10”c12 is formed on the surface of the substrate 28, and a film with a thickness of 100 mm is formed thereon.
The tunnel region 8 is composed of the shared floating gate electrode 14 formed through a human-sized tunnel silicon oxide film 16, and a control gate electrode M17 formed over the shared floating gate electrode 14 through a glabella insulating film 15 thereon.

Reference numeral 19 denotes a tunnel electrode line, which connects S at the bottom of the tunnel region 8.
A tunnel impurity diffusion layer 9 with a concentration of about 1×1°019 cm −2 is formed on the surface of the t-substrate 28 extending parallel to the bit line 23 direction, and a selection gate electrode 4 of the selection transistor 3
The word line 2 activates all memory cells connected to the word line 2 and writes and reads data between each bit line 23.
At the bottom of 5, a concentration of 1 x 10"c is formed via a word line insulating film 20 of about 400 in terms of Si02 film thickness.
It is connected to the word line impurity diffusion layer 21 of about a-2, and is directly electrically connected in the direction of the bit line 23. bit line 2
3 is connected to the drain t8i11 of the selection transistor 3, and when the word line 25 is selected, data can be written to and read from the memory cell. source line 2
4 is connected to the source electrode 12 of the memory transistor 6. The word line 25 is composed of the selection gate electrode 4 of the selection transistor 3 and the control gate electrode 7 of the memory transistor 6. 26 and 27 are the Si
These are a smooth coat insulating base silicon oxide film for the base formed on the memory cells of the matrix array configured on the substrate 28 and a smooth coat insulating film for surface passivation.

As shown in FIGS. 1(e) and (f), the glabella insulating film 1
The upper polycrystalline semiconductor layer of the floating gate electrode 14 and the selection gate electrode 4 formed through the gate electrode 5 is shared, and the lower layer side is electrically isolated by an element isolation field oxide film 18, and the tunnel region 8 and the read transistor region 10 This is clearly expressed.

FIG. 2 shows an on-chip EEP showing one embodiment of this invention.
It is a block diagram of ROM. In the figure, 50 is a unit circuit that stores 1-bit information. A memory cell matrix array, 51 and 51, is constructed by arranging memory cells in a matrix and connecting each cell to the word line 25 in FIG. 1 for selecting the cell and the bit line 23 for transmitting stored information. Reference numeral 52 denotes a row address buffer and a column address buffer, in which row and column address input signals 59 and 60 of TTL level are "H". The "L" level is detected, the signal level is amplified and converted into an internal MOS level signal, and the row/column decoders 53 and 54 are further driven via a driver. The row decoder 53 and column decoder 54 select the word line 25 and bit line 23 specified by the row/column address, so they drive the word line 25 via a word driver and control the multiplexer. 55 is this line. The column selector and sense amplifier 56 reads the data stored in the memory cell designated by the column decoders 53 and 54 to the sense amplifier 56, and detects the minute signal voltage of the data stored in the memory cell via the bit line 23. Amplify it as a voltage level. 57 is a data output buffer, and a chip select buffer 58
A chip select input signal 61 that selects a data input/output terminal is received via the chip select input signal 61 to select a data input/output signal 62, and a driver drives a large load capacitance. Reference numeral 58 denotes a chip select buffer, which receives the chip select input signal 61 and passes it through a driver to the data output buffer 57, other row address buffers, and column address buffer 51.
．． 52, line. Column decoder 53, 54, sense amplifier 56
control to select data input/output terminals and operation mode.

Like the conventional example, the EEFROM of the above embodiment uses the fact that the threshold voltage seen from the control gate electrode 7 of the memory transistor 6 differs depending on whether or not electrons are accumulated in the floating gate electrode 14 to store data. Remember. The tunnel region 8 of the memory transistor 6 exchanges electrons between the floating gate electrode 14 and the tunnel impurity diffusion layer 9 through the thin tunnel oxide silicon 1!18 through which F (Fowler)-N (Nordheim) current flows. conduct. In this case, the electric field E across the tunnel silicon oxide I1i16. X is each applied potential ■ of the word line 23 and the tunnel electrode line 19; and VT, and tunnel oxide silicon film 1
It is determined from the thickness ToX of 6 by the following formula.

VOx=A-vG-B-vT Here, A and B represent the capacitive coupling ratio. Therefore, the high electric field conditions that allow current to flow through the tunnel silicon oxide film 16 are (approximately 13 to 14 MV/cm), electrons are injected and released into the floating gate electrode 14 depending on the positive and negative voltage of EOX, thereby performing writing and erasing.

Furthermore, the read transistor region 10 of the memory transistor 6 has a two-layer polycrystalline structure made of the control gate electrode 7 and the floating gate electrode 14, which controls the potential level determined by the amount of charge in the floating gate electrode 14 injected and discharged in the tunnel region 8. Reading is performed by detecting the threshold voltage using a silicon type read transistor. If electrons are injected into the floating gate electrode 14, the read transistor becomes an enhancement (always off) type transistor, and if electrons are released excessively from the equilibrium state, it becomes a depletion (always on) type transistor. Next, the selection transistor 3 is used only during reading, and the drain electrode 11 and source electrode 12
When selecting or non-selecting the read transistor region 1o sandwiched between the read transistor region 1o, the selection gate electrode 4 is given a potential of, for example, 5V or Ov to turn the selection transistor 3 on and off, and the potential of the bit line 23 is changed to the read transistor region 1o. Area 1
You may or may not tell 0. The potentials applied to each element during writing/erasing and reading are shown in Table 2 below.

The above describes the operation of a 1-bit memory cell.

Next, the operation of the memory cell matrix array 50 in which a plurality of memory cells are arranged will be explained. FIGS. 3 and 4 are equivalent circuit diagrams of an EEFROM cell matrix array showing one embodiment of the present invention, and diagrams showing potentials applied to each element in the operation mode. In Figure 3, W
,, W2 and W3 are word lines 25, B I * B
2 and B3 are bit lines 23, Sl1+ S +2+
. . . SSS is the source line 24, T, , T2 and T, are the tunnel electrode lines 19, s, s2 and S3 are the selection transistors 3, M , , M , 2, . . .
・・・． M3, indicates the memory transistor 6. Furthermore, in FIG. 4, E indicates erasure (enhancement writing) in which the memory transistors M l in M 12 and MtS connected to the word line W1 are turned off (“1”).
In the write mode (depression write) in which only the memory transistor Mn is turned on (“0”), P is the memory transistor Mn connected to the word line W. ．． ,M. In the read mode for reading 2 and M+3, H represents a high level potential of 18 to 20V, L represents a low level potential of Ov, and M represents, for example, an IOVo medium level potential.

In the case of E in the above erase mode, the memory transistor M1,
, M, 2 and M13 tunnel oxide silicon WA16
A high electric field (for example, 13 MV/c+a) is applied to the floating gate electrode 14, and electrons are injected from the tunnel impurity diffusion layer 9 into the floating gate electrode 14. Other memory transistors M21, M22
．． "・"・, M33 tunnel oxide silicon film 16
Since no electric field is generated in , there is no injection or emission of electrons.

Table 2 Next, in the case of P in the write mode, the memory transistor M
A high electric field (for example, −1 5 M V /cm) is applied to the l+ tunnel oxide silicon film 16, and electrons are emitted from the floating gate electrode 14 to the tunnel impurity diffusion layer 9. Other memory transistor M2l? A low electric field (for example, 5.5 MV/
cm) is applied, so there is no injection or emission of electrons. Furthermore, since no electric field is generated in the tunnel oxide silicon film 16 of the memory transistors M12 and M1, the memory transistors M2■, M23, M3■ and M
Since a low electric field (for example, -7.5 MV/cm) is applied to the tunnel oxide silicon film 16 of 33, no electrons are injected or emitted.

Furthermore, in the case of R in the read mode, the channel of the memory transistor in the enhancement state among the memory transistors M 11, M , 2 and M13 is turned off, current does not flow from the drain electrode 11 to the source electrode 12, and the bit line A "1" state is read by a sense amplifier 56 connected to 23. On the other hand, among the memory transistors Mll, M, ■, and M13, the memory transistor in the depletion state has its channel turned on, and current flows from the drain electrode 11 to the source electrode 12, and the sense transistor connected to the bit line 23 “O” at amplifier 56
The state is read. At this time of reading, the unselected word line 2
5 becomes OV, and even if the unselected memory transistor 6 is in the enhancement state or depletion state, no current flows from the bit line 23 through the unselected memory cell, preventing reading from the selected memory transistor. Never.

In the above embodiment, the case where only the memory transistor 6 connected to the word line 25 selected in E in the erase mode is erased is shown. 19 may be brought to the "L" level to erase all memory transistors 6 at once. Also,
“Erase mode” in which depletion writing is performed on specific multiple memory transistors 6 constituting one byte or more at once
Alternatively, only a specific memory transistor 6 may be operated in a "write mode" in which enhancement writing is performed.

〔Effect of the invention〕

Since this invention is configured as explained above,
It has the effects described below.

(1) Since the memory transistor and the selection transistor are configured in series, the isolation margin and connection impurity diffusion layer can be omitted, allowing for miniaturization and easy high integration, while at the same time increasing the channel resistance due to the connection impurity diffusion layer. A device that can operate at high speed while suppressing the noise can be obtained.

(2) By directly electrically connecting multiple tunnel impurity diffusion layers extending parallel to the bit line direction with tunnel electrode lines, there is no drop in the threshold voltage of the selection transistor during writing. High write efficiency is possible.

(3) By making the selection transistor read-only and optimizing its structure and arrangement, it is possible to lower the channel resistance between the drain and source of the series transistor cell consisting of the selection transistor and the lead transistor region of the memory transistor, and increase the mutual conductance. Therefore, high-speed reading is easily possible.

[Brief explanation of the drawing]

FIG. 1 is a plan view, an equivalent circuit diagram, and a sectional view of an EEFROM cell showing an embodiment of the present invention, FIG. 2 is a block diagram of an EEFROM cell showing an embodiment of the present invention, and FIGS. 3 and 4 are An equivalent circuit diagram of an EEFROM cell matrix array showing an embodiment of the present invention and a diagram showing the potentials applied to each element during the operation mode, and FIG. 5 is a plan view, cross-sectional view, and equivalent circuit of an EEPROM cell showing a conventional example. It is a diagram. In the figure, 1 is a drain region, 2 is a source region, 3 is a selection transistor, 4 is a selection gate electrode, 5 is a connection impurity diffusion layer, 6 is a memory transistor, 7 is a control gate electrode, 8 is a tunnel region, and 9 is a tunnel. Impurity diffusion layer, 1
0 is a lead transistor region, 14 is a floating gate electrode,
15 is an interlayer insulating film, 18 is an element isolation field silicon oxide film, 19 is a tunnel electrode line, 21 is a word line impurity diffusion layer, 22 is a control gate line, 23 is a bit line, 24 is a source line, 25 is a word line, 28 is an St substrate, and 50 is a memory cell matrix array. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a semiconductor memory device equipped with a memory cell having a memory transistor and a selection transistor arranged in a matrix on a semiconductor substrate, a polycrystalline semiconductor upper layer of a floating gate electrode and a selection gate electrode formed through an interlayer insulating film is used. The lower layer is electrically separated by an element isolation field oxide film to form a tunnel region and a lead transistor region, and the selection gate electrode of the selection transistor and the control gate electrode of the memory transistor are directly connected and made common. A read-only nonvolatile semiconductor memory device that is electrically writable and rewritable. (2) A tunnel impurity diffusion layer formed on the surface of the first conductivity type semiconductor substrate below the tunnel region of the memory transistor, and a polycrystalline selection gate electrode in the selection transistor formed in series with the lead transistor region of the memory transistor. A word line impurity diffusion layer formed on the substrate surface on the tunnel region side of the lower part of the semiconductor layer, and a second conductivity type connecting impurity diffusion layer formed on the substrate surface connecting the tunnel impurity diffusion layer and the word line impurity diffusion layer. 2. The semiconductor memory device according to claim 1, further comprising a tunnel electrode line directly electrically connected in parallel to the bit line direction.