JPH03166623A - Divider circuit - Google Patents

Abstract

PURPOSE:To form the divider circuit of high accuracy and a high speed by dividing a dividend into two high order and low order groups, storing the respective division results as a high order division table and a low order division table, and adding the high order division result and the low order division result. CONSTITUTION:The circuit is provided with a high order division table 5 in which a result of division of a prescribed upper bit is stored, a high order division table reference circuit 6 for referring to the high order division table 5 corresponding to a value of the upper bit of a dividend and a divisor, and a low order division table 7 in which a result of division of a prescribed lower bit is stored. Also, this circuit is provided with a low order division table reference circuit 8 for referring to the low order division table 7 corresponding to a value of the lower bit of the dividend and the divisor, and an adder circuit for adding a result of reference of the high order division table reference circuit 6 and a result of reference of the low order division table reference circuit 8. In such a way, the dividing circuit of a high speed and high accuracy can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a division circuit that performs integer division in a device that performs digital arithmetic operations.

BACKGROUND OF THE INVENTION Conventionally, there are three methods for performing division in digital operations. That is, the first method is to use an MPU (microprocessor unit) to perform calculations within a program.
The second method is to perform calculations using an LSI for floating point calculations, and the third method is to create a table of division results in advance and perform calculations by referring to the table. The first method is MP
The calculation speed required by the peripheral circuit and program to control U is about 1 microsecond, and the second method requires a peripheral circuit using an LSI for floating point calculations, conversion from integer to floating point, and conversion from floating point to floating point. The calculation speed required to control conversion to integers is about 10 microns. Considering the ease of use and calculation speed of the first and second methods, it is difficult to implement the division operation as part of the hardware. Therefore, the third method is generally used to implement the division operation as part of the hardware. In the third method, all possible combinations of divisor and dividend are calculated in advance and stored in a storage device as a division table.
This is a method of calculating a calculation result by referring to a division table for given data.

Problems to be Solved by the Invention This third method is very effective in terms of ease of configuration and high-speed processing. However, in recent digital processing, calculation accuracy is an important consideration, and if the calculation accuracy is increased, the third method becomes difficult to implement due to the problem of the storage capacity of the storage device.

For example, when performing division on the outputs of two 12-bit A/D converters, since both the divisor and dividend are 12 bits, it is necessary to create a table with 224 elements, that is, 16777216 elements, and the result of the operation is divided into 12 bits. This requires a 32 megabyte storage device.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to reduce the capacity of a storage device and provide a high-speed, high-precision division circuit.

Means for Solving the Problems In order to achieve the above object, the present invention provides an upper division table that stores division results of predetermined upper pits, and an upper division table that stores the division results of predetermined upper pits, and an upper division table reference circuit that references the division table of;
a lower division table storing a predetermined lower bit division result; a lower division table reference circuit that references the lower division table corresponding to the lower bit value of the dividend and the divisor; and an upper division table. An adder circuit is provided for adding the reference result of the division table reference circuit and the reference result of the lower division table reference circuit.

In the present invention, the set of dividends is A1, the significant digits of set A of dividends are NA bits, the set of divisors is B1, the significant digits of set B of divisors are NB bits, the set of quotients is C1, the significant digits of set C of quotients are N bits.
c. When division of each element of A and B is performed using a table reference method, 2 to the power of (NA+NB) tables are required. Next, set N2 = NA / 2 (round up calculation), and of the set A of dividends, the subset where the upper N2 bits are not zero and the other pits are zero is AU1, the subset where the upper N2 bits are zero is AL, The element of A is a,
If the AuO element is aU and the element of A4 is al, there is ass aL that can be expressed as a"aU+aL. That is, a
When , is divided under B, aaU aL − = − + − bb b .

Here, the results of dividing all elements of Au by all elements of B are stored in advance in an upper division table,
By storing the result of division of all elements of B by all elements of Ax, in a lower division table,
The first and second terms on the right side of the above equation can be determined by referring to a table.

The calculation can be realized by adding the division results obtained in this way. By performing division in this configuration, the number of elements in the division table is sufficient to be 2 to the power of (N2+NB+1), and the number of table elements can be reduced compared to the conventional table reference method.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

The figure is a diagram showing an embodiment of the division circuit of the present invention. In the figure, 1 is an input signal line for the dividend, 2 is an input signal line for the divisor, 3 is an input signal line above the input signal line for the dividend, 4 is an input signal line below the input signal line for the dividend, 5 6 is an upper division table, 7 is a lower division table, 8 is a lower division table reference circuit, 9 is an addition circuit, and 10 is an output signal line. In this embodiment, the input signal line 1 of the dividend is 12
There are 12 input signal lines 1 for the divisor, and 12 input signal lines for the upper input signal line 3.
There are 6 lines, 6 lines for lower input signal lines 3, and 12 lines for output signal lines 10. This indicates that the effective digits of the dividend are 12 bits, the upper and lower significant digits of the dividend are 6 pits each, the divisor is 12 bits, and the quotient is 12 bits.

The operation of this embodiment will be explained below. The upper division table 5 stores the values of division results obtained by combining all the values of the upper 6 bits of the dividend and all the values of the divisor. Table 1 shows a part of the upper division table 5.

Further, the lower division table 7 stores the values of division results obtained by combining all the values of the lower 6 bits of the dividend and all the values of the divisor. Table 2 shows a part of the lower division table 7. The dividend is input to the dividend input signal line 1, of which the upper six lines are led to the upper division table reference circuit 6, and the lower six lines are guided to the lower division table reference circuit 8.

Table 1 below shows a part of the upper division table Table 2 shows a part of the lower division table Also, the divisor is input to the divisor input signal line, and the upper division table reference circuit 6 and is led to the lower division table reference circuit 8. Next, the upper division table reference circuit 6 calculates the address using the upper 6 bits of the dividend and the 12 bits of the divisor, and refers to the upper division table 5 to obtain the division result for the upper 6 bits. The result is passed to the adder circuit 9. In the lower division table reference circuit 8,
Address calculation is performed using the lower 6 bits of the dividend and the divisor l2 bits, and by referring to the lower division table 7, the division result for the lower 6 bits is obtained, and the result is passed to the adder circuit 9 at the subsequent stage. The adder circuit 9 adds the division result for the upper 6 bits and the division result for the lower 6 bits to obtain the desired division result.

In this embodiment, the upper division table 5 and the lower division table 7 each require a storage capacity of 2 megabytes. Also, table references are less than 120 nanoseconds,
Addition of the division results for the upper 6 bits and the division results for the lower 6 bits was achieved at a high speed of 20 nanoseconds or less.

In this embodiment, the dividend is divided into two groups, upper and lower, and the results of each division are stored as a division table, and the division is performed by referring to the table. It is possible to realize a configuration in which the division is divided into many parts, each division result is stored as a division table, and the division is performed by referring to the table. In the latter case, a more effective storage capacity reduction effect can be expected.

Effects of the Invention As described above, when dividing an integer, the present invention divides the dividend into two groups, upper and lower, and stores the results of each division as an upper division table and a lower division table. By looking up the table to find the upper division result and lower division result, and then adding the upper division result and lower division result, it is possible to easily realize a high-precision and high-speed division circuit. The effect is great.

[Brief explanation of the drawing]

The figure is a block diagram of a division circuit in one embodiment of the present invention. 1...Dividend input signal, 2...Divisor input signal,
3... Upper input signal of the input signal of the dividend, 4...
Lower input signal of dividend input signal, 5... Upper division table, 6... Upper division table reference circuit, 7
. . . Lower division table, 8. Lower division table reference circuit, 9. Addition circuit, 10. Output signal.

Claims (1)

[Claims] an upper division table that stores division results of predetermined upper bits; an upper division table reference circuit that refers to the upper division table that corresponds to the value of the upper bits of the dividend and the divisor; and a predetermined lower division table. a lower division table that stores bit division results; a lower division table reference circuit that references the lower division table corresponding to the lower bit value of the dividend and the divisor; and the upper division table. A division circuit comprising: an addition circuit that adds the reference result of the reference circuit and the reference result of the lower division table reference circuit.