JPH03165562A - Manufacture of masked rom - Google Patents

Abstract

PURPOSE:To shorten a ROM in manufacturing time by a method wherein a a bit line connected to a drain region through a contact hole bored in the interlaminar insulating film of a MOS transistor is formed, and a silicon film is deposited thereon, which is thermally treated. CONSTITUTION:A field oxide film 2 is formed on a substrate 1, an oxide film 3 is formed through thermal oxidation, a polysilicon layer is deposited, which is patterned for the formation of a gate electrode 4, and ions are implanted using the gate electrode 4 and the field oxide film 2 as a mask to form a source region 5s and a drain region 5d in the substrate 1. An interlaminar insulating film 6 is formed on the whole surface of the substrate 1, the oxide film 3 and the interlaminar insulating film 6 formed on the drain region 5d are removed for providing a contact hole 6a. An Al wiring layer is deposited to serve as a bit line 7, a passivation film 8 is deposited, and then program data is obtained. In succession, a photoresist 9 is applied and then developed, and the film 8 is etched using the photoresist 9 as a mask to make the bit line 7 exposed, an amorphous silicon film 10 is deposited, which thermally treated to form a deposited silicon layer 11. By this setup, processes are reduced in number after data are obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a mask RO using a MOS type semiconductor integrated circuit.
This relates to a method of manufacturing M (Read Only Memory).

[Summary of the invention]

The present invention provides a method for manufacturing a mask ROM in which a MOS type transistor as a memory cell is formed on a semiconductor substrate, in which a silicon layer is selectively formed on a contact portion between the MOS type transistor and the bit line. After forming, heat treatment is performed to increase the resistance of the contact portion, thereby shortening the time (TAT) from obtaining the program information to completing the mask ROM, and improving productivity. It is.

[Conventional technology]

A master slice type mask ROM, in which programming is performed depending on whether or not an element is connected to a bit line in the IC manufacturing process, is normally manufactured according to the following process.

First, a MOS transistor as a memory cell is formed on a silicon substrate, and then an interlayer insulating film is formed on the base, and the process waits until program information is obtained.

Next, a mask for opening a contact hole in the interlayer insulating film is manufactured based on the program information. TAT (turnaround time) is determined by the time required from the fabrication of this mask to the completion of the mask ROM.

The interlayer insulating film is etched using the above mask to selectively form contact holes.

After a wiring layer made of AP or the like is deposited on the entire surface including the inside of the contact hole by sputtering or the like, the wiring layer is patterned using a mask for forming a wiring pattern.

Subsequently, a passivation film is deposited using a vapor phase growth method or the like. Then, etching is performed to open a bonding pad for connection with the outside.

Finally, heat treatment is performed in a hydrogen atmosphere to stabilize the characteristics and complete the mask ROM.

In the conventional manufacturing method as described above, the opening pattern of the contact hole formed in the interlayer insulating film is determined by program information. For this reason, the number of steps from receiving information from the user to completing the mask ROM is large, and in reality, about 40 hours or more is required. Therefore, it is desired to shorten the TAT.

As a countermeasure for this improvement, for example, a technique described in Japanese Patent Laid-Open No. 173359/1984 is known.

According to this technology, wiring between a MOS transistor and a bit line is formed in advance, and then laser irradiation is applied to the contact area between the drain region of the MOS transistor and the bit line in accordance with program information, thereby forming a contact area. Selectively rendered non-conductive. Therefore, the number of steps after information acquisition is reduced, and the time required for completion is also shortened.

[Problems to be Solved by the Invention] However, when a contact portion is made non-conductive by laser irradiation as described above, it is difficult to irradiate a minute contact hole with a laser beam. Also, special equipment is required to scan the laser beam according to the programmed pattern. Therefore, it is impractical to apply it to current production lines, and productivity is also a problem.

Therefore, the present invention has been proposed in view of the conventional situation, and provides a method for manufacturing a mask ROM in which the contact resistance between the bit line and the drain region is selectively increased to shorten the TAT. The purpose is to

[Means to solve the problem]

The mask ROM manufacturing method of the present invention has been proposed to achieve the above-mentioned object.

That is, the present invention provides MOS as a memory cell on a semiconductor substrate.
A bit line made of an aluminum-based wiring layer is formed and connected to the drain region through a contact portion opened in the interlayer insulating film on the drain region of the MOS transistor. The method is characterized in that a silicon film is deposited, and then the contact portion is selectively made to have a high resistance by heat treatment.

(Function) In the present invention, regardless of whether or not there is a connection between the drain region of the MOS type transistor and the bit line, the manufacturing process up to the formation of the bit line wiring made of the aluminum-based wiring layer or the formation of the passivation film is completed in advance. After that, based on the program information, a silicon film is selectively deposited on the bit line on the contact part of the MOS transistor and the focus line, and then heat treatment is performed. As a result, the silicon is diffused into the bit line, and the aluminum When the solid solubility limit in the wiring layer is exceeded, silicon deposits in the contact portion, and the contact portion is selectively made to have a high resistance, making it appear as if it were programmed.

〔Example] Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an example in which a passivation film is selectively removed according to program information in a mask ROM manufactured by the master slice method, an amorphous silicon film is deposited on the exposed bit line, and then heat treatment is performed.

First, the circuit of the mask ROM of this embodiment will be explained.

As shown in FIG. 2, the drain wire of a MOS transistor serving as a memory cell is connected to a bit line 17 via a contact portion 16. A high level voltage is supplied to this focus line 17, and a sense amplifier 13 is connected to its end. On the other hand, the source electrode of the MOSI transistor is connected to the ground line 14. Further, a MOS transistor and a word line 12 are selected as appropriate.

In the memory cell B where the nMOS transistor and the bit line 17 are connected at the contact part 16, the bit line 17 is discharged by the MOS transistor and approaches the ground level, and conversely, the nMOS transistor and the bit line 17 are not connected. In memory cell A, the potential of bit &117 is held at a high level even after word line 12 is selected.

Therefore, the bit line 17 and MO in the contact portion 16
IJ is generated in the memory cell depending on whether the S transistor is conductive or not.
, or "O" information is stored.

Next, a method of manufacturing the mask ROM of this embodiment will be explained.

First, as shown in FIG. 1(a), Loco is placed on the substrate 1.
A thick field oxide film 2 is formed using the S method or the like. Then, after thermally oxidizing the entire surface to form a thin oxide film 3, a polysilicon layer is deposited on the entire surface, and the polysilicon layer is patterned using photolithography and etching technology to form a gate insulating film. A gate electrode 4 is formed through a certain oxide film 3. Subsequently, ion implantation is performed using the gate electrode 8i4 and the field oxide film 2 as a mask.
A source region 5s made of n° type impurities is formed on the surface of the store board l.
and a drain region 5d. In this way, the substrate 1
The nMOS transistor formed thereon is used as a memory cell. Further, adjacent memory cells are separated from each other by field oxide film 2.

Then, an interlayer insulating film 6 is formed on the entire surface by a CVD method or the like. As the interlayer insulating film 6, for example, a PSG film or a BPSG film is used.
II etc. can be used. Next, contact hole 6
Perform etching using a mask to open a.
Oxide film 3 and interlayer insulating film 6 on drain region 5d are partially removed.

A contact hole 6a is formed for each drain region 5d regardless of whether or not the nMOSMOS transistor line 7 is connected. As a result, the exposed train area 5d
The surface thereof serves as a contact interface 6b with the bit line 7.

Next, the contact hole 6a is filled and an aluminum wiring layer containing 1% silicon (hereinafter referred to as
It is expressed as an Al-1%Si wiring layer.

) is deposited by sputtering or the like. This A11%S
The i wiring layer functions as a bit line 7. Passivation 11 is applied over the entire surface to protect the surface of the device.
1B and waits in this state until the program information is manually input.

Once the program information is obtained, the passivation film 8
1: Coat photoresist 9. Based on the program information, the photoresist 9 is nMOS)
Contact interface 6b of memory cell A where transistor and bit line 7 are not connected without opening on the area of memory cell B where transistor and bit line 7 are connected;
It is exposed and developed in a pattern that opens at the top. This photoresist 9 is used as a mask for patterning the passivation film 8. The time from the mask manufacturing process to the completion of the mask ROM is defined as TAT.

Next, using the photoresist 9 as a mask,
Etch passivation 1lI8.

As a result, passivation film 8 remains in the region of memory cell B, and in memory cell A, passivation film 8 on contact interface 6b is removed and bit line 7 is exposed.

As shown in FIG. 1B, after unranging the photoresist 9, a thin layer of amorphous silicon 1i10 is deposited over the entire surface including the exposed bit line 7 by sputtering or the like. The thickness of this amorphous silicon film IO is, for example, about 300 to 500.

Next, according to the usual process, a bonding pad (not shown) for connection with the outside is opened, and then heat treatment is performed.The conditions for this heat treatment may be selected as appropriate. In the atmosphere, the temperature is 450
The temperature should be around °C. Through such heat treatment, the nMOS transistor and the bit line 7 are disconnected from each other in the memory cell A.
Then silicon is diffused into the bit line 7. On the other hand, n
In the memory cell B where the MOS transistor and the bit line 7 are connected, the passivation film 8 is interposed between the amorphous silicon film 10 and the bit line 7, so there is no risk of silicon being diffused into the bit line 7.

Since the bit line 7 is made of Affi-1%Si wiring layer,
When the silicon diffused by the heat treatment exceeds its solid solubility limit, it precipitates at the contact interface 6b, as shown in FIG. 1(c). As a result, the contact interface 6 of memory cell A
Precipitated silicon N11 is formed in the region b, and the contact resistance increases significantly.

On the other hand, the contact resistance at the contact interface 6b of memory cell B is kept low. Therefore, the contact interface 6b is selectively made to have a high resistance, as if programmed.

As described above, in this embodiment, by forming the precipitated silicon layer 11 on the contact interface 6b according to the program information, the resistance of the contact interface 6b can be selectively increased. Further, since the formation of the passivation film can be completed before the information is obtained, the number of steps after the information is obtained is reduced, and the TAT can be shortened. Furthermore, the precipitated silicon N11 is formed by performing the formation process of the amorphous silicon film 10 and the heat treatment process.
It can be easily formed without requiring special equipment or complicated processes. Furthermore, since it can be formed all at once over the entire surface of the wafer, productivity is also excellent.

〔Effect of the invention〕

As described above, in the present invention, by forming the wiring or passivation film in advance and manufacturing the mask ROM to a nearly completed state, it is possible to complete the mask ROM in a short time after obtaining information. can. Furthermore, the present invention makes it possible to selectively increase the contact resistance between a MOS transistor and a bit line using equipment widely used in current production lines without requiring any special manufacturing equipment.

[Brief explanation of the drawing]

FIG. 1(a) to FIG. 1(c) are mask ROMs of the present invention.
FIG. 3 is a schematic cross-sectional view for explaining the manufacturing process order of an example of the manufacturing method. FIG. 3 is a circuit diagram of a mask ROM. 2nd rj! J: Substrate Field oxide film Oxide film 4 Gate electrode 5s Source region 5d Drain region 6 Interlayer insulating film 6a Contact hole 6b Contact interface 717 ... Bit line 8 ... Passivation film 9 ... Photoresist film 1O ... Amorphous silicon film 11 ... Deposited silicon layer 12 ... Word line 13 ... Sense amplifier 14 ... Ground line 16...Contact part

Claims (1)

[Claims] A MOS transistor is formed as a memory cell on a semiconductor substrate, and a bit line made of an aluminum wiring layer is connected to the drain region of the MOS transistor through a contact portion opened in an interlayer insulating film on the drain region of the MOS transistor. A method of manufacturing a mask ROM, comprising selectively depositing a silicon film on the bit line, and then selectively increasing the resistance of the contact portion by heat treatment.