JPH03165189A - Image pickup element drive circuit - Google Patents

Abstract

PURPOSE:To ensure a DC level of a video signal normally obtained from an image pickup element by stopping the charge discharge drive for a period including a clamping timing so as to prevent mis-clamping effectively at discharge of undesired charge. CONSTITUTION:A clamp pulse CLP to specify the timing for clamp processing to a video signal output from a solid-state image pickup element is generated within a generating period of a horizontal blanking pulse HBLK. In order to prevent erroneous clamp of undesired charge in advance based on the clamp pulse CLP, the production output of horizontal transfer pulse H1/H2 for the horizontal blanking pulse HBLK is stopped. As a result, the discharge of undesired charge in the clamp timing is avoided when the horizontal transfer pulse H1/H2 is generated continuously. Thus, the generation of mis-clamping for the discharge period of undesired charge is avoided effectively and the DC level of the video signal is always stably ensured.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention effectively prevents misclamping when unnecessary charges are discharged from an image sensor and ensures a normal DC level of a video signal obtained from the image sensor. The present invention relates to an image sensor driving circuit having a simple and practical configuration.

[Prior Art] Recently, various electronic still cameras have been developed that electronically image a subject using a solid-state imaging device such as a CCD to obtain an electronic still image.

Capturing electronic still images using this type of solid-state image sensor is
For example, as shown in FIG. 5, a solid-state image sensor (for example, a CCD imager) 1 is driven by a timing signal generation circuit 3 including a CCD driver 2, and signal charges read out from the solid-state image sensor 1 are thereby driven. This is done by supplying a video signal indicated by to a video processing circuit 5 via a floating DF fusion amplifier (FDA) 4.

The controller 6, which is mainly composed of a microprocessor (MPU), controls the operation of the timing generation circuit 3, and controls the electronic imaging of the subject by the solid-state image sensor 1 and the signal charge obtained by this imaging. This is to control readout from the solid-state image sensor 1.

That is, the solid-state image sensor 1 includes a plurality of charge conversion sections 1a provided in a matrix, and these photoelectric conversion sections 1a.
First charge transfer registers (vertical shift registers) are provided along the column direction of the group Ib and transfer the charges transferred in parallel from each of the photoelectric conversion units 1a in the vertical direction (vertical direction) in the figure. , are provided at the output ends of the first charge transfer registers 1b group in the left-right direction (horizontal direction) in the figure, and receive signal charges that are serially transferred and input in parallel from the first charge transfer registers tb group. It is provided with a second charge transfer register (horizontal shift register) lc that performs serial transfer and reads out and outputs from its output gate.

Further, a transfer gate tt is formed in a region between the photoelectric conversion section 1a and the vertical shift register tb for controlling the transfer of photocharges in the photoelectric conversion section 1a to the vertical shift register Ib. This transfer gate 11
The accumulated charge in the photoelectric conversion section 1a is transferred to the vertical shift register 1b only during a time period in which a high-level signal is applied to the photoelectric conversion section 1a.

Note that in FIG. 5, the individual signal lines for the transfer gate 1t are omitted. Also, vertical transfer electrode 1d
is the vertical transfer pulse V1. ~v4 to vertically transfer and drive charges in the first charge transfer register lb group, and the horizontal transfer electrode 1e receives horizontal transfer pulses H1 and H2 to drive the charge in the second charge transfer register 1c.
This is to transfer and drive charges in the horizontal direction.

The timing signal generation circuit 3 generates the vertical transfer pulses V1. ~v4 and horizontal transfer pulses H1 and H2 are generated at predetermined timings and applied to the vertical transfer electrode 1d and horizontal transfer electrode 1e via the CCD driver 2, respectively, thereby driving the solid-state image sensor I. .

The solid-state image sensor 1 is basically driven by the photoelectric conversion unit 1.
The signal charges accumulated in a according to the amount of incident light are transferred to the first charge transfer register Ib group by synchronizing with the vertical synchronizing signal V5yne and putting the transfer gate 1t in a state where the charges can be shifted. , the signal charges input to the first charge transfer register group 1b are sequentially vertically transferred pixel by pixel according to the vertical transfer pulses VL, -v4. When signal charges for one row in the horizontal direction from the first charge transfer register 1b group are input in parallel to the second charge transfer register IC, the horizontal synchronization signal H5ync
driving the second charge transfer register IC in synchronization with;
According to the horizontal transfer pulses H1 and H2 that drive the second charge transfer register 1c, signal charges for one row in the horizontal direction are read out in time series and output.

Vertical transfer of signal charges in units of one pixel by driving the first charge transfer register (vertical shift register) group Ib, and transfer of signal charges by one pixel by driving the second charge transfer register (horizontal shift register) lc By repeatedly performing the horizontal transfer over the rows, the photoelectric conversion unit 1
The signal charges determined in step a are repeatedly scanned in the row direction and read out in time series.

Now, the video signal corresponding to the signal charge read out from the solid-state image pickup device 1 as described above is applied to the video processing circuit 5 after passing through the floating DEF fusion amplifier (FDA) 4.

In this video processing circuit 5, first, the CDS of its input stage is
The circuit 7 receives the input video signal VI from the solid-state image sensor 1.
Correlated double sampling processing is applied to the DEO to remove low frequency noise components such as reset noise contained in the video signal VIDEO, and to compensate for DC level fluctuations at the pixel signal level.

The video signal VIDEO subjected to such processing is transmitted via the capacitor 8 to the next stage circuit having a different DC operation level. The optical black clamp circuit 9 is connected to the video signal VI transmitted via the capacitor 8 in this way.
Clamping is performed on the DEO using the optical black level OBL as a reference level. In other words, the clamp circuit 9 receives the video signal VIDE as shown in FIG.
On the front porch of O (within the horizontal blanking period),
The DC level is clamped (constant) to the optical black level OBL, and the DC component for the video signal VIDEO is defined as the black level OBL.

To briefly explain this clamping effect, for example, as shown in FIG. 7(a), when the brightness level of the video signal VIDEO read from the solid-state image sensor I changes greatly with changes in the horizontal scanning period, the clamping circuit By passing through the capacitor 8, the video signal transmitted to the video signal 9 becomes an alternating current component waveform whose center potential is the reference potential on the clamp circuit 9 side, that is, a signal waveform as shown in FIG. 7(b). Therefore, if this continues, the DC component that the video signal VIDEO originally had will be lost. Clamp circuit 9
In this way, in order to recover the DC component of the video signal V I DEO that is lost through the capacitor 8, the DC level is optically adjusted during the horizontal blanking period (front porch of the video signal V I DEO). Clamp at black level OBL. As a result, the seventh
As shown in Figure (e), the signal level of the video signal V I DEO at the front porch is defined as the optical black level OBL in the next stage circuit. Then, the video signal VIDEO will be handled correctly.

[Problem to be solved by the invention JVI] By the way, as a method for electronically capturing a subject image using this type of solid-state image sensor l, it is possible to control the accumulation time of signal charges by the solid-state image sensor l and adjust the exposure amount. There is a so-called element shutter that determines the This element shutter discharges unnecessary charges generated in the photoelectric conversion section 1a of the solid-state image sensor l, and then causes the photoelectric conversion section 1a to accumulate signal charges according to the amount of incident light over a predetermined period of time. This signal charge is read out as an image signal at a predetermined timing such as vertical synchronization.

However, conventionally, the process of discharging the unnecessary charge is performed by driving the charge transfer register of the solid-state image sensor 1 at high speed, and some of the unnecessary charge that cannot be discarded is discharged by the overflow drain around the horizontal transfer register. It is discharged as is as the output of the solid-state image sensor 1. Moreover, this unnecessary charge discharge processing is generally carried out at the second stage even during the horizontal blanking period in order to discharge unnecessary charges in all the photoelectric conversion units and shift registers remaining in the solid-state image sensor l.
This is performed by continuously driving the charge transfer register (horizontal shift register) 1c. For this reason, conventionally, the discharge period of unnecessary charge and the clamping timing by the clamp circuit 9 often overlap, and for example, as shown in FIG. 8, the clamping is performed at the timing when the output waveform corresponding to the unnecessary charge component appears. Sometimes I put it away. When such a misclamp occurs, the signal level of the unnecessary charge is lower than the optical black level O, which is originally the lower reference level of the video signal.
Since the BL is specified, the level of the subsequent video signal VIDEO decreases significantly as shown in FIG.
A problem occurred in which so-called black sinking occurred.

FIG. 4 shows the horizontal blanking pulse HBLK, clamp signal (hiclamping pulse) CLP, horizontal transfer pulses H1, H2, and vertical transfer pulse V1. It is a figure showing the timing relationship of ~v4. As can be easily understood from the timing relationship shown in FIG. 4, in this example, even when clamping is performed on the video signal (clamping pulse CLP period), charge readout from the horizontal shift register 1c is continuously driven by the horizontal transfer pulses H1 and H2. As a result, misclamping as described above will occur.

Moreover, when such a misclamp occurs, in reality,
For example, since the steep response operation shown in FIG. 8 is not performed, it takes time to recover the normal optical black level OBL for the subsequent video signal VIDEO, and the A problem has arisen in that the image capturing and recording operation of the video signal V I DEO is hindered.

The present invention has been made in consideration of the above circumstances, and its purpose is to effectively prevent misclamping when unnecessary charges are discharged from an image sensor, and to improve the image signal obtained from the image sensor. An object of the present invention is to provide an image pickup device drive circuit having a simple and highly practical configuration that can always maintain a stable DC level.

[Means for Solving the Problems] An image sensor driving circuit according to the present invention includes a photoelectric conversion section that accumulates signal charges according to the amount of incident light, and a charge transfer register for reading out the charges accumulated in the photoelectric conversion section. The time m1 including the clamping timing for the output of the image sensor within the unnecessary charge discharge period for the image sensor equipped with
The present invention is characterized by comprising means for stopping the charge discharge drive for the charge transfer register in the section.

[Function] According to the present invention, clamp processing is performed on at least the video signal output corresponding to the signal charge read from the charge transfer register even within the period set for discharging unnecessary charges. During this period, reading and outputting charges from the charge transfer register is prohibited, so that the clamping timing for the video signal and the timing for discharging unnecessary charges do not overlap. As a result, unnecessary charges will not be erroneously clamped at the clamp timing, so the DC level of the video signal will not be inadvertently shifted due to misclamping, and the DC level can be stably kept constant. Become.

[Embodiment 2] An image sensor driving circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart conceptually showing the operation sequence when recording a still image in a system to which the present invention is applied, and FIG. FIG. 3 is a diagram showing the timing relationship of each signal. Furthermore, FIG. 3 is a timing diagram showing the timing relationship in detail by expanding the time axis of the main part (A-A section) in FIG. It is configured to be executed selectively.

That is, in FIGS. 2 and 3, a vertical blanking pulse (VBLK), a horizontal blanking pulse (IBL), a clamping pulse (CLP), and a shutter control pulse (5II) are used to show the driving mode of the image sensor characteristic of this system.
T, vertical transfer pulse V1. ~V4. Horizontal transfer pulse H
1, H2,) The timing relationship between the transfer gate pulse TG and the effective image strobe pulse AVS representing the readout section of the effective image signal by the a-body image sensor is shown.

The block configuration of this embodiment system is the same as the block configuration shown in FIG. 5 described above, so the details of the embodiment system will be described here with reference to FIG. 5.

When this system is started, the controller 6 performs processing to identify whether or not a shutter trigger signal is input from a shutter trigger switch (not shown) or the like (step a). When the input of the shutter trigger signal is detected in this identification process, the controller 6 receives photometric information about the imaging target obtained by a photometric means (not shown), and aperture control information for specifying the aperture value in the imaging optical system. (Aperture information) etc., set the time T2 to define the exposure time (signal charge accumulation time) in the element shutter function (
Step b). Next, a time (TI + T2) is set by adding the time T1 necessary for discharging unnecessary charges in the photoelectric conversion section 1a of the solid-state image sensor to the exposure time T2 (Step C). These time settings are made by presetting count values corresponding to the above-mentioned times in the counter function section of the controller 6.

As described above, when the time TI for discharging unnecessary charges and the exposure time T2 for accumulating signal charges are set, the shutter control signal SHT with a time width corresponding to the above time (TI + T2) is transmitted to the controller 6. The signal is applied to the timing signal generation circuit 3 from The timing signal generation circuit 3 generates a transfer gate pulse TG based on such a shutter control signal SHT, and drives the solid-state image sensor with its element shutter.

That is, as shown in FIG. 2, the timing signal generation circuit 3 generates four transfer gate pulses TG within the time period T1.
is applied to the transfer gate of the solid-state image sensor to turn on the gate function. Due to the ON operation of this transfer gate, the photoelectric conversion section 1 of the solid-state image sensor
The unnecessary charge accumulated in a is transferred to the vertical shift register 1b.
group and is discharged via vertical shift register lb group.

The section following the trailing edge of four such transfer gate pulses TG is set as the effective accumulation time of signal charges in the photoelectric conversion section 1a, that is, the exposure time by the element shutter function.

Therefore, from the unnecessary charge discharge time T1 to the exposure time T2
When the shutter control signal SHT falls, the timing signal generating circuit 3 applies a transfer gate pulse TG to the transfer gate of the solid-state image pickup device in synchronization with the falling of the shutter control signal SHT. Due to this ON operation of the transfer gate, the photoelectric conversion section 1a
The signal charges accumulated in the vertical shift register tb are simultaneously transferred to the vertical shift register tb.
readout from the vertical shift register 1tJJ via the horizontal shift register IC is started. This point is the end point of exposure in the element shutter function.

As shown in FIG. 2, the transfer gate pulse TG that defines the end of the exposure is emitted at a time slightly later than the end of the exposure time T2.

Therefore, the time T1 for discharging unnecessary charges in the photoelectric conversion section la
The period T3 from the trailing edge timing to when the transfer gate pulse TG (5-gate transfer gate pulse TG) after the end of the exposure time T2 is emitted becomes a substantial exposure time.

Returning to the processing procedure shown in FIG. 1, the setting of the time (Tl + T2) shown in step C described above defines the pulse width of the shutter control signal SHT as described above, and the shutter This corresponds to issuing the control signal SHT to the solid-state image sensor.

When the shutter control signal 5) IT is issued, the vertical shift register 1b immediately transfers the vertical transfer pulse V1. V2. ~V4 is received and high-speed transfer operation is performed. Due to this high-speed transfer operation of the vertical shift register 1b, unnecessary charges transferred from the photoelectric conversion section 1a are quickly discharged (step d). still,
The frequency itself of the horizontal transfer pulse H1/H2 applied to the horizontal shift register IC at this time is constant.

However, as shown in FIG. 3, which shows the signal timing at the horizontal rate, in the present invention, this horizontal transfer pulse H1/
The setting of the intermittent period of H2 has the following remarkable characteristics.

That is, the horizontal transfer pulse Hl/H2 is equal to the horizontal blanking pulse +1 B that defines each horizontal blanking period.
During the generation period of LK, its generation is controlled to stop. In other words, horizontal blanking pulse 1
In response to the occurrence of tBIJ, the generation and output of the horizontal transfer pulses H1/H2 is controlled to stop, and unnecessary charges are prevented from being discharged from the solid-state image sensor during that period (step e).

As shown in FIG. 3, the clamp pulse CLP that defines the timing for performing clamp processing on the video signal output from the solid-state image sensor is generated within the generation period of the horizontal blanking pulse HBIJ described above. It looks like this. In order to prevent such erroneous clamping of unnecessary charges based on the ramp pulses CI and P, in this system, in order to prevent unnecessary charges from being discharged at the clamp timing, the horizontal transfer pulse Hl/P during the horizontal blanking pulse IIBLK period is This is to stop the generation output of H2.

As a result, unlike the conventional system in which horizontal transfer pulses H1/H2 are continuously generated as shown in Figure 4, unnecessary charges are not discharged at the clamp timing, so mis-clamping occurs during the discharge period of unnecessary charges. is effectively avoided.

Note that the transfer drive of the horizontal shift register lc is stopped within the period (horizontal blanking pulse) IBL during the unnecessary charge discharge period (unnecessary charge discharge period Tl in the photoelectric conversion unit 1a) as shown in FIG. This is the signal charge accumulation time in the photoelectric conversion unit 1a, and is only within the period T2) during which unnecessary charges in the shift register are discharged. It goes without saying that during the reading period of video signals of other centuries, an appropriate ramping operation can be performed on the video signal output read from the horizontal shift register 1c.

As explained above with reference to FIG. 2, when the unnecessary charge discharge period Tl begins, the unnecessary charge discharge operation starts as described above, and the timing signal generating circuit 3 The timing operation continues (step f). After measuring the time T1, the timing signal generating circuit 3 causes the photoelectric conversion section 1a to start accumulating signal charges (step g).

Thereafter, the timing operation for the time (Tl +72) is continued in step h), and at the timing when the timing ends, the drive mode of the vertical shift register lb is switched to the normal operating frequency (step i).

That is, instead of generating high-speed horizontal transfer pulses H1/H2 to discharge unnecessary charges at high speed, horizontal transfer pulses H1/H2 at a normal read speed are generated and output.

When the unnecessary charge discharge drive is completed, the transfer gate is turned on with a slight delay from the completion timing, and the signal charge accumulated in the charge conversion section la is transferred to the vertical shift register 1b as described above (step j). The signal charges transferred and held to the vertical shift register 1b are then transferred to the next vertical blanking pulse VBL.
In step k), the generation of vertical transfer pulses Vl, V2 . ~V
4 and the horizontal transfer pulses H1/H2, the data are sequentially read out from the solid-state image sensor (step m). When this signal charge is read out, an effective strobe pulse AVS is outputted from the timing signal generation circuit 3 in synchronization with the vertical blanking pulse VBLK, and a video signal corresponding to the signal charge read out from the solid-state image sensor is captured. is instructed (step Ω).

After the signal charges are read out in this manner, the system enters a state of waiting for input of a trigger signal again, and returns to the trigger signal detection/identification operation mode.

As described above, according to the present invention, the image pickup device can be removed by a simple configuration including a means for stopping the charge discharge drive in the charge transfer register at the clamping timing for the output of the image pickup device within the unnecessary charge discharge period. It is possible to achieve great practical effects, such as being able to fundamentally avoid the possibility of misclamping occurring in the output video signal from the video signal.

Note that the present invention is not limited to the embodiments described above. For example, within the unnecessary charge discharge period, the drive of the second charge transfer register (horizontal shift register) le is not stopped during the entire horizontal blanking signal IIBLK period, and at least a period in which clamp processing is performed according to the clamp signal CLP. It is sufficient to prohibit the driving of the second charge transfer register IC so as to include the following. Such on/off control of charge transfer driving for the charge transfer register can be easily realized by a timekeeping operation in a controller (microprocessor), gate array, or the like.

In addition, although the explanation has been made here assuming that the first and second charge transfer registers lb and lc are driven using the vertical transfer pulses Vl and ~V4 and the horizontal transfer pulses H1 and H2, the first and second charge transfer registers lb and lc are driven. register lb.

There are no particular limitations on the configuration of 1c or its driving method. In addition, the present invention can be similarly applied not only to capturing still images but also to capturing movie images, and in short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, it is possible to easily and effectively prevent misclamping when discharging unnecessary charges, and to produce an image in which the optical black level is always stably and accurately defined. Great practical effects such as being able to obtain signals can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the transition of operation modes in an image sensor drive circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are signal timing diagrams for explaining the operation of the embodiment circuit, respectively. , FIG. 4 is a timing diagram for explaining the problems in the conventional technology, FIG. 5 is a schematic configuration diagram of an image sensor drive circuit including a solid-state image sensor and its peripheral circuits, and FIGS. 6 to 8 are respectively for solid-state imaging. FIG. 3 is a diagram for explaining an optical black clamp effect on a video signal read out from an element. ■...Solid-state image sensor, la...Photoelectric conversion unit, 1b.
...First charge transfer register group, lc...Second charge transfer register, 2...CCD driver, 3...Timing signal generation circuit, 5...Video processing circuit, 6.
...Controller, 9...Optical black clamp circuit.

Claims (1)

[Scope of Claims] An unnecessary charge discharge period for an image sensor equipped with a photoelectric conversion section that accumulates signal charges according to the amount of incident light and a charge transfer register for reading out the charges accumulated in this photoelectric conversion section. 1. An image sensor driving circuit comprising means for stopping charge discharge drive for a charge transfer register of the image sensor during a time period including a clamping timing for the output of the image sensor.