JPH0316314A - Bias circuit - Google Patents

Abstract

PURPOSE:To make a reference voltage highly stable and to attain ultrahigh speed operation by constituting the bias circuit of the same circuit form as an emitter coupling logic(ECL) circuit operating at ultrahigh speed. CONSTITUTION:A gate circuit GC consists of the ECL and a gate circuit transistor(TR) T3 and a bias circuit TR T11 are turned on off complimentarily when viewing the TRs from a node C, and both the circuits are operated in a direction cancelling the base current. Thus, even when a reference voltage VREF (level of the node C) is fluctuated, the stabilization is implemented quickly and highly stable reference voltage is realized. Thus, the high speed operation required substantially to the ECL circuit is realized.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a reference voltage necessary for bias circuits, particularly ultra-high-speed operation emitter-coupled logic (ECL) circuits used in bipolar digital integrated circuits installed in ultra-large electronic computers, etc. Regarding the bias circuit for supplying the voltage, the purpose of this is to stabilize the reference voltage, contribute to high-speed operation of logic circuits, and facilitate LSI design. , the emitter is connected to a low potential power supply line via a constant current source, and the collector of each of the pair of transistors is
Each of the pair of transistors is connected to a high potential power supply line through a first resistor, and each base of the pair of transistors is connected to a corresponding collector through a second resistor, and a third resistor. The reference voltage is connected to a low-potential power supply line through the transistor, and the reference voltage is extracted from one of the pair of transition terminals.

[Industrial application field]

The present invention relates to a bias circuit, and in particular, a bias circuit for supplying a reference voltage necessary for an ultra-high-speed operation emitter-coupled logic (ECL) circuit used in bipolar digital integrated circuits installed in ultra-large electronic computers, etc. Regarding.

In recent years, ultra-large computers have been required to increase their processing power and speed up processing, and in order to achieve this,
Bipolar digital integrated circuits, especially EC
There is a demand for L circuits to operate at ultra high speeds.

[Conventional technology]

FIG. 3 shows an example of the structure of a conventional bias circuit.

Note that in the following description, unless otherwise specified, the term "transistor" refers to an npn transistor.

In FIG. 3, BC indicates a bias circuit, and GC indicates a gate circuit that receives a reference voltage VREF from the bias circuit. This gate circuit GC has two power supply lines Vcc
(OV) and VEB (VCC>VCB:l), it has the form of an ECL circuit configured between signal power transistors Tl, T2 and reference voltage power transistor T.
3, resistors Rl and R2 connected to the collector side of each transistor, and a constant current source (transistor TO and resistor RO) connected to the common emitter side of each transistor. A bias voltage VB of a level sufficient to turn on the 1 transistor is supplied to the gate of the 1 transistor TO.

During normal operation, a constant current defined by (VB-VIE')/RO flows through either the signal input transistors Tl, T2 or the reference voltage input transistor T3.

The bias circuit BC includes a transistor T4, a diode D, and a resistor R3 connected in series between two power supply lines VCC and VMI, and a resistor R4 and a transistor T5 also connected in series between the power supply lines. and a resistor R5, and a transistor T4.
The base and emitter of are each transistor T5
collector, connected to the base. Reference voltage VRE
F is taken out from the base of transistor T5. This reference voltage VRBF is connected to the transistor T4 and the diode D.
It is defined by the forward voltage drop of , the resistance values of resistors R3 and R4, and the voltage of power supply line VBB.

In this structure, for example, the input signal A of the gate circuit GC
or the level of B decreases and the corresponding transistor T1
Alternatively, when T2 is turned off, the reference voltage input transistor T3 is turned on and draws current from the bias circuit BC through the node C. At this time, the level of the node C drops instantaneously, thereby reducing the current flowing through the transistor T5, and in response, the base potential of the transistor T4 rises, so that the current flowing through the transistor T4 increases.

As a result, a current flows from the power supply line VCC to the node C via the transistor T4, and the level of the node C rises and returns to the original level.

Conversely, when the level of the input signal A or B increases and the corresponding transistor T1 or T2 is turned on, the reference voltage human power transistor T3 is turned off and current is discharged to the bias circuit BC through the node C. At this time, the level of the node C rises instantaneously, thereby increasing the current flowing through the transistor T5, and in response, the base potential of the transistor T4 decreases and the current flowing through the transistor T4 decreases. In this case, the charge corresponding to the increase at node C flows into power supply line VEH via diode D and resistor R3, so that the level of node C gradually settles to the original level.

In other words, when the level of node C (reference voltage VREF) decreases, transistor T5 operates in an off-tendency, then transistor T4 operates in an on-tendency, so that node C returns to its original level; When the level of C rises, the charge on the node C is drained through the diode D and the resistor R3, so that the level of the node C increases.
returns to its original level, and in either case, the response operation to fluctuations in the reference voltage VREF is not performed quickly.

[Problem to be solved by the invention]

In the conventional bias circuit described above, the reference voltage VREF
It is not designed to respond quickly to fluctuations in . Therefore, for example, the gate circuit G is connected to the reference voltage VREF.
Even if noise is superimposed from C, a recovery operation for canceling out the noise, that is, an operation for stabilizing the reference voltage to its original level, cannot be performed at high speed. In other words, since it is not possible to quickly follow changes in noise, the reference voltage becomes unstable, which in turn causes the disadvantage that the operating speed of the gate circuit itself decreases. This cannot be said to be preferable from the viewpoint of realizing the high-speed operation originally required of the ECL circuit.

Furthermore, recently, SOG (Sea of Gate), that is, gate-packed LSI, has been proposed as a measure to achieve high integration and large scale, but in this case, a bias circuit is installed between each gate circuit. It will be necessary to arrange it appropriately.

However, according to the conventional structure, the bias circuit BC and the gate circuit GC have different circuit formats, so LSI designers have to decide how to place the bias circuit and the relationship between the functional blocks (multiple gate circuits). I had no choice but to do the layout with great difficulty.

In other words, there is a problem in that it is extremely complicated to arrange the bias circuit and the gate circuit in a mixed manner. This cannot be said to be preferable from the viewpoint of improving the efficiency of LSI design.

The present invention was created in view of the problems in the prior art described above, and provides a bias circuit that stabilizes the reference voltage, contributes to high-speed operation of logic circuits, and facilitates LSI design. is intended to provide.

[Means to solve the problem]

The above-mentioned problems in the prior art can be solved by configuring the bias circuit in the same circuit type as the ECL circuit that receives reference voltage from the bias circuit.

Therefore, according to the present invention, the bias circuit supplies a reference voltage to an ECL circuit, and includes a pair of transistors connected with their emitters in common, and the emitters are connected to a low potential power supply line via a constant current source. each collector of the pair of transistors is connected to a high potential power supply line through a first resistor, and the base of each of the pair of transistors is connected to a corresponding one through a second resistor. A bias circuit is connected to the collector and to a low potential power supply line via a third resistor, and is configured to take out the reference voltage from the base of one of the pair of transistors. provided.

[For production]

Since the bias circuit is configured in the same current mode logic (CML) circuit format as the ECL circuit, the base potential (reference voltage) of one of the pair of transistors is the same as the ECL circuit.
Even if the reference voltage fluctuates, the fluctuation is quickly offset by the action of the current switch, and the reference voltage can be stabilized. This contributes to realizing the high-speed operation originally required of the ECL circuit.

Furthermore, since the bias circuit and the ECL circuit have the same circuit format, it is possible to easily arrange both circuits in a mixed manner without requiring any complicated effort during LSI design.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows the structure of a bias circuit as an embodiment of the present invention together with the structure of a gate circuit (ECL circuit).

In the figure, BCI is a bias circuit, GCf''! A gate circuit that receives the reference voltage VREF from the bias circuit, V
CC, VEE and VT are power supply lines of specified voltage, V
B indicates the bias voltage for the constant current source. In addition, the magnitude of each voltage, VCC (OV) > VR [EF > VB, VT
>VEE relationship is satisfied.

The gate circuit GC is composed of an ECL, and transistors Tl and Tl are connected in parallel and respond to human input signals A and B, respectively.
T2, and a transistor T having a common emitter and connected in parallel with the transistor and responding to the reference voltage VRBF.
3, a resistor R1 connected between the collectors of the transistors Tl and T2 and the power supply line VCC, a resistor R2 connected between the collector of the transistor T3 and the power supply line VCC, and the emitter of each transistor and the power supply line VCC. It consists of a transistor TO and a resistor RO connected between the line VB[E and forming a constant current source. A bias voltage VB of a level sufficient to turn on the transistor is supplied to the base of the transistor TO. During normal operation, signal input transistors Tl, T
A constant current defined by (VB - VB6) /RO flows through either the transistor T2 or the reference voltage human power transistor T3.

On the other hand, the bias circuit BCI is also constructed of ECL like the gate circuit IGC. That is, it includes a pair of transistors T11 and T12 connected with their emitters in common, and the common emitter is connected to the power supply line VBIE through a constant current source consisting of a transistor TIO which responds to a bias voltage VB and a resistor R10. ing. The collector of the transistor Tll is connected to the power supply line vCC via a resistor Rll, and the base thereof is connected to the collector via a resistor R12 and to the power supply line VT via a resistor R13. Similarly, the collector of transistor T12 is connected to the power supply line vCC through a resistor R14, and its base is connected to the collector through a resistor R15 and to the power supply line VT through a resistor R16. ing. The reference voltage VRIEF necessary for the gate circuit GC is taken out from the base of the transistor Ti1. This reference voltage VREF is the voltage of the power supply line VT and the resistors R11, R12 . It is defined by each resistance value (voltage division ratio) of R13.

Transistor T1 in gate circuit GC. Similar to T2 and T3, the l transistors Tll and Tl2 in the bias circuit BCI also constitute a current switch, and during normal operation, both the transistors TIL and T12 have (VB-VEB)/RIO(D A constant current, defined by half, flows.

According to the structure of this embodiment, for example, when the level of the input signal A (B) of the gate circuit GC decreases and the corresponding transistor Tl (T2) turns off, the reference voltage input transistor T3 turns on and the bias circuit Pull out current from BCI. At this time, current flows through resistor R12 and node C
The level of T1 decreases instantaneously, thereby decreasing the current flowing through transistor Tll and increasing the current flowing through transistor TI2.

As a result, the current flowing through the resistor Rll is relatively reduced, and the level of the node C, which once dropped, quickly rises, and i+/bell is stabilized.

Conversely, when the level of the input signal A (B) of the gate circuit GC rises and the corresponding transistor TI (T2) turns on, the reference voltage input transistor T3 operates in the off direction and supplies current to the bias circuit IBcI. Spit it out.

As a result, the level of node C rises instantaneously, and transistor Tll turns on (transistor T12
operates in the OFF direction. As a result, the current flowing through the resistor Rll increases relatively, and a portion of the current also flows through the resistor R12, so that the level of the node C decreases, and the level of the node C is stabilized to the original level.

In this way, when viewed from the node C, the gate circuit side transistor T3 and the bias circuit side transistor Tll perform on/off operations opposite to each other, so that both circuits operate in the direction in which their respective base currents cancel each other out. It has become. Therefore, even if the reference voltage VREF (the level of node C) fluctuates, it is quickly stabilized, and the reference voltage can be highly stabilized. This contributes to realizing the high-speed operation originally required of the ECL circuit.

In addition, since the bias circuit is constructed in the same ECL circuit format as the gate circuit, it is particularly suitable for SOG type LS. I
In this case, the bias circuit can be easily placed anywhere without having to worry about the placement relationship between the bias circuit and each gate circuit. That is, it becomes possible to arrange bias circuits and gate circuits in a mixed manner, which greatly facilitates LSI design.

Note that in the embodiment described above, the resistor R13. R16 is configured to be connected to the power supply line VT;
It may be configured to be connected to the EB.

〔Effect of the invention〕

As explained above, according to the bias circuit of the present invention, E
By configuring the circuit in the same circuit format as the CL circuit, it is possible to achieve high stability of the reference voltage, which in turn contributes to the ultra-high speed operation of the ECL circuit. Further, since both circuits have the same circuit format, both circuits can be arranged in a mixed manner during circuit design, which is extremely useful from the viewpoint of improving the efficiency of LSI design.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the structure of a bias circuit as an embodiment of the present invention, Fig. 2 is a circuit diagram showing the structure of a modification of the embodiment shown in Fig. 1, and Fig. 3 is an example of a conventional type. 2 is a circuit diagram showing the configuration of a bias circuit as shown in FIG. (Explanation of symbols) BCI, BC2...bias circuit, GC...gate circuit (ECL circuit), TIO~TI2...transistor, RIO~R16...resistor, VCC, !/8B, VT・・・Power supply −t i'/, V
R庳F...Reference voltage, VB...Bias voltage. FIG. 1 is a circuit diagram showing the configuration of a bias circuit as an embodiment of the present invention. FIG. 2 is a circuit diagram showing the configuration of a modification of the embodiment.

Claims (1)

[Claims] A reference voltage (VRE) is applied to an emitter-coupled logic circuit (GC).
F) is a bias circuit that supplies a pair of transistors (F) connected with a common emitter.
T11, T12), the emitter is connected to a low potential power line (VEE) via a constant current source (VB, T10, R10), and each collector of the pair of transistors is connected to a first resistor. (R11, R14) to a high potential power line (VCC), and each base of the pair of transistors is connected to a corresponding collector via a second resistor (R12, R15). and is connected to a low potential power supply line (VT, VEE) via a third resistor (R13, R16), and the reference voltage is taken out from the base of one of the pair of transistors. bias circuit.