JPH0316096U - - Google Patents
Info
- Publication number
- JPH0316096U JPH0316096U JP7659689U JP7659689U JPH0316096U JP H0316096 U JPH0316096 U JP H0316096U JP 7659689 U JP7659689 U JP 7659689U JP 7659689 U JP7659689 U JP 7659689U JP H0316096 U JPH0316096 U JP H0316096U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- time
- circuit
- alarm
- time information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electric Clocks (AREA)
- Electromechanical Clocks (AREA)
Description
第１図は本考案におけるアラーム時計の一例を
示したブロツク図であり、第２図はその外観を示
した説明図である。
ＭＡ……主時計、１９……出力端子、ＳＵ……
副時計、３１……計時回路、３２……記憶回路、
３３……検出回路、３９……入力端子。
FIG. 1 is a block diagram showing an example of an alarm clock according to the present invention, and FIG. 2 is an explanatory diagram showing its appearance. MA...Main clock, 19...Output terminal, SU...
Sub-clock, 31...Timekeeping circuit, 32...Memory circuit,
33...Detection circuit, 39...Input terminal.
Claims (1)
報を出力する出力端子を有する主時計と、 上記主時計の上記出力端子から出力される上記
時刻情報を入力する入力端子と、入力された時刻
情報に基いて現在時刻を計時する計時回路と、入
力された時刻情報に基いてアラーム時刻を記憶す
る記憶回路と、上記計時回路における現在時刻と
上記記憶回路におけるアラーム時刻との一致を検
出する検出回路とを有する副時計とからなり、 上記主時計の出力端子と上記副時計の入力端子
とが着脱自在に構成されたアラーム時計。[Claims for Utility Model Registration] A master clock having an output terminal for outputting time information corresponding to the current time and alarm time; an input terminal for inputting the time information output from the output terminal of the master clock; A clock circuit that clocks the current time based on input time information, a storage circuit that stores an alarm time based on the input time information, and a match between the current time in the clock circuit and the alarm time in the storage circuit. 1. An alarm clock comprising: a sub-clock having a detection circuit for detecting a detection circuit, wherein an output terminal of the main clock and an input terminal of the sub-clock are detachably configured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7659689U JPH0316096U (en) | 1989-06-29 | 1989-06-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7659689U JPH0316096U (en) | 1989-06-29 | 1989-06-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0316096U true JPH0316096U (en) | 1991-02-18 |
Family
ID=31618208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7659689U Pending JPH0316096U (en) | 1989-06-29 | 1989-06-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0316096U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014513298A (en) * | 2011-04-29 | 2014-05-29 | コーニンクレッカ フィリップス エヌ ヴェ | Method and system for managing alarm signals and an alarm clock having such a system |
-
1989
- 1989-06-29 JP JP7659689U patent/JPH0316096U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014513298A (en) * | 2011-04-29 | 2014-05-29 | コーニンクレッカ フィリップス エヌ ヴェ | Method and system for managing alarm signals and an alarm clock having such a system |
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