JPH0316063A - Magnetic reproducing device - Google Patents

Abstract

PURPOSE:To effectively evade a bit error and to obtain a correct decoded data by initializing a data of probability upon detriment to the continuity of the data. CONSTITUTION:The magnetic reproducing device 1 for reproducing a prescribed data DPR recorded on a magnetic recording medium 14 by utilizing a partial response system, is provided with data detecting circuits 20-25 and 28 for detecting the continuity of data DR, DA and DSUB contained in a regenerative signal SRF and Vitervi decoding circuits 35 and 36 for decoding the regenerative signal SRF and also for initializing the data DELTAk of probability based on a detecting result SEXZ of the data detecting circuits 20-25 and 28. That is, the continuity of the data DR, DA and DSUB contained in the regenerative signal SRF is detected, and the data DELTAk of probability is initialized based on this detecting result SEXZ, so that the decoding of the regenerative signal SRF with a reference of the data DELTAk of probability which is erroneous can effectively be evaded. By this method, the data securely is reproduced.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Conventional technology D. Problems to be solved by the invention (Figures 23 and 24)
Figure) Means for solving the E problem (Figures 1 and 2) F action (Figures 1 and 2) G embodiment (G1) First embodiment (Figures 1 to 19) ) (G2) Second embodiment (Fig. 20) (G3) Third embodiment (Fig. 21) (G4) Other embodiments (Fig. 22) H Effect of invention A Industrial application field Book The present invention relates to a magnetic reproducing device, and is suitable for application to, for example, a video table recorder configured to reproduce digital video signals.

B Summary of the Invention The first invention makes it possible to effectively avoid bit errors in a magnetic reproducing device by initializing probability data when data continuity is impaired.

Furthermore, in a second aspect of the invention, in a magnetic reproducing device, by detecting a certain portion of the signal suppressed by arithmetic processing, the beginning of continuous data can be reliably detected.

C. PRIOR TECHNOLOGY Conventionally, in a general video tape recorder, which is a magnetic reproducing device of this type, a video signal recorded as an analog signal is reproduced using, for example, a frequency modulation method. D Problems to be Solved by the Invention By the way, if the video signal is converted into a digital signal and recorded on a magnetic tape, deterioration in image quality can be effectively avoided no matter how many times dubbing is performed.

However, as shown in FIG. 23, when recording and reproducing signals on a magnetic tape, the magnetic head, etc.! Since the magnetic conversion system has differential characteristics, the CN ratio deteriorates at lower frequencies, whereas as the frequency increases, the CN ratio similarly deteriorates due to the magnetization characteristics of the magnetic tape.

Therefore, in a magnetic recording/reproducing system, a digitized video signal (hereinafter referred to as a digital video signal) has a characteristic that the frequency band is narrow in order to obtain a good CN ratio.

Therefore, when recording digital video signals, select a recording method that concentrates the spectrum of the signal near the maximum CN ratio.This effectively avoids deterioration of the CN ratio of the reproduced signal and It is necessary to efficiently record and reproduce video signals. In this case, a method of recording and reproducing the digital video signal may be considered using a partial response method of class (1), which is one of the high-efficiency encoding methods.

In other words, in magnetic recording and reproduction, the CN ratio deteriorates at low and high frequencies, so the frequency characteristics are expressed by the class ■ partial response ( 1-D”) can be approximated and expressed as the frequency characteristic H(ω).

By the way, the frequency ωO at which the response is minimum (that is, the Nycast frequency) is determined by the following formula for the delay time T expressed by the delay operator D? ω. 1■・・・・・・(1) There is a relationship of T.

Therefore, select the amount of delay represented by delay operator D,
It is believed that by concentrating six spectral signals in the vicinity where the CN ratio is maximum, digital video signals can be efficiently recorded and reproduced by effectively utilizing the frequency characteristics of the magnetic recording and reproducing system.

That is, during recording, if the arithmetic processing expressed by the following equation is sequentially performed on the digital video signal, the frequency characteristics of the digital video signal can be converted into a recording signal that approximates the frequency characteristics of the magnetic recording and reproducing system. be able to.

Therefore, by sequentially recording the recording signals on the magnetic tape, the frequency characteristics of the magnetic recording and reproducing system can be effectively utilized.
It is believed that digital video signals can be recorded efficiently.

By the way, MOD2 represents the remainder of 2.

On the other hand, since the electromagnetic conversion system has differential characteristics, the reproduced signal output from the magnetic head is expressed as (1-D) using the delay operator D, and is indicated by the broken line in Fig. 24. It is expressed by the frequency characteristics shown below. Therefore, during playback, (1+
By executing the arithmetic processing in D), the following equation (1 - D) (1 + D) -1 - D'' ...... (3) can be added as a whole, and thereby It is thought that it is possible to reproduce a digital video signal by setting the transfer function to 1 for the entire system.
When recording and reproducing digital video signals using the partial response method, it is thought that it is possible to reproduce digital video signals with fewer bit errors by applying the Viterbi decoding method. That is, the Viterbi decoding circuit detects transitions in the data by using the correlation between successively input data, and decodes the data based on the detection result.

Therefore, if the recorded signal is decoded from the reproduced signal using the (1-D) relationship of the reproduced signal with respect to the recorded signal, and then the digital video signal is decoded based on the decoded data, the signal level can be used as the standard. Compared to general decoding circuits,
It is believed that bit errors in decoded data can be reduced.

However, in this type of magnetic recording/reproducing device, the recording signal is divided and recorded for each recording track, so it becomes difficult to provide continuous data to the Viterbi decoding circuit at the timing of switching recording tracks. .

Furthermore, in this type of magnetic recording/reproducing apparatus, it is difficult to avoid dropout, which also makes it difficult to provide continuous data to the Viterbi decoding circuit.

Therefore, in such a case, there is a problem that it becomes difficult to obtain correct decoded data via the Viterbi decoding circuit, and it becomes difficult to reliably reproduce the digital video signal.

The present invention has been made in consideration of the above points, and aims to propose a magnetic reproducing device that can obtain correct decoded data. ? Means for Solving the Problems In order to solve the problems, in the first invention, a partial response method is used to improve the magnetic recording medium 14.
In the magnetic reproducing device 1, which is configured to reproduce predetermined data D. ,D. , DSt+1, the data detection circuits 20, 21, 22, 23, 24, 25, 28 and the data detection circuit 20, which decodes the reproduced signal
, 21, 22, 23, 24, 25, 28 detection results St
Viterbi decoding circuits 35 and 36 are provided to initialize likelihood data Δk based on o.

Furthermore, in the second invention, in the magnetic reproducing device 1 configured to reproduce predetermined data D recorded on the magnetic recording medium 14 using the partial response method, the reproduced signal S0 is (1-D) an arithmetic processing circuit 20 that performs arithmetic processing; and signal detection circuits 2l, 22, 23, 2 that detect a certain amount of the signal S suppressed by the arithmetic processing circuit 20.
4 and 25.

? Data DR, DA, D included in the action reproduction signal S■! I.J.
The continuity of II is detected and the detection result is S,. By initializing the likelihood data Δk based on , it is possible to effectively avoid decoding the reproduced signal SIF based on the incorrect likelihood data Δk.

Furthermore, if the arithmetic processing circuit 20 detects the suppressed signal component SP, it is possible to detect a certain portion of the signal SP at the Nycast frequency, and the beginning of the data can be detected with high accuracy.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) First embodiment (Gl-1) Recording system In FIG. 1, 1 indicates a video tape recorder as a whole, and the clock signal SCKjl is four times as large as the subcarrier signal.
. A video signal Sv is applied to an analog-to-digital conversion circuit 2 which is configured to operate as follows.

As a result, from the analog-to-digital conversion circuit 2 to 8
A digital video signal Dv of approximately 25 bits (MBPS) is compressed by the data compression circuit 4.
) is converted to data D. On the other hand, an error correction circuit (ECC) 6 receives the digital video signal D1 from the data compression circuit 4 as well as the digitally processed audio signal DA, divides it into predetermined blocks, and performs shunting and error correction. It is designed to perform code addition, etc. Furthermore, the error correction circuit 6 is configured to receive sub-data Dsu+s structured with recording track number, video signal time code, etc. As shown in the figure, the digital video signal DI, audio signal Da, and sub data I)sum are sequentially output one block at a time for a predetermined period of time.

As a result, the error correction circuit 6 converts the digital video signal D and the audio signal D, as shown in FIG.
Approximately 30 (MB) composed of A and sub data D317I
The recording data Dmzc (FIG. 3(A)) of PS:1 is output to the precode circuit 8.

On the other hand, as shown in FIG. 4, the bricode circuit 8
Record data DI in exclusive OR circuit 8A! . Then, the output data of the exclusive OR circuit 8A is recorded as recording data D0. The signal is fed back to the input terminal of the exclusive OR circuit 8A via two stage delay circuits 8B and 8C which operate at a repetition frequency of .

As a result, the precode circuit 8 executes the arithmetic processing of (2) 2 and uses the correlation between the data of the record data DIItc to generate the record data D■. The value 1 and -? 3 (B)) and outputs it to the adder circuit 9. The adder circuit 9 receives a predetermined reference signal SP together with the bricode data Dpt, and adds the core reference signal S, before and after the digital video signal DI% audio signal DA and the sub data DSLIM that make up the bricode data Dpt. is added before and after each block.
It is designed to form a post ampoule and a briand ampoule (Figure 2). Therefore, by detecting the reference signal during playback, it is possible to detect the starting point of each data. By the way, the reference signal S2
is the repetition frequency 3 of the bricode data D■
The clock signal SCKI! It consists of a single frequency sine wave signal synchronized with C.

Therefore, the frequency of the reference signal Sp is a frequency ω that satisfies equation (1). At the same time, during reproduction, the reference signal S,
By creating a clock signal using the clock signal, the reproduced signal can be processed using the clock signal as a reference.

Furthermore, the adder circuit 9 is configured to output its output signal to the magnetic heads 12A and 12B via the amplifier circuit 10.

On the other hand, the magnetic heads 12A and 12B are arranged at angular intervals of 180 degrees on a rotating drum (not shown), thereby forming recording tracks in sequence and alternately on the magnetic table l4. It is designed to do this. At this time, the rotational speed of the rotating drum is set such that the magnetic head 12A or 12B starts scanning at the timing when the reference signal S added to the beginning of the digital video signal D is output to the magnetic head 12A or 12B. As a result, the reference signal S, 1 block of digital video signal DA, the reference signal S, 1 block of audio signal DA%, the reference signal S, , the sub data DSuff
i, the reference signal S, are recorded in the order of one recording track? It is designed to form a square.

Thus, as shown in FIG. 5, during reproduction, the reference signal S, digital video signal DI1, audio signal D. A reproduced signal SIF (FIG. 5(A)) can be obtained by repeating the sub data D3 and D3 at a period T of half a rotation of the rotating drum. Furthermore, in this embodiment, the reproduced signal SI
While demodulating F and displaying the image, separate audio signal D
A and the sub-data Dsum can be re-recorded (that is, by post-recording), and in this case, a reference signal S synchronized with the audio signal DA and the sub-data D3Ul is provided before and after the audio signal DA and the sub-data Dsum. The audio signal DA and sub data D Sum can be updated while the data is added.

(Gl-2) The reproduction system magnetic heads 16A and 16B receive the reproduction signal SIIF,
Via the amplifier circuit l8 and equalizer circuit 19? It is output to the arithmetic processing circuit 20.

On the other hand, as shown in FIG. 6, the arithmetic processing circuit 20
It consists of an adder circuit 21 and a delay circuit 22 that operates at the cycle of the reference signal SP, and reproduces the reproduced signal SIIF.
The arithmetic processing of (1+D) is executed for C (FIG. 3(C)).

As a result, the arithmetic processing circuit 20 can correct the reproduced signal S, as expressed by equation (3), and thereby the output signal S, whose amplitude changes depending on the logic level of the recorded data D, (Fig. 3(D)) can be obtained.

? Gl-3) Data Detection Circuit On the other hand, the envelope detection circuit 2l is configured to envelope-detect the reproduced signal S■ output from the equalizer circuit 19.

Therefore, as shown in FIG. 7, in the normal playback mode, when dropout occurs, the playback signal S
The signal level in Figure (A)) decreases at the dropout, so this is the case? Therefore, the envelope detection signal S decreases in signal level. (2) (FIG. 7(B)), whereas if dropout does not occur, the envelope detection signal S is maintained at approximately a predetermined signal level. Vl (FIG. 5(B)) can be obtained.

On the other hand, as shown in FIG. 8, in the variable speed reproduction mode, the reproduction signal Sur (FIG. 8 (A) and (B))
The envelope changes to an abacus bead shape, and the reproduced signal S■
The signal level of the reproduced signal SIIF partially decreases, and the continuity of the data included in the reproduced signal SIIF is lost before and after the portion where the signal level decreases.

Therefore, in the variable speed playback mode, it is possible to obtain an envelope detection signal S0■ whose signal level changes in an abacus-like manner.

The comparison circuit 22 compares a predetermined reference level and the envelope detection signal S! NVI comparison results S,. M,, (Figure 5 (C
) and FIG. 7(C)), and thereby, based on the signal level of the reproduced signal SRF? Detect dropout and partial signal level drop in variable speed playback mode.

On the other hand, the envelope detection circuit 23 outputs the output signal S
F and outputs its envelope detection signal SEHVt to the comparator circuit 24.

In this case, in the output signal S, ((Fig. 5 (D)), by selecting the frequency of the reference signal S, as the frequency expressed by equation (1), the reference signal The signal level of SP is suppressed and output.

Therefore, the envelope detection signal S! MV■((Figure 5(
In E)), in addition to the dropout part and the partial reduction in the signal level in the variable speed playback mode, the i level is increased in the part between the digital video signal D3, the audio signal DA and the sub data I)sum. It drops to almost O level.

The comparison circuit 24 compares the predetermined reference level with the envelope detection signal S ENV* s cospz (fifth
Figure (F)) is made to obtain, thereby regenerating? Regarding the signal SRF, it is possible to detect a dropout portion, a portion where the signal level partially decreases in the variable speed reproduction mode, and a portion of the reference signal St. The exclusive OR circuit 25 outputs the comparison result S CON
(1) The exclusive OR of S CONFg and S CONFg is obtained, and the arithmetic processing (1+D) is thereby performed to detect the portion of the reference signal S whose signal level has been suppressed. Thus, in this embodiment, PL L (ph
(locked loop) circuit 26, generates a reproduction clock signal SCIIPm synchronized with the reproduced reference signal Sp, and controls the entire video table recorder l based on the reproduction clock signal SeKPl. It is designed to drive the playback system. Furthermore, in this embodiment, a pulse generator (P
After clearing a counter circuit (not shown) with a reference pulse signal (that is, a switching pulse signal (swp)) output from C) at the rotation period of the rotating drum, the output signal S! The first rising edge of XI (i.e., at the beginning of the digital video signal DI) and the last falling edge (i.e., at the end of subdata D!01)
This detects the magnetic head 16A.
and 16B detect the timing of scanning the recording track. In fact, in a normal video table recorder, the timing at which the magnetic head scans the recording track is detected using only the reference pulse signal of the pulse generator as a reference, and thereby the reproduced signal is processed for each recording track. It is done like this. However, since variations in the mounting position of the pulse generator cannot be avoided, it is difficult to obtain highly accurate detection results when detecting the timing of the magnetic head scanning the recording track using only the reference pulse signal as a reference. becomes difficult.

Especially if high recording density is desired, as in this example? When recording and reproducing information, it is difficult to obtain sufficient accuracy for practical use when detecting the beginning of each piece of recorded data based only on the reference pulse signal. However, if a certain portion of the signal suppressed by the arithmetic processing circuit 20 is used as a reference, a highly accurate detection result can be obtained, and the beginning of each data can be reliably detected and the reproduced signal S It can be processed. On the other hand, the exclusive OR circuit 28 outputs the output signal SEX+ of the exclusive OR circuit 25 and the comparison result S Co. (1) to obtain the exclusive OR of (1+D), thereby suppressing the reference signal S
In addition to the P portion, a portion where the signal level has decreased due to dropout and a portion where the signal level has locally decreased in variable speed playback mode are detected. (Gl-4) Decoding circuit In contrast to this, analog-digital conversion circuit 29? , driven by a reproduction clock signal SCKPI,
As a result, the signal level of the output signal SF is converted into a digital value at the cycle in which the signal level of the reproduced signal SIIF rises and falls, and the resulting input data y5 is output to the selection circuit 30.

By the way, the human power data yk obtained by executing the calculation process of (1 + D) in this way is the bricode data DPI
For +, the relationship (1-D2) is maintained.

In this case, as shown in FIG. 9, the arithmetic processing of (1-D'') for the bricode data DPI is as follows: {i! b., b.
,,..., consecutive bricode data D■
This means that the subtraction process is repeated by delaying the clock cycle.

Therefore, as shown in FIG. 10, input data y. If it is separated into even and odd sequences, the precode data DPI
The arithmetic processing of (1-D") for (1-D") is performed on precode data DPI1 of even and odd series, respectively.
This is equivalent to executing the calculation process.

Therefore, if input data y is separated into even and odd sequences, precode data DPR can be decoded using the relationship (1-D). On the other hand, in a magnetic recording/reproducing system, since noise is mixed in the electromagnetic conversion system, as shown in FIG. It can be equivalently expressed as an addition circuit 32 that adds noise SN to the output signal SF of the circuit 31.

Therefore, if the output signal SF is extracted for each even number series and odd number series of precode data DPI, as shown in FIG. 33 output signal SF
It can be rewritten with an addition circuit 34 that adds noise SN to .

Therefore, if input data yk is divided into even and odd sequences and then Viterbi decoding is applied using the relationship (1-D), it is possible to reduce bit errors and decode bricode data D0. Can you do it? .

For this reason, in this embodiment, the input data yk is divided into even number series and odd number series and decoded, and at this time, the input data yk is decoded using the Ferguson's algorithm
Viterbi decoding circuit 35 applying ALGOLITHM)
and 36, the input data y is
Decrypt II.

That is, the selection circuit 30 sequentially switches the contacts in synchronization with the input data yk, thereby dividing the input data y into even number series and odd number series data.
5 and 36.

Incidentally, if you perform the calculation process (1-D) on precode data D■, the calculation result of value 2 or value -2 will be obtained for consecutive data of values 1, -1 or values -1, l, respectively. Therefore, as shown in FIG. 13, in the output signal Sr mixed with noise (FIG. 13 (A)), the amplitude value fluctuates around the value 2 or -2, and the symbol P1 Pulse-like noise is mixed in as shown in .

As a result, as shown in FIG. 14, the Viterbi decoding circuit 35
In (36), for example, the values 1.8, 1.2,
-1.7, 0, 0.8, ...... input data)'
lIsyk+1... (FIG. 13(B)) is input, and the input data yu, y. , . . . are outputted to the comparator circuit 40 and the latch circuit 4l via the adder circuits 38 and 39, respectively.

The latch circuit 41 receives data D, which is the decoding result output from the comparison circuit 43 (that is, corresponds to the input data yk).
It has a memory means 44 and a switch means 45 configured to store probability data Δk of the comparison circuit 4.
When data D of values 0 to 1 and -1 is output, the switch means 45 is turned on to take in the data output from the adder circuit 39 and update the probability data Δk. ing.

Incidentally, in this case, probability data Δk of the value O is stored as an initial value.

On the other hand, the adder circuit 38 sends the probability data Δk (corresponding to the input data yk one clock period before) stored in the latch circuit 41 and the subtracted data D2 of the input data)'m++ to the comparator circuit 40. It is designed to output.

The comparison circuit 40 converts the subtracted data D2 into data D of the value LO, -1 (hereinafter referred to as predicted input value) at a threshold level of ±1, and converts the predicted input value D3 into data D, which is referred to as a predicted input value. Make it.

In other words, the exact data Δk and the input data yk
1, if the following formula Δk>'l1-+>1 (4) holds true, the predicted input value D3 is set to the value 1 and stored in the memory 44. Likelihood data Δk
is expressed by the following formula Δ (k+1) = Vk. r + 1...
...(5) Update to probability data Δ(k+l) expressed as follows.

On the other hand, the following formula Δk>'++. When the relationship t<1 (6>) is established, the predicted input value D3 is set to the value -1, and the probability data Δ stored in the memory means 44 is
k is updated to probability data Δ(k+1) expressed by the following formula Δ (k+1)−ym−+ 1 (7).

Furthermore, when the following equation 1Δk 1m-+ <1 (8) holds true, the predicted input value D, is set to 0, and the probability data Δk is calculated by the following equation Δ(k+1 )−Δk
......The probability data Δ(
This means that, as shown in Fig. 15, if the value of the input data ``/k*1 changes by more than the value l (Fig. 15 (A) ), set the predicted input value D, to the value -1 or the value 1 in the opposite direction to the fluctuation direction, and set the value 1 smaller than the value of the human input data y to the new probability data Δ(k+1). means to update (first
Figure 5 (B)). Therefore, if the value of input data yk*1 changes significantly beyond the area indicated by diagonal lines, the value 1 or the value -1
The predicted input value D, is obtained, and the input data)'kl
The probability data Δ(k+1) of the value according to the O value is updated, whereas if the change does not exceed the area shown by the diagonal line, the predicted input value D, of the value O is output, and the probability data is updated to Δ(k+1). Data Δ(k+1) is retained as is.

As a result, as shown in FIG. 16, if a predicted input value D of value 1 is obtained, input data)'m++
If the value of y3 falls, it can be determined that the value of input data y3 at least l clock cycle ago would have risen significantly to the positive side.

Therefore, even when large noise is mixed in at the timing of the input data y11, it can be seen that the value of the bricode data exhibits changes other than the transition rising from the value -1 to the value 1 and the transition remaining at the value -1. Conversely, as shown in FIG. 17, if the predicted human power {I D 3 with the value -1 is obtained, the input data yk &
When the value of yk rises, it can be determined that the value of the input data yk at least l clock period ago would have fallen significantly on the negative side. Therefore, even if a large amount of noise is mixed into the input data)'ka+ timing, the value of the bricode data exhibits changes other than the transition that falls from the value 1 to the value -1 and the transition that remains at the value 1. I understand that.

On the other hand, as shown in FIG. 18, if the predicted input value D, of value O is obtained, the input data
*This means that the change in t was small, and even if large noise is mixed in, the value of the bricode data will change other than the transition rising from value 1 to value 1 and the transition falling from value 1 to value 1. It can be seen that this was exhibited.

Therefore, as shown in FIG. 19, the values 1, ? If the predicted input value D3 of O is obtained, the bricode data D■
It can be seen that the value of is either a transition in which the value 1 continues after falling from the value 1 to the value -1, or a transition in which the value 1 continues.

On the other hand, if a predicted input value D, of value -1 is subsequently obtained, then a change other than the transition rising from value -1 to value 1 and the i transition held at {i-1 will occur. From this fact, it is determined that the value of the continuous bricode data D2 two clock cycles ago is a transition in which the value 1 continues after falling from the value 1 to the value -1.

Similarly, if a predicted input value D of value -1 is followed by a predicted input value D of value 1, then when a predicted input value D of value -1 is obtained here, the bricode data D■ It can be seen that the value of has risen from the value -1 to the value 1.

Thus, based on the successive predicted input values D3, the bricode data D. It is possible to determine the transition of the data D1, , and thereby decode the recorded data D1, .

Furthermore, at this time, the probability data Δk is (4>~(
9) As expressed in equation 9, when input data h changes by 1 or more, it is updated according to the value of input data h, so the larger the absolute value of that value, the predicted input value D , it can be determined that the transition of the bricode data DPI determined by , is more reliable. Based on this detection principle, the Viterbi decoding circuit 35 (36) sequentially updates the probability data Δk, and detects the transition of the human identity data y, based on the updated probability data Δk. In other words, for the probability data Δk of value 0, the value 1
．． When input data 7 k** of 8 is input, the value=1.
By obtaining the subtracted data of 8, the predicted input value D of value -1 is output (Fig. 13 (B)), and the probability data Δk is updated to the value 0.8 (Fig. 13 (B)). D))
.

Next, input data y with a value of 1.2 is input. ．． When 1 is input,
Subtraction data with a value of -0.4 is obtained, and the predicted input value D with a value of 0
, is output, and in this case the switch means 45 is held in the off state, so that the value 0.8 is certain? Likeness data Δ
k is held in the latch circuit 44. On the other hand, when input data yk1 with a value of -1.7 is subsequently input, subtracted data with a value of 2.5 is obtained, a predicted input value D3 with a value of 1 is output, and the probability data Δk is The value is updated to 0.7.

As a result, the value 18 is changed from the human power data '1 ma+ to the value 1
．． It is possible to detect that the precoordination data D0 continues to have the value -1 and the value 1 until the second input data yk+1.

In this way, it is possible to sequentially detect the values of the brico data D■ based on the predicted input value D3. Comparison circuit 43
outputs the decoding result data D1 with a value of 1 when the certainty data Δk is greater than or equal to 0; however, when the certainty data Δk takes a negative value, it outputs the decoding result data with a value of -1. By outputting D, the rising and falling edges of the input data yk are detected based on the probability data Δk.

The data memory circuit 45 has 20 stages of shift register circuits connected in series, and is designed to temporarily store the data D, which is the result of decoding.

Further, the data memory circuit 45 converts the decoding result data D of logic levels "1" and "-1" into data of logic levels "1" and 'OJ, respectively, and then converts the data
The logic level is inverted based on the control signal S output from 6.

The control circuit 46 determines the transition of the precoder data DPI (FIG. 13(C)) based on the result of multiplying the decoding result data D1 output from the multiplication circuit 48 and the predicted input value D.
is detected, and a control signal Sc is output according to the detection result.

As a result, the data DI of the decoded result is inverted as necessary, and the precoded data is decoded. Further, the data memory circuit 45 is configured to connect an exclusive OR circuit to its output stage, and thereby performs arithmetic processing (1-D) on the decoded precode data and outputs the reproduced data DPI.
Convert to

In this way, the Viterbi decoding circuit 35 (36) decodes the input data by utilizing the (1-D) relationship between the preceding and succeeding data, thereby decoding the input data containing noise and having a low CN ratio. Even when decoding data, data with significantly fewer bit errors is decoded.

Furthermore, in this embodiment, the latch circuit 41 receives the output signal SEX2 of the exclusive OR circuit 26,
The probability data Δk is initialized to the value O at the timing when the output signal SEX2 rises.

If this causes a dropout, if the signal level partially decreases in variable speed playback mode, or if continuous input data is interrupted at the beginning of the digital video signal Da, audio signal DA, or sub data D SLIM, respectively. , after initializing the likelihood data Δk to the value 0, successive input data are decoded.

In practice, digital video signals D, I, audio signal DA and sub data D SU! Separately? When recording, not only when a dropout occurs between recording tracks, but also when the audio signal DA and sub data D3 are re-recorded separately using a technique such as overflow, the data is input to the Viterbi decoding circuit. Continuity of input data is lost.

In this case, in the Viterbi decoding circuit, if the continuity of input data is lost, a bit error will occur by decoding the input data that follows with incorrect certainty data. By initializing the value 0 to the value 0, it is possible to effectively avoid decoding the input data based on data with incorrect certainty.

Therefore, bit errors can be effectively avoided and the reproduced signal SIF can be reliably decoded. The selection circuit 49 is
Upon receiving the reproduced data output from the Viterbi decoding circuits 35 and 36, by sequentially switching the contacts, the data divided into even and odd series is returned to the original arrangement, and the reproduced data DPI (Fig. 3 (E)) is Output. On the other hand, the error detection and correction circuit 50 detects the reproduced data Dp
yr is received, detects bit errors, corrects the bit errors, and then separates data into audio signal SAPI and video signal data.

The data expansion circuit 52 receives the data of the video signal separated by the error detection and correction circuit 50, and expands the data in the opposite manner to the data compression circuit 4.

In this way, the video signal SVPI can be obtained via the digital-to-analog conversion circuit 54.

Incidentally, in this embodiment, the arithmetic processing circuit 20, the envelope detection circuits 2l, 23, the comparison circuits 22, 24, and the exclusive OR circuits 25, 28 operate on the data D, I, DA, D included in the reproduced signal SRF. The data detection circuit that detects the continuity of 3LII1 is to be monitored.

Furthermore, envelope detection circuits 2l, 23, comparison circuit 22
, 24 and the exclusive OR circuit 25 constitute a signal detection circuit that detects the signal Sp suppressed by the arithmetic processing circuit 20.

? Gl-5) Operation of the embodiment In the above structure, the video signal Sv is converted into a digital video signal Dv by the analog-to-digital conversion circuit 2, and then compressed into data D of about 25 [MBPS] by the data compression circuit 4. be done.

The compressed data DI is subjected to processing such as shuffling and addition of a code for error correction together with the audio signal D in the error correction circuit 6, and is converted into recording data D■ of 30 (MBPS). The recorded data DI10 is subjected to arithmetic processing according to equation (2) in the precode circuit 8 and converted into bricode data D, and added to the standard signal S of the Nycast frequency in the adder circuit 9.

As a result, on the magnetic tape 14, the reference signal S2
, one block of digital video signal DI, reference signal S
,, 1 block of audio signal DA% reference signal SP,
Sub data D! IJIs reference signal S. ．． Signals are recorded in this order to form a recording track.

On the other hand, from the magnetic heads 16A and 16B? The reproduced signal S■ is input to an amplifier circuit 18 and an equalizer circuit 19.
The signal is input to the analog-to-digital conversion circuit 29 via the arithmetic processing circuit 20, and is converted into input data y-ray at the rising and falling periods of the signal levels of the reproduced signals S and IF.

At this time, the reproduced signal SIF and output signal S, which are input and output signals of the arithmetic processing circuit 20, are transmitted to the envelope detection circuit 21.
and 23, respectively, and the resulting envelope detection signals SIN■ and S! ,1vt
is output to the exclusive OR circuit 25 via the comparison circuits 22 and 24.

As a result, the arithmetic processing circuit 20
The suppressed portion of the reference signal SP is detected by the arithmetic processing, and thereby the beginning of each data recorded on the magnetic tape can be detected.

This detection result S,■ is output to the PLL circuit 26,
As a result, a reproduction clock signal SCKla is generated in the PLL circuit 26 based on the reference signal S.

? Furthermore, in a similar manner, the timing of scanning the recording track by the magnetic heads 16A and 16B is detected based on the detection results S, and the reference pulse signal is used as a reference, whereby the reproduced signal SIF is sequentially processed.

On the other hand, the input data y. is divided into an even number series and an odd number series by the selection circuit 30, and then is given to the Viterbi decoding circuits 35 and 36, whereby the input data yk is decoded into reproduced data. At this time, in addition to the beginning of each data, the drop The likelihood data Δk is initialized in the out part and in the part where the signal level locally decreases in the variable speed playback mode, so as to effectively avoid bit errors. The reproduced data is returned to its original arrangement before being divided into even and odd series in the selection circuit 49, thereby obtaining reproduced data DPII. The reproduced data D■ is sequentially passed through an error detection and correction circuit 50, a data decompression circuit 52, and a digital-to-analog conversion circuit 54, and is converted into a video signal SVPI in the opposite manner to that at the time of recording. Gl-6) Effects of the Example According to the structure described above, the signal component suppressed by the arithmetic processing circuit 20 is detected, and the probability is determined based on the detection result and the detection result of the signal level of the reproduced signal S■. data Δk
By initializing the data, it is possible to effectively avoid bit a loss when data continuity is lost.

(G2) Second Embodiment FIG. 20, in which parts corresponding to those in FIG. 1 are denoted by the same reference numerals, shows a second embodiment.
The beginning of the data is detected based on the input data yk output from 9.

That is, the comparison circuit 60 is configured to output the comparison result between the input data y5 and a predetermined reference level to the signal processing circuit 62, and thereby, a certain portion of the signal suppressed by the arithmetic processing circuit 20 is initially removed by dropout or the like. It is detected along with the portion where the signal level has decreased.

On the other hand, the signal processing circuit 62 outputs a switch? Referring to the pulse signal SWP, the reference switching pulse signal RF is determined from the comparison result of the comparator circuit 60, in which the signal level rises at the beginning of the digital video signal Dv, and then falls at the time ξ when the sub data Ds■ ends.
Create SWP.

Furthermore, the signal processing circuit 62 is configured to initialize probability data Δk of the Viterbi decoding circuits 35 and 36 at the beginning and dropout of data based on the output signal of the comparison circuit 60.

Thus, according to the structure shown in FIG. 20, based on the input data yk output from the analog-to-digital conversion circuit 29, a certain portion of the signal suppressed by the arithmetic processing circuit 20 is detected from the beginning together with a portion where the signal level has decreased. However, even if the certainty data Δk is initialized based on the detection result, the same effect as in the first embodiment can be obtained. (G3) Third Embodiment FIG. 21, in which parts corresponding to those in FIG. This is what I did. That is, the tone decoder circuit 70 receives the reproduced signal SilF
A certain portion of the signal at the Nycast frequency is extracted from the source and its signal level is detected, and thereby the reference signal S
The presence or absence of P is detected.

Thus, according to the configuration shown in FIG. 22, even if a portion of the signal at the Nycast frequency is directly detected instead of detecting a portion of the signal suppressed by the arithmetic processing circuit 20, the beginning of the data can be detected. Therefore, the same effects as in the first embodiment can be obtained.

(G4) Other embodiments In the above-mentioned embodiments, the input data VMS)'k*1, . . . are decoded using the Viterbi decoding circuit 35 (36) to which Ferguson's algorithm is applied However, the present invention is not limited to this, and can be widely applied to various Viterbi decoding circuits. can.

That is, as shown in FIG. 22, in a general Viterbi decoding circuit, when obtaining a decoding result for one piece of sequential data (represented by symbol d8), the data d. The probability of reaching d is divided into the case of going through the previous value l and the case of going through the previous value - 1, and when the difference is large, it is determined that data d8 is likely and output. It is being done. Therefore, the probability is formed by fIl←ゝ, which represents the probability of passing through the previous value l, and fm(1), which represents the probability of passing through the previous value - 1. Bit errors can be effectively avoided by initializing the data Δk when data continuity is lost.

Furthermore, in the above-described embodiment, a case has been described in which the magnetic heads are arranged on the rotating drum at angular intervals of 180 degrees to sequentially and alternately obtain the reproduction signal S■, but the present invention is not limited to this. It can be widely applied, such as when two sets of magnetic heads are disposed close to each other on the top of the magnetic head, and reproduction signals S2 are simultaneously obtained from two recording tracks.

In particular, when the reproduction signal SjIF is intermittently obtained from two recording tracks at the same time, it is inevitable that the continuity of data between the recording tracks will be impaired, and in this case, the probability data Δk should be initialized. This can reduce bit errors.

Furthermore, even when magnetic heads are placed adjacent to each other, if a certain portion of the suppressed signal is detected by the arithmetic processing circuit, the beginning of the data can be detected with high precision, and the data can be reliably reproduced. Further, in the above-described embodiments, a case was described in which a digital video signal was recorded and reproduced, but the present invention is not limited to this, and can be widely applied to cases in which various digital signals are reproduced.

Further, in the above-described embodiment, a case was described in which data recorded on a magnetic tape is reproduced, but the present invention is not limited to magnetic tapes, but can be applied to a wide range of magnetic reproducing apparatuses using magnetic recording media. Effects of the Invention As described above, according to the first invention, when the continuity of data is impaired, the certainty data Δ of the Viterbi decoding circuit
By initializing k, it is possible to effectively avoid bit errors and obtain a magnetic reproducing device that can reliably reproduce data. Furthermore, according to the second invention, by detecting a certain portion of the signal suppressed by the arithmetic processing circuit,
The beginning of the data can be detected with high accuracy, and thus the certainty data Δ of the Viterbi decoding circuit can be detected as needed.
By initializing k and controlling the PLL circuit,
A magnetic reproducing device that can reliably reproduce data can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a video table recorder according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing the data structure, FIG. 3 is a signal waveform diagram for explaining the operation of the video table recorder, and FIG. Figure 4 is a block diagram showing the bricode circuit.
Fig. 5 is a signal waveform diagram showing the processing of the reproduced signal, Fig. 6 is a block diagram showing the arithmetic processing circuit, Fig. 7 is a signal waveform diagram to explain dropout detection, and Fig. 8 is a signal waveform diagram showing the variable speed playback mode. FIGS. 9 and 10 are diagrams for explaining the operation of the arithmetic processing circuit. FIGS. 11 and 12 are block diagrams showing an equivalent circuit of the magnetic recording and reproducing system. FIG. Diagrams for explaining the operation of the Viterbi decoding circuit, FIG. 14 is a block diagram showing the Viterbi decoding circuit, and FIG.
- Fig. 19 is a diagram for explaining the operation, Fig. 20 is a block diagram showing the second embodiment, Fig. 21 is a block diagram showing the third embodiment, and Fig. 22 is a diagram showing other embodiments. FIG. 23 is a characteristic curve diagram for explaining the recording/reproducing system, and FIG. 24 is a characteristic curve diagram for explaining the partial response system. 1...Video table recorder, 8...
Precode circuit, 14...Magnetic tape, 20.
... Arithmetic processing circuit, 2123 ... Envelope detection circuit, 21, 24, 40, 43, 60 ...
... Comparison circuit, 29 ... Analog-digital conversion circuit, 35, 36 ... Viterbi decoding circuit. tSelf-image trauma's di-7 lecture' 2 Figure 4 Words La L Tewota Figure 3 Arithmetic processing Figure 6 Insertion of Dorotsu out Figure 7 /! Sanskritization of raw signals Fig. 8 Arithmetic processing Fig. 9 A High number system Da''j's Nu&Deri Fig. 10 Birth energy record $F Raw ice enjoyment fb circuit Fig. 11 Viterbi's number cycle crossing operation Fig. 13 f) Case 8I) Transition Fig. 16 f) Saiai Tsuki 1shi Fig. 17

Claims (2)

[Claims] (1) In a magnetic reproducing device configured to reproduce predetermined data recorded on a magnetic recording medium using a partial response method, a data detection circuit detects continuity of data included in a reproduced signal; A magnetic reproducing apparatus comprising: a Viterbi decoding circuit configured to decode the reproduced signal and initialize likelihood data based on the detection result of the data detection circuit. (2) In a magnetic reproducing device that uses the partial response method to reproduce predetermined data recorded on a magnetic recording medium, an arithmetic processing circuit that performs the arithmetic processing (1-D) on the reproduced signal; and a signal detection circuit that detects the signal component suppressed by the arithmetic processing circuit.