JPH03159405A - Amplifier circuit - Google Patents

Abstract

PURPOSE:To hold the advantageous characteristic of cascade connection while it is realized by means of a simple layout by supplying the gate potential of an FET in cascade connection from the intermediate potential of a level shift stage being a prestage. CONSTITUTION:The level shift stage is constituted of the n-number of diodes D1-Dn which are in cascade connection in a forward direction with respect to a current. On the other hand, an amplifier stage is composed of FETQ1- FETQ3. The gate of FETQ2 is connected to a connection point between the diodes D3 and D4 constituting the level shift stage. Since a bias voltage advantageous to the gate of cascade FET can be supplied without separately providing a power source with such constitution, the scale of a circuit is prevented from being enlarged and the layout is prevented from becoming complicated even if a differential amplifier is constituted and is multistage-connected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to amplifier circuits. More specifically, the present invention provides a semiconductor integrated circuit including a level shifter configured with a plurality of voltage drop elements such as diodes and/or resistors, and an amplification stage configured with at least one pair of cascode-connected FETs. Concerning new configurations of circuits.

In a semiconductor integrated circuit configured using conventional technology FET,
A cascode connection is a configuration of an amplifier circuit used particularly for the purpose of improving gain.

FIG. 3 is a diagram showing a typical configuration of an amplifier circuit configured by such a cascode connection.

As shown in the figure, the amplifier circuit with cascode connection is
FETQ. , Q2 and Q3. Here, the FET Q3 connected to the highest voltage side has its gate and source short-circuited and functions as a load element. On the other hand, Ql connected to the lowest voltage side has its gate connected to the input from the previous stage.

In addition, an independent power supply V is connected to the gate of FETQ2.

A bias voltage is supplied from FETQ and Q2, and FETQ and Q2 are connected in cascode.

In the amplifier circuit configured in this way, an input FETQ receives an input signal from the previous stage, and a cascode connection FETQ2.
It is assumed that both operate in the saturated region. Therefore, when the input FET and the cascode FET are configured with FETs with the same characteristics, the gate of the cascode FETQ2 whose gate is grounded in an alternating current manner is connected to the input FETQ.
．． A potential shifted several volts higher than the input potential is applied.

In the cascode-connected amplifier circuit configured in this way, the gate is terminated with low AC impedance, thereby suppressing the feedback capacitance seen from the input side FET and having the effect of widening the band.

Problems to be Solved by the Invention By the way, when designing an amplifier circuit using the cascode connection as described above, the DC bias voltage applied to the gate of the cascode FET Q2 may be generated using an independently prepared power supply circuit or a resistance element. It is supplied from a dedicated potential generated by a resistive divider circuit. Therefore, it was inevitable that the circuit for generating this bias voltage would increase the size of the circuit.

Furthermore, when multiple cascode amplifier stages are connected, the aforementioned DC bias potential must be supplied to multiple gates within the integrated circuit, so the pattern layout, especially when integrated, is extremely complex. Become. Furthermore, the cascode amplification stage shown in Figure 3 is a single-ended one, but if this is configured as a differential power scode amplification stage, the pattern layout becomes even more complex, and an amplifier circuit using cascode connection is used. This is a major obstacle when it comes to doing so.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a novel amplifier circuit configuration that can solve the above-mentioned problems of the prior art and can be realized with a simpler layout while retaining the advantageous features of the cascode connection.

Means for solving the problem, that is, according to the present invention, includes a level shift stage having an input coupled to one end and comprising a plurality of voltage drop elements connected in series, and an output of the level shifter as an input signal. In a circuit including an amplification stage configured by cascode-connecting a first FET to which a bias voltage is applied to the gate and a second FET to which a bias voltage is applied to the gate, the gate of the second FET is connected to the level shifter. It is connected to a node in the middle of a plurality of voltage drop elements constituting a stage, and is configured such that the intermediate potential of the level shift stage is applied as a bias potential to the gate of the second FET. An amplification circuit with features is provided.

Operation The amplifier circuit according to the present invention has a cascode-connected FET, especially in a cascode amplification stage including a level shift stage at the front stage.
Its main feature is that the gate potential of is supplied from the intermediate potential of the preceding stage level shift }&. That is, in the amplifier circuit according to the present invention, an intermediate potential based on the modulation voltage of the previous stage is applied to the gate of the cascode-connected FET.

Therefore, in the amplifier circuit according to the present invention, a special power supply circuit for generating the gate potential is not required, and the gate voltage is supplied from the level shift stage arranged adjacent to the amplifier stage due to the layout. The wiring for supplying the gate voltage is very short and requires only a simple pattern.

The configuration of the amplifier circuit according to the present invention is suitable for GaAsME, in which a level shift circuit is often connected to the input side.
It can be applied particularly advantageously in integrated circuits using S FETs. Moreover, it is particularly advantageous in a multi-stage connection configuration formed by repeating a large number of circuits that combine an amplification stage and a level shift stage.

Hereinafter, the present invention will be described in more detail with reference to the drawings, but the following disclosure is only one embodiment of the present invention, and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 2 is a circuit diagram showing a conventional configuration example of an amplifier circuit using a cascode connection and having a level shift stage at the front stage.

As shown in the figure, this circuit consists of n diodes D1
~Do is connected in series in the forward direction with respect to the current, and the level shift stage is connected to the low voltage power supply V, via the current source, and the FE
It is composed of an amplification stage composed of TQ, .about.FETQ3.

Here, FETQ3 is used as a nonlinear resistive load by shorting its gate and source.

Also, FETQ. and Q2 are connected in cascode, and the output of the level shift stage is input to the gate of FETQ, the bias voltage is supplied to the gate of FETQ2 from an independent power supply v0, and the output is connected to the drain of FETQ2 and FETQ3. is extracted from the connection point with the source. Although the power supply Vc is indicated by a single symbol in FIG. 2, it is actually constituted by a resistor divider circuit or the like consisting of a plurality of elements.

Such a conventional amplifier circuit can be constructed relatively easily if only one circuit is used as shown in FIG. However, if this is configured as a differential amplifier, or if it is configured as a multiple amplifier, the power supply V
, or wires for supplying bias power must be routed.

FIG. 1 shows an example of the configuration of an amplifier circuit constructed according to the present invention, and in contrast to FIG. 2, it is basically composed of a level shift stage and an amplification stage of the same construction.

That is, the level shift stage is composed of n diodes D1 to D, , connected in series in the forward direction with respect to the current, while the amplification stage is composed of F E T Q. ,~FE
It is composed of TQ3.

However, the gate of FETQ2 is connected to the connection point between diodes D3 and D forming the level shift stage.

Therefore, the diode that monitors this level shift stage is
Assuming it is a GaAs Schottky diode, the FET
The gate of Q2 has a voltage of about 2.
An in-phase voltage shifted to the high voltage side of 2V is applied as a bias voltage.

Furthermore, FETQ. When the diodes D1, D2, and D3 inserted between the gate of FET Q2 and the gate of FET Q2 are GaAs Schottky diodes, it is preferable that the number of diodes is 2 to 3 or more.

With this configuration, an effective bias voltage can be supplied to the gate of the cascode FET without providing a separate power supply, so the scale of the circuit can be expanded even when configuring a differential amplifier or connecting multiple stages. The layout will not become complicated.

Effects of the Invention As explained above, the amplifier circuit according to the present invention does not require a special power supply circuit for generating the gate potential of the cascode FET, and the level shift stage arranged adjacent to the amplifier stage due to the layout. Since the gate voltage is supplied from the gate, the wiring for supplying the gate voltage is very short and a simple pattern is sufficient.

Therefore, even when using a differential configuration or connecting in multiple stages, the scale of the circuit does not increase, and the layout is very easy.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the basic configuration of an amplifier circuit according to the present invention, and FIGS. 2 and 3 are circuit diagrams showing typical configurations of conventional amplifier circuits. [Main reference symbols] Q,, Q2, Q3...FET, D1~D0...Diode

Claims (3)

[Claims] (1) A level shift stage having an input coupled to one end and configured by connecting a plurality of voltage drop elements in series;
FET and a second FET to which a bias voltage is applied to the gate are connected in cascode. 1. An amplifier circuit connected to a node in the middle of a drop element, and configured such that an intermediate potential of the level shift stage is applied as a bias potential to the gate of the second FET. (2) The amplifier circuit according to claim 1, wherein the voltage drop element constituting the level shift stage is a diode based on GaAs. (3) The amplifier circuit according to claim 1 or 2, wherein the first and second FETs are FETs based on GaAs.