JPH03156563A - Digital information processor - Google Patents

Abstract

PURPOSE:To obtain an information processor equipped with a learning function by a digital circuit by executing learning on the stage of learning by using a selector circuit and a combining circuit and generating permutation data at the stage of an information processing based on a learnt select signal. CONSTITUTION:On the stage of learning, an external input signal 101 is held until an output 106 is settled at a fixed value in a latch 111. In a select circuit 112, the suitable permutation of an output 103 from the latch 111 is selected according to a select signal 105 of a control circuit 114. An output 104 from the circuit 112 receives suitable conversion in a combining circuit 113 and is outputted as an output signal 106 afterwards. When an input 108 from a comparator 115 shows dissidence, the circuit 114 outputs the select signal. On the stage of the information processing, the signal 101 is held for fixed time in the latch 111 and outputted as an output 103. According to a select signal 105 determined by the circuit 114 at the time of learning, the output 103 is passed through the circuit 112 and converted to permutation data 104. The data 104 receives suitable conversion by the circuit 113 and are outputted as the output signal 106 afterwards.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a digital information processing device with a learning function.a.Prior art:For example, as an information processing device with a learning function,
Here are some examples of neural network learning algorithms using pack propagation (& For example, parallel distributed processing)
ButtedProcessing (MIT pr
ess)), so I will briefly explain the main points using Figure 2. 4. A neural network learning algorithm using pack propagation () The basic idea is to change the connection between neurons on the network. This changing operation is called learning, and the expected value is defined as the teacher signal. In Figure 2, 201
is an external input signal 202 is an expected value signal; 203 is an output signal of a neural network; 204 is, for example, a three-layer neural network; and 2.05 is one neuron in the neural network. The error function (E,) between the actual output 203 (oa'') of each neuron corresponding to the output layer of the neural network and the expected value signal 202 (tiJ) is defined as follows.

E p-1/2Σ(t*joaj) ” ・(1
) (oej is the actual output value of each neuron) ・(2
) (tpj is the expected value of each neuron) (3) The pack propagation learning algorithm uses the steepest descent method to change the connection method between neurons, that is, the connection coefficient, so as to minimize this error function. . This makes it possible to bring the actual output value of each neuron closer to the expected value, and learning is completed. At this time, each neuron (for example, 205) performs the following threshold processing.

oe+=f(ΣWIIXI−θ1)j・(4)f (
t)=1/ (1+exp (-t))・(5)
(s i gmo id function) W J l: Coupling coefficient of neuron (j) xl: Human power value from neuron (i) to neuron (j) θ1: Threshold value of neuron (j) Repeat this procedure Therefore, the coupling coefficient wji of the neuron is the expected value t pj when the output opj is the teacher signal
(Neural Net) 20
1 increase compared to 4 Coupling coefficient wjiE1g It is difficult to realize this flexible change using a digital circuit using a semiconductor element. Conventionally, the coupling coefficient wjiE1g was realized by software or by using an analog circuit such as an optical element. It was realized with hardware.

In addition to this, there are perceptrons and other information processing devices with learning functions.All of these were realized using software power\analog circuits using optical elements, etc.9 inventions are trying to solve the problem. As mentioned in the section on conventional technology, in order to realize an information processing device with a learning function, analog circuits such as software or optical devices are used, and semiconductor devices, which are superior in terms of integration and reliability, are used. There is no one that has been realized using digital circuits.The object of the present invention is to realize a digital information processing device having a learning function using digital circuits.

Means for Solving the Problems The present invention is directed to solving the above problems. A selection circuit that selects by allowing overlap on the path from input to output and a combination circuit that performs upward mapping from the output of the selection circuit are installed. By further comprising a control circuit that feeds back the comparison result between the output and the expected value to the selection circuit, an information processing device having a learning function can be realized using a digital circuit. Action (, t, (1) learning stage (2) information processing stage) In the learning stage of (1), the selector circuit allows duplication from m input data and selects n pieces. Generate appropriate permutation data and input it to the combinational circuit.The combinational circuit generates data from n permutation data.In addition to this data 1-2, along with expected value signals manually input from the outside. Even if the information is input to the comparison circuit and inputted manually to the control circuit, the control circuit will switch the select signal based on this information if the output of the combinational circuit and the expected value are different.By repeating this, the output of the combinational circuit and the expected value will be changed. The values match and learning ends, but next!'-, (2)
At the information processing stage of <! Based on the select signal learned in the learning stage (1), n pieces of specific permutation data are generated from m pieces of manual data, which are input to the combinational circuit LA and k outputs are obtained.Example 1: Digital trust in one embodiment of the present invention
1 is a latch that receives the input signal 101, 102 is a clock signal input to the latch 111, and 103 is a 3-bit output 112 of the latch 111, which is a 5-bit permutation from the 3-bit signal 103 by a select signal 105, allowing overlap. 104 is the 5-bit output j'J of the select circuit 112, l13 is the combinational same block that inputs the output signal 104 from the select circuit 112, 106 is the 1-bit output signal from the combinational circuit 113 115 The comparison circuit 108 which receives the output 106 and the expected value signal 107 from the outside is the comparison circuit 11.
Output from 5 114 is output 108 and selected to select circuit 112, 301 is 243 shift registers, 108 is input from the comparison circuit fi 1
05 is the output of the 243 shift registers, 304 is an enable signal for shifting the contents of the shift registers,
The output 105 is input to the select circuit l12 as a select signal. Here, among the 243 shift registers, the register to which the signal 108 from the comparator circuit is input is the lowest register.In the initial state of learning, 243
The lowest register among the shift registers is set to l, and the other registers are reset to O. When learning starts, the input 10 from the comparator circuit is
When 8 indicates a mismatch, 0 is input to the lowest register, the enable signal 304 is turned on, and the contents of the register are set to 1.
Even if the bit is shifted, this is human power 108 from the comparison circuit.
is repeated until it indicates a mismatch, and ends when the output 108 from the comparator circuit no longer indicates a mismatch.In other words, only one bit of the output 105 of the shift register is always 1.This means that the select circuit 1
Only 1 bit of the select signal 105 to 12 is H.
The operation of the embodiment of the present invention, which corresponds to showing IGH, consists of two stages: (1) learning stage, and (2) information processing stage. First, the operation in the learning stage (1) will be explained. External input signal 101 is held by latch 111 until output 106 settles to a constant value. Select circuit 1
In 12, an appropriate permutation of 5 bits is selected from the 3 bits of the output 103 from the latch 111 by the select signal 105 of the control circuit 114, allowing duplication.
= Select one from 243 combinations Output 104 from select circuit 112 is combination circuit 1
After undergoing some suitable transformation by 13, the output signal 10
At the same time, the output signal 106 is inputted to the comparison circuit 115 together with the expected value signal 107, and the comparison result 108 is inputted to the control circuit 114.In the control circuit 114, if the input 108 from the comparison circuit 115 indicates a mismatch. Based on the above explanation, the next select signal is output. By repeating this process, the select signal is switched one after another. When the output signal 106 and the expected value signal 107 match, learning is completed. This section describes the operation of the processing stages.
The external human power 101 is held for a certain period of time by a latch 111 and output as a 3-bit output 103.
Data 1 is converted into specific 5-bit permutation data 104 through the select circuit 112 by a certain select signal 105 determined by the control circuit 114 during learning.
04 is subjected to a certain appropriate transformation by the combinational circuit 113, and then outputted as the output signal 106 to obtain the fourth order.This generally proves that learning is possible according to the present invention. The purpose of such a system is to have the system find its own way (by means of an algorithm) to a given relationship (input signal to output signal); the proof of this is given below.

First, input data 103 to the select circuit, output data 104 of the select circuit, and output data 1 of the combinational circuit.
06 and expected value data 107 are defined as follows: Input to the select circuit...X Output of the select circuit...Y Output of the combinational circuit...Z Expected value...D (X is the m-th vector vector k Y is n-th pect/kZ, D
i! Also, let the conversion from X to Y, that is, the selection condition of the select circuit, be the function f + (0≦i≦S; where S is an appropriate integer), and the conversion from Y to Z, that is, the combination. The logic of the circuit is expressed as a function g.In this case, the function f+ represents the selection condition of a selection circuit that outputs duplicate permutations.
A set of functions that express all mapping relations from a certain input X to an output Y.
Any Y can be output by selecting There are more than one. FIG. 4 shows the basic algorithm of the present invention. From the properties of the functions fi and g, for a certain X, Z
= D. Even if there exists at least one Y, and there is a l that outputs such Y, then it outputs the same expected value dED for a certain xlEX and a value x2EX close to it. We show that there exists a certain value i and that it can be determined by the algorithm. This is essentially due to the nature of the function g (above), that is, it is a function representing a many-to-l mapping. Now, if z = d for a certain zEZ, then If it is sufficiently thicker, there are multiple y E Y that output z. Let G be the set of such y, and i that outputs yEG like this for 4xl is an element of G from the property of the function fi. There are as many as
Similarly, for X2, output yEG like this i
There are as many elements of G as there are elements of G, and such a set is 12 and a
Now let I be the entire set of i. As mentioned above, the larger the ratio of n to k, the greater the number of elements in G. Therefore, there may be common elements between il and 12. Assuming that there is a common element like this, let the set be A
shall be. Figure 5 shows the relationship between sets ■, 11, 12, and A. By the algorithm shown in Fig. 4, i=
Starting from 0, if a certain 1=i0 becomes 2=d, then
Next, if we manually calculate x2, starting from 1=io, and get z=d at a certain 1=il, at this time, if we manually calculate x1, it does not necessarily mean that z=d. There is no element of (~ Therefore, if the set A
If exists, by repeating this,
Although it is possible to determine l that is definitely iEA, therefore,
It is possible to output the same expected value when a similar value is given as input to a certain i. Here,
As stated above, this is clearly a valid assumption.Also, the presence or absence of set A depends on the function g, and its number of elements is n, depends on k. In other words, the learning speed for such problems is 1 - for boat fishing, n depends on k, Ln
The larger is and the smaller k is, the easier it is to converge (°C. However, if the function g is inappropriate, the set A may not exist. From the above description, the algorithm in Figure 4 can be used to convert the human input signal to the output signal. By having the system find its own method, a learning function has been realized.A Effects of the Invention As stated above, according to the present invention, a semiconductor element with excellent integration and reliability is achieved. It is possible to construct an information processing device with a learning function using a digital circuit using

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a digital information processing device according to an embodiment of the present invention. FIG. 2 is a configuration diagram showing a neural network. FIG. 3 is a circuit diagram showing an example of the control circuit shown in FIG. 1. Figure 5 shows the basic algorithm of the invention. This is a diagram showing the relationship between i2 and A. 101... External input signal 102... Clock signal 1
03...Latch output 104...Select circuit output 105...Select signal q106...External output 10
7... Expected value signal, 108... Comparison circuit output 1
11...Latch, 112...Select same section 11
3...Combination time i 114...Control time!
115... Comparison time i 301... i shift registers 304... Enable signal

Claims (1)

[Claims] A select circuit that selects n permutations from m inputs from the outside while allowing duplication, and a number k smaller than n, inputs the n outputs of the select circuit, and outputs k values. a combinational circuit that performs upward mapping from n data to k data, and a comparison circuit that compares the k outputs of the combinational circuit with k expected value signals from the outside; A digital information processing device comprising: a control circuit that receives the output of the comparison circuit as an input and determines an output condition of the selection circuit.