JPH03155597A - Reverberation attaching device - Google Patents

Abstract

PURPOSE:To reproduce a reverberation tone in a natural field with fidelity by changing filter characteristic to be attached on the reverberation tone in point of time. CONSTITUTION:The device is equipped with a frequency characteristic control means 10 to attach the filter characteristic on an input signal itself or a generated reverberation tone, and a filter characteristic varying means 11 to attach temporal change on the filter characteristic. For example, the filter characteristic is attached on the input signal at the frequency characteristic circuit 10. The filter characteristic is variably controlled in point of time with the filter characteristic varying means 11. The output of the frequency characteristic control circuit 10 is inputted to a reverberation attaching circuit 12. Thereby, it is possible to reproduce the reverberation tone in the natural field with fidelity by changing the filter characteristic in point of time so as to attenuate a high- pass area earlier in the reverberation attaching device.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a reverberation sound adding device for artificially adding reverberation to a music signal, etc. This is what I did.

[Conventional technology]

When artificially adding reverberation to music signals, etc., the most direct electronic method is to generate signals with various time delays from the direct sound, corresponding to the impulse response in an acoustic space such as a virtual hall. This is a method of expressing it as a superposition of . That is, as shown in FIG. 2, the impulse response of the virtual acoustic space has a delay time τI with respect to the direct sound.
and level g, (1-1,2,...,n), then input the delay time τl and level gI as coefficient parameters (reflected sound parameters). By creating a reflected sound sequence for each sample of the signal and superimposing the reflected sounds of each sample at the same time (this operation of multiplying the delayed signal by a gain and adding it is called a convolution operation). , a reverberant sound is created.

As shown in FIG. 3, this superposition is carried out by inputting each sample value of the input signal to a shift register 1 having a multi-tap while sequentially shifting it every sampling period τ0.
Within the sampling period τ0, the delay time is 1 or more.

Delayed signals x1 to x of each sample from each tap corresponding to
o are respectively output, amplifiers 2-1 to 2-n give gains g1 to gn to these, and adder 3 adds them, thereby creating one sample of the reverberant signal. and,
This operation is performed using the sampling period τ of the input signal. By repeating each step, a series of reverberation signals is created.

In addition to the method using the impulse response described above, there are various devices that artificially add reverberation.

[Problem to be solved by the invention]

Reverberation signals created by conventional reverberation adding devices do not take frequency characteristics into consideration, but in nature, the frequency characteristics of reverberation change over time. In other words, in the natural world, high-frequency components of reverberation attenuate quickly, and over time, only low-frequency components become available. Therefore, even in the reverberation addition described above,
If the frequency characteristics of the reverberant signal to be created can be temporally controlled, more natural reverberant sound can be created.

In addition to such purposes, it would be convenient if the frequency characteristics of reverberant sound could be temporally controlled for purposes such as obtaining special effects.

The present invention aims to solve the problems in the conventional techniques and provide a reverberation adding device that can temporally control the frequency characteristics of reverberant sound.

[Means to solve the problem]

A first invention of this application is a reverberation adding device for creating a residual sound of an input signal, including a frequency characteristic control means for adding filter characteristics to the input signal itself or the created reverberation sound;
The filter includes a filter characteristic control means for adding a temporal change to the filter characteristic.

Further, a second invention of this application is a reverberation adding device that performs data calculation on input signal data based on predetermined coefficient data to create reverberant sound data of the input signal, in which the input signal before creating reverberant sound The filter characteristic control means adds a temporal change to the residual column after creating data or reverberant sound.

[For production]

According to the first invention, by temporally changing the filter characteristics in the reverberation adding device so that the high frequency range attenuates quickly, it is possible to faithfully reproduce reverberant sound in the natural world. Furthermore, various special effects can be obtained by setting various temporal changes in the filter characteristics.

Further, according to the second invention, in the reverberation adding device that performs data calculation on input signal data based on predetermined coefficient data to create reverberation sound data of the input signal, the temporally changing filter characteristics are obtained. be able to.

〔Example〕

An embodiment will be described in which the present invention is applied to a reverberation adding device that performs convolution operations using impulse responses as coefficient parameters to create reverberant sound of an input signal. Here, we will explain data before creating reverberant sound, data after creating reverberant sound, or cases in which filter characteristics are added to the coefficient parameters and temporal changes are added to the filter characteristics. do.

(Example 1) A first example of the present invention is shown in FIG. This is to give frequency-temporality to input data before creating a reverberant signal.

In FIG. 1, an input signal is given a filter characteristic by a frequency characteristic control circuit 10. In FIG. This filter characteristic is variably controlled over time by filter characteristic control means 11. The output of the frequency characteristic control circuit 10 is input to the reverberation adding circuit 12. The reverberation addition circuit 12 creates a reverberation signal for each sample of the input signal based on the impulse response parameters (parameters related to delay time and level) stored in the coefficient memory 14, and adds them by convolution operation. to create a series of reverberant signals (
(the calculation shown in FIG. 3 above). By variably controlling the filter characteristics of the frequency characteristic control circuit 10 over time, the reverberation adding circuit 12 outputs a reverberation signal to which a filter characteristic that changes over time is added.

(Example 2) A second example of the present invention is shown in FIG. This is a method in which filter characteristics are given to data after the reverberation signal is created.

In FIG. 4, an input signal is input to a reverberation adding circuit 12. In FIG. The reverberation adding circuit 12 creates a reverberation signal for each sample of the input signal based on the impulse response coefficient parameters stored in the coefficient memory 14, and
These are added by convolution to create a series of reverberant signals.

The reverberation signal output from the reverberation adding circuit 12 is given filter characteristics by the frequency characteristic control circuit 10. This filter characteristic is variably controlled over time by a filter characteristic control means.

(Embodiment 3) A third embodiment of the present invention is shown in FIG. This is a method in which filter characteristics are given to the coefficient parameters of an impulse response for creating a reverberant signal.

In the diagram m5, the impulse response coefficient parameters stored in the coefficient memory 14 are stored in the frequency characteristic control circuit 10.
The filter characteristics are given by . This filter characteristic is variably controlled over time by the filter characteristic control means 11. The reverberation addition circuit 12 creates a reverberation signal for each sample of the input signal based on the coefficient parameters to which the filter characteristics are applied, and adds these signals by convolution to create a series of reverberation signals.

Since the impulse response pattern and the filter characteristics are of the same dimension, the impulse response pattern is transformed by passing it through the frequency characteristic control circuit 10, and the convolution operation is performed using this transformed impulse response. A reverberant signal with filter characteristics can be obtained.

According to the embodiments shown in FIGS. 1, 4, and 5, when the input signal is interrupted, the filter characteristic band of the frequency characteristic control circuit 10 is changed in the lower frequency direction in accordance with the attenuation of the reverberant signal. By narrowing the range to , it is possible to quickly attenuate the high range, and it is possible to reproduce historical reverberations in the natural world. In addition to this, it can also be used to add special effects.

(Example of configuration of frequency characteristic control circuit 10) Example 14 of the frequency characteristic control circuit 10 in each of the above embodiments
An example is shown in Figure 6. This is a system in which two systems of filter circuits with different frequency characteristics are provided and the frequency characteristics are gradually switched by cross-fading them.

In FIG. 6, the input signal is branched into two systems A and B,
are input to filters 16 and 18, respectively. Filter 1
The frequency characteristics of 6.18 are set independently. The outputs of the filters 16.18 are multiplied by cross-fade coefficients x + y in multipliers 20.22, added together in an adder 24, and output. The coefficients x and y are set so that the coefficient y changes from 1 to 0 while the coefficient X changes from 0 to 61, for example, as shown in FIG. Therefore, at first, only the characteristics of the filter 16 are effective, but as time passes, the characteristics of the filter 16 gradually weaken, and the characteristics of the filter 18 begin to become effective, and eventually only the characteristics of the filter 18 become effective. In this way, the frequency characteristics can be switched continuously. For example, filter 1
6.18 are both low-pass filters, and the cutoff frequency of the filter 16 is set to a high frequency f1, and the cutoff frequency of the filter 16 is set to a low frequency f2, then the cutoff frequency gradually increases from ft to f2. A frequency characteristic that changes as follows can be obtained.

Moreover, if such switching is performed continuously, it is possible to change the frequency characteristics over a wide range.

FIG. 8 shows an example of this, in which the filter characteristics are alternately switched when the input is interrupted and the reverberant signal gradually attenuates. Here, as the filter characteristic, for example, the characteristic shown by ai in FIG. 9 is used. The coefficient X+y is 1 to 1, as shown in FIG.
It changes between 0 continuously and periodically, with x and y maintaining a mutually inverted relationship (x+y=1). As shown in FIG. 8, one filter characteristic is used continuously while the coefficient changes from 0 to 1 to 0, and when the coefficient attenuates to 0, it is switched to the next filter characteristic. That is, in the example of FIG. 8, when the input continues, x
-1, y=o, and the characteristics of the filter 16 on the A system side are utilized to set the characteristics of a, which has the highest cutoff frequency.

When the input is interrupted, the filter characteristic on the A system side remains a, and the value of coefficient X gradually attenuates to 1-0, and the filter characteristic on the B system side is set to b, which has a lower cutoff frequency than a. The value of the coefficient y gradually increases from 0 to 1. When the coefficient X becomes 0, the filter characteristic on the A system side is switched to C, which has a lower cutoff frequency than b. In this way, each time the values of coefficients x and y become 0 in A system and B system, the filter characteristics are sequentially switched to a, b, c, d, ..., i, with a lower cutoff frequency. As a result, it is possible to faithfully reproduce the characteristics of reverberant sound in the natural world, in which the high-frequency components of the reverberant signal attenuate quickly and the low-frequency components remain for a long time.

By the way, the filters 16 and 18 in FIG.
(Unite impulse response
: acyclic filter) and I I R (lnf'1nl
It can be configured with a digital filter such as a cyclic filter. An example of a second-order IIR type filter is shown in the first example.
Shown in Figure 0. This is a signal obtained by adding a coefficient (gain) Ao to the input signal by the multiplier 26, and a signal obtained by adding a coefficient (gain) Ao to the input signal by the delay element 27.
After delaying by one sampling period τ, the multiplier 28 calculates the coefficient A.
The adder 31 adds the signal added with 1 and the signal obtained by delaying the input signal by a period of 2τ with the delay element 27.29 and adding the coefficient A2 with the multiplier 30, and the output of the adder 31 is added with the period with the delay element 32 τ. The signal delayed and given a coefficient 81 by a multiplier 33 and the output of the adder 31 are processed by delay elements 32 and 34 at a period of 2τ. The signal delayed and given a coefficient B2 by the multiplier 35 is fed back to the adder 31.

In this circuit, (z) is obtained as the transfer function H between input and output. Coefficients A, A, A, B, B
The filter characteristics can be arbitrarily set by the value of 20 1 2 1 .

FIG. 11 shows an example of the configuration of the frequency characteristic control circuit 10 of FIG. 6 in which the filters 16 and 18 are FIR type filters. For example, as shown in FIG.
. is one sampling period τ with the delay element 40. Each multiplier 4
2... gives the coefficient a - a, and each al XO
=a20''0 is accumulated by 20 adder 44 (that is, by convolution operation)
The input signal xo is given low-pass filter characteristics. Filter characteristics are set by the values of coefficients a1 to a2°. In the circuit of Fig. 11, especially RA
This is achieved through program control using M. Note that each control signal used in the circuit of FIG.
As shown in the figure.

In FIG. 11, filter characteristic parameter memory 46
is the coefficient a − a + b tL that determines the frequency characteristic for each filter characteristic to be set (for example, the characteristics of a, b, ..., i in FIG. 9).
11-b, . . . , 11- (when filter characteristics are expressed by m sample points each) are stored in each address as shown in Table 1 below.

Table 1: Storage contents of filter characteristic parameter memory 46 The filter characteristic selection circuit 48 selects two filter characteristics from among the filter characteristics (a-i) stored in the filter characteristic parameter memory 46.

The data memory 50 has m+1 addresses, and updates the samples of the input signal in order from the addresses where the oldest samples are stored, and writes new samples. As a result, the data memory 50 always stores the past m from the present moment.
+1 samples are now stored.

The counter 52 instructs the write address of the data memory 50, and is counted up by the clock C1 generated every sampling period τ0 of the input signal, and when the count reaches m, the count is repeated from 0 again.

The counter 54 instructs successive addresses in the filter characteristic parameter memory 46 and data memory 50, and counts up from 0 to m in response to m+1 clocks C2 generated during the sampling period τ0 of the input signal. The value of the counter 52 is subtracted from the value of the counter 54 by a subtracter 56, and added to the data memory 50 as an address.

The data memory 50 is switched to the write mode by the clock C3 when the value of the counter 54 is 0, and is in the read mode when the count value is other than that.

Therefore, in the write mode, the value of the counter 52 is directly added to the data memory 50 as a write address,
A human sample is written to that address. After writing, the data memory 50 returns to the read mode, and the counter 54 is sequentially incremented by the clock C2. Then, the value of the counter 52 (address of the latest data) is subtracted in the subtracter 56, and the value of one sample before, two samples before, . The samples are sequentially read out within one sampling period τ0.

Further, the filter characteristic parameter memory 46 stores two filter characteristics selected by the filter characteristic selection circuit 48 from among the filter characteristics a-i shown in Table 1 (for example, the characteristics a and b) using the value of the counter 54 as an address. ) are sequentially output in parallel.

The output data of the data memory 50 is two systems A.

B, and multipliers 58 and 60 provide coefficients of the filter characteristics sequentially output from the filter characteristic parameter memory 46. Since the readout of the delay data and the readout of the filter characteristic coefficients are synchronized by the counter 54, the multipliers 58 and 60 provide coefficients corresponding to the delay data being read out.

The output data of the multiplier 58 is sent to the adder 62 and the register 64.
are accumulated sequentially in an accumulator consisting of, in a periodic manner. The total accumulated value of m data obtained within the period is latched into the register 66 by the clock C1. The accumulated value is in register 6
6, register 64 is reset by the inverted signal of clock C1 to prepare for accumulation in the next sampling period.

The output data of multiplier 60 is similarly processed.

As a result, the registers 66 and 72 output data in which the filter characteristics selected by the filter characteristics selection circuit 48 are added to the input signals, and these data are processed by the multipliers 74 and 76, where the cross-fade coefficients x and y are respectively adjusted. Granted.

The cross-fade parameter memory 78 has coefficients x, y
(See FIG. 7), for example, the values shown in Table 2 below are stored in each address.

Table 2: Storage contents of cross-fade parameter memory 78 When the counter 80 is triggered by the trigger signal TRG, it is counted up by the clock C4 having a cycle much longer than one sampling cycle τ0 of the input signal. This count value is added to the memory 78 as an address, and the coefficients x and y shown in Table 2 are sequentially read out. The output data of the multiplier 7476 is added by the adder 78,
The sampling period τ is the same as the input signal. is output.

In this way, the filter characteristics of the A system are sequentially switched to the filter characteristics of the B system.

Note that when the A system is completely switched to the B system (that is, when the value of the counter 80 becomes 10), if the counter 80 stops counting, the filter characteristics of the B system will continue to be utilized. It will be done.

Also, if the A system is completely switched to the B system, the A
By switching the system to another filter characteristic and switching the counter 80 to count down, it is possible to sequentially switch from the filter characteristic of the B system to the new filter characteristic of the A system.

Furthermore, when the value of the counter 80 falls to 0, the B system is switched to another filter characteristic, and if the counter 80 is switched to up-count, the A system's filter characteristic is switched to the B system's new filter characteristic. Can be done. In this way, switching of filter characteristics as shown in FIG. 8 is realized.

(Configuration examples of the reverberation adding circuit 12 and coefficient memory 4 in FIGS. 1 and 4) The embodiment shown in FIG. 1 (which gives filter characteristics to the input signal before adding reverberation) and the embodiment shown in FIG. The configuration example of the reverberation adding circuit 12 and the coefficient memory 4 applied to the reverberation adding circuit (which gives filter characteristics to the input signal after adding the reverberation) is shown in the first example.
Shown in Figure 4. The circuit shown in FIG. 14 realizes the principle of adding residual snow shown in FIG. 3 through program control using a RAM. Here, since there is a limit to the speed of convolution calculation that can be performed within one sampling period τθ to create a reverberant signal, the impulse response parameters (τ 1g1) to (τ 2g ) shown in Fig. 2 are
Rather than using all of n, the convolution operation is performed by selecting an area. In other words, when the input signal continues, the rear reverberation sound is masked, and there is no audible problem even if it is interrupted, so the parameters of the initial reverberation sound (τ, g)
A reverberant sound is created by convolution using only ~(τ 9g1)11 1 .

In addition, when the input signal is interrupted, the masking effect disappears, and if only the initial reverberation sound is used, the reverberation sound suddenly stops and feels unnatural. Therefore, the range of parameters to be used (τ
1g2) ~ (τl+1°g1+1), and even (τ 1
g3) to (τl+2°gD2) to obtain a natural reverberation sound from the early stage through the middle stage to the latter stage. Hereinafter, a convolution operation in which the area of parameters to be used is sequentially shifted to a lower level in this manner will be referred to as "adaptive" convolution. Incidentally, each control signal used in the circuit of FIG. 14 is shown in FIG. 15. In addition,
The clock C1 in FIG. 15 is the clock C1 in FIG.
(a signal generated every sampling period τ).

In FIG. 14, the input signal is temporarily stored in the flash memory 82. The flash memory 82 stores the input signal for a period of about several tens of milliseconds, which is necessary to detect whether the input signal continues or is interrupted in order to determine whether to shift to the adaptive mode.

The counter 80 provides a write address to the pre-memory 82, and is incremented by a clock c1 every cycle τ0.

The counter 86 provides a read address to the pre-memory 82, and is counted up by the clock C8 and reads out data at each address in the pre-memory 82 within a period τθ. The counter 86 has a period τ according to the clock C4.
It is reset to the beginning of 0.

The pre-memory 82 is clocked at a period τ by the clock C9. It is switched to write mode once at the end of the process.

At this time, the counter 86 has been reset, the value of the counter 80 is output as is, and a new sample of the input signal is written to the address of the pre-memory 82 (the storage address of the oldest data) indicated by the value.

At timings other than clock C9, the prememory 82 is in the read mode, and the value obtained by subtracting the value of the counter 86 from the value of the counter 80 is given as a read address by the subtracter 84, and the stored contents of the prememory 82 are read in one sampling period. τ. are read out sequentially within

The coefficient memory 14 stores impulse response coefficient parameters at each address as shown in Table 3 below.

Note that, for convenience, the delay time data τ1 is one sampling period τ of the input signal. It is remembered in the form of how many personalities it corresponds to. (It is also possible to store this in real time form, but in that case a separate interface configuration with timing on the circuit is required.

Data memory 88 stores samples of the input signal to create a residual signal.

The counter 9o provides a write address to the data memory 88, and every sampling period τ0 of the input signal (
It is incremented by this clock C1. Subtractor 92 calculates I at each delay time for the current write address.
The address is determined and given to the data memory 88 as a read address. Data memory 88 is clocked periodically by clock C5. It is switched to write mode once. At this time, since the delay time parameter is 0, the value of the counter 90 is output as is from the subtracter 92, and the output of the pre-memory 82 is written to the address of the data memory 88 indicated by the value. At this time, the pre-memory 82 stores the counter 8
Since the next write address is commanded by 0, the data loaded into data memory 88 will be a sample of the pre-memory 82 delayed input signal.

At timings other than clock C5, the data memory 88
is switched to read mode and the period τ is read from coefficient memory 4.
By each delay time parameter τ1 that is sequentially outputted within, the data at each delay time of τ1 with the write address as a reference is sequentially read out.

Each delay data x1 of the input signal read out one time from the data memory 88 is sent to the coefficient memory 4 in the multiplier 94.
Each level parameter is sequentially output from
6, the multiplication value from the multiplier 94 is accumulated by the adder 98 and the register 00. As a result, the accumulator 96 finally outputs the total accumulated value within the period τ. The contents of register 100 are reset by clock C6 after all multiplication values have been accumulated.

The zero detection circuit 104 detects the level of the input signal, and uses a multiplier 106 to square the delayed data sequentially read out from the flash memory 82 within one sampling period τ0, and sends each squared value to the adder 108 and the register 10. Accumulate with . Then, the total accumulated value within the period τ is transferred to the register 112 using the clock C1. In this way register 1
2 holds a value corresponding to the level of the input signal.

The register 10 is reset every sampling period τ0 by the clock C1.

The adaptive operation parameters are read out as follows.

When the output of the zero detection circuit 104 becomes zero, the comparator 1
18 resets the counters 20,122. The counter 20 sets the initial value of the adaptive operation parameter data, and is set to "1" when reset, and becomes the count value of the output of the coincidence detection circuit 124 when the reset is released.

The counter 16 commands a read address, and is reset by a clock C7 that is output once every cycle τ0, reads the value of the counter 20 at the next clock C8, uses that value as the initial value, and counts up the clock C8. Outputs i successive addresses used for continuous operation within period τ. When the counter 20 is "1" (when the input signal continues), the counter 16 is preset to "1" and the coefficient memory 4 is sequentially designated from address 1 to address i.

The counter 22 is reset and released by zero detection, and thereafter is counted up by the clock C1. This count value corresponds to the number of samples after the shift to the adaptive mode, and means the elapsed time t after the shift to the adaptive mode (the elapsed time after the input signal is interrupted).

The coincidence detection circuit 124 determines each delay time parameter τl to τ for adaptive operation. and time t, and each time they match, a pulse is output, and the counter 20 counts this.

This is because in adaptive operation, the parameter of the delay time after (that is, greater than t) the elapsed time t after the input signal interruption is applied (the delay time before (less than t) Since the input signal data corresponding to 2 is 0 due to the interruption of human power, it is meaningless to convolve it), find out how many parameters have passed since the input signal was interrupted, and calculate This is to determine whether to apply the parameters to the convolution operation.

The value of the counter 16, which counts the clock C5 with the value of the counter 20 as the initial value, is added to the coefficient memory 4 as a read address, and the corresponding parameter data is read out.

In addition, in FIG. 14, the timing controller 130
outputs control signals for operating each circuit.

FIG. 15 shows an example of the operation of the circuit shown in FIG. 14.

However, this indicates a state where adaptive operation has not yet been achieved.

The sampling period starts with a clock C1, and this clock C1 is counted by counters 80 and 90, and the write address is shifted by one.

Since the delay time parameter is initially 0, the value of the counter 80.90 is then directly applied to the data memory 88 as an address signal. Data memory 88 is written with clock C5.

At this time, the counter 80 in the pre-memory 82 is commanding the next write address, and the data at that address is transferred to the data memory 88 by the clock C5. Thereafter, new data is entered into the pre-memory 82 by the clock C9.

The adaptive operation parameters are sequentially read out from the coefficient memory 14 at the cycle of the clock C8.

In FIG. 15, since the adaptive operation has not yet been started, the initial value of the counter 116 is 1 (O before it is in the reset state), and the adaptive operation parameter is (τ + g
) ~ (τ 1g,) and the beginning 1 1 1
1 i pieces have been read. Once the adaptive movement begins,
The initial value of the counter 116 changes sequentially from 2.3, . . . , and the parameters also shift sequentially accordingly.

One sampling period τ due to this adaptive operation.

If we accumulate each calculation value within, in each cycle. At the end of the process, a final cumulative n value is obtained, which is one sample of the reverberant signal. And each sampling period τ. This operation is repeated for each reverberation signal to create a series of reverberant signals.

The reverberation adding circuit 12 shown in FIG. 14 described above can be applied to the embodiments shown in FIGS. 1 and 4 in combination with the frequency characteristic control circuit 10 shown in FIG. 11. In this case, in the embodiment shown in FIG. 4, filter characteristics are added after adding reverberation to the input signal, so that when the input signal is interrupted, the reverberation signal is attenuated as shown in FIG. It is possible to gradually change the filter characteristics. However, in the embodiment shown in FIG. 1, filter characteristics are added before adding reverberation, so when the input signal is interrupted, the frequency characteristic control circuit 1
0 input side, a reverberant signal that gradually attenuates like the input signal in FIG. 8 cannot be obtained, and the combination of the frequency characteristic control circuit 10 in FIG. It is not possible to gradually change the filter characteristics with attenuation.

(Other configuration examples of the circuit shown in FIG. 1) Therefore, in the embodiment shown in FIG. 1 as well, the frequency characteristic control circuit 10 and the reverberation adding circuit make it possible to gradually change the filter characteristics as the reverberant signal is attenuated. Twelve configuration examples are shown in FIGS. 16 and 17, respectively.

The frequency characteristic control circuit 10 shown in FIG. 16 is provided with a pre-memory 132 on the input side to temporarily store the input signal and then send it to the data memory 50. Based on the data stored in the pre-memory 132, a zero detection circuit 134 detects the input signal. When the sustained/interrupted state is detected and the input signal is interrupted, writing to the data memory 50 is stopped, the data of the input signal immediately before the interruption is held in the data memory 50, and this is repeatedly read out to perform convolution calculation. The filter characteristics are given by the following steps, and the filter characteristics are switched at this time. Furthermore, in the reverberation adding circuit 12 in FIG.
Reverberation is added by applying adaptive convolution to the output from the frequency characteristic control circuit 10 whose filter characteristics change.

Details of the circuits shown in FIGS. 16 and 17 will be explained. In FIGS. 16 and 17, the same reference numerals are used for parts common to the circuits in FIGS. 11 and 14.

In FIG. 16, the flash memory 132 is the data memory 5.
Writing and successive output of input signals are performed using the same address signal as 0. The write clock C3' of the flash memory 132 is a signal that is generated a moment later than the write clock C3 of the data memory 50. Therefore, while data is being read from the next write address of the pre-memory 132, the data that has been read from the pre-memory 132 is written into the data memory 50 by the clock c3.
Data delayed by the capacity of is written. Immediately after this, writing to the flash memory 132 is performed by clock 03'.

The zero detection circuit 134 is almost the same as that shown in FIG. 14, except that the clock C2 is used as the transfer clock for the register 140. This zero detection circuit 134
The output of the comparator 144 is input to a comparator 144, and if it is smaller than a predetermined threshold level, it is determined that the input signal has been interrupted. As a result, new writing to the data memory 50 is stopped, the counter 52 stops counting, and the data of the input signal immediately before the interruption is held in the data memory 50, and this data is repeatedly read out every sampling period τ0. The coefficients of the filter characteristics read from the filter characteristic parameter memory 46 are added, and the filter characteristics are added by convolution calculation.

At this time, the counter 8o is activated by the output signal of the comparator 144 as the trigger signal TRG, and sequentially reads out the values of the cross-fade coefficients x and y from the cross-fade parameter memory 78, and sets the frequency characteristics of the A system and the B system. Apply a crossfade between the frequency characteristics of. Then, each time one system is completely attenuated, the counter is switched up or down, and the filter characteristics of the attenuated system are switched. By doing so, the frequency characteristic control circuit 10 outputs a signal with the filter characteristics sequentially switched even after the input signal is interrupted.

In the reverberation adding circuit 12 shown in FIG.
8, the output signal of the frequency characteristic control circuit 10 shown in FIG. 16 is input manually, and reverberation is added by convolution calculation. When comparator 144 of FIG. 16 detects a loss of input signal, counters 20, 122 are released from reset and adaptive operation is performed. That is, counter 22
The elapsed time after shifting to the adaptive operation is determined, and the match detection circuit 124 outputs a pulse every time the delay time parameter τ1~ matches .This is counted by the counter 120, and the initial value of the counter 16 is sequentially increased. Then, successive addresses in the coefficient memory 4 are sequentially changed to higher-order addresses, and the parameters of the impulse response used for adding reverberation are sequentially shifted from the initial phase to the middle phase to the late phase. Adaptive operation is thus performed. In this case, a signal in which the filter characteristics are sequentially changed is inputted to the human input from the frequency characteristic control circuit 10 in FIG. Output. In this way, the control shown in FIG. 8 is also realized in the embodiment shown in FIG.

(Example of configuration of the embodiment shown in Figure 5) Next, a configuration example of the embodiment shown in FIG. 5 will be explained.

In the embodiment shown in FIG. 5, filter characteristics are added to the impulse response parameters themselves for adding reverberation, as described above. This is an attempt to obtain a reverberation signal with predetermined filter characteristics by passing the impulse response pattern through a filter and transforming it, and then performing a convolution operation using this transformed impulse response. .

An example of the configuration of the embodiment shown in FIG. 5 is shown in FIG. 18.

In FIG. 18, the input signal is temporarily stored in a flash memory 150 for detection of its continuation/discontinuation state, and then transferred to a data memory 152.

The coefficient memory 14 stores impulse response coefficient parameters for adding reverberation. Since impulse responses occur at discrete times as shown in FIG. 19, the coefficient memory 14 of the embodiments shown in FIGS. (see Table 3), but here, in order to add filter characteristics to the impulse response itself, we will use the impulse response as data arranged in chronological order, and record the reflected sound for each sampling period To. Memorize the level. That is, even parts where there is no reflected sound are stored as reflected sounds of level 0. Table 4 below shows the storage contents of the coefficient memory 14 when using the impulse response in FIG. 19 as an example; Since the address itself corresponds to the delay time, there is no need to store delay time data as in the case of Table 3 above.

In FIG. 18, the counter 153 is the data memory 15
This command commands a write address of 2, and is counted up every cycle τ0 by the clock C1. counter 15
4 is for commanding successive addresses of the data memory 152 and the coefficient memory 14, and the period τ is set by the clock C8.
A predetermined number is counted up for each 0. The subtracter 155 subtracts the value of the counter 154 from the value of the counter 153 and provides the value obtained by subtracting the value of the counter 154 to the data memory 152 as a subsequent address.

The zero detection circuit 158 detects the level of the input signal based on the stored contents of the flash memory 150. For example, like the zero detection circuit 104 in FIG.
It is configured to calculate the sum of squares of 50 stored data.

Comparator 160 compares the output of zero detection circuit 158 to a predetermined threshold to determine the sustain/discontinue condition of the input signal.

Counter 156 provides the initial address of the parameters for adaptive operation, and when the input signal is sustained,
It is reset by the output of comparator 160. Therefore, at this time, the adder 162 directly uses the count value of the counter 154 as a read address command for the coefficient memory 14.
The coefficient memory 14 reads out the coefficient parameters of the impulse response from address 0. Further, when the input signal is interrupted, the counter 156 is reset and is counted up every sampling period τ0. Therefore, the read address area of the coefficient memory 14 has a sampling period τ. Each address is shifted by one address, and the coefficient parameters of the lower impulse responses are output one after another. In this way, the adaptive operation parameters are read out.

The impulse response coefficient parameters output from the coefficient memory 14 are manually input to the frequency characteristic control circuit 10. The frequency characteristic control circuit 10 is configured as shown in FIG. 11, for example, and imparts predetermined filter characteristics to the manually inputted impulse response coefficient parameters. When using the frequency characteristic control circuit 10 shown in FIG. 11, the period of the input signal is not the period τ0 of the clock C1 but the period of the clock C8, so the convolution operation for imparting filter characteristics in the circuit shown in FIG. Change the speed accordingly.

Note that FIG. 20 shows an example in which the coefficient parameters of the impulse response shown in FIG. 19 are passed through the frequency characteristic control circuit 10 to give filter characteristics (in FIG. This shows the case where

) The coefficient parameters of the impulse response to which the filter characteristics are added are sequentially read out from the frequency characteristic control circuit 10 at the cycle of the clock C8, and are stored in the data memory 15 in synchronization with this.
The multiplier 164 multiplies the data of the input signal output from the multiplier 164. The second multiplication value is obtained by the adder 166 and the register 16.
Accumulated by an accumulator consisting of 8, 1 sampling interval τ. The total accumulated value obtained each time is latched into the register 170 by the clock C1. In this way,
A reverberation signal with frequency characteristics is output from the register 170.

Note that the output of the comparator 160 is used as the signal TRG for the filter characteristic cross-fade in the frequency characteristic control circuit 10.
(Fig. 11). Also, the first
Even in the configuration shown in FIG. 8, it is possible to perform control in which the filter characteristics are sequentially switched along with the attenuation of the reverberant sound as shown in FIG.

〔Effect of the invention〕

As explained above, 1. According to the first invention of this application, the filter characteristics added to the reverberant sound are changed over time. It is possible to faithfully reproduce the reverberant sound. Furthermore, various special effects can be obtained by setting various temporal changes in the filter characteristics.

Further, according to a second invention of this application, in the reverberation adding device of a method of performing data calculation on input signal data based on predetermined coefficient data to create reverberation sound data of the input signal, the temporally changing Filter characteristics can also be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the invention. FIG. 2 is a diagram showing an impulse response. FIG. 3 is a circuit diagram showing a circuit that adds reverberation by convolution using the impulse response of FIG. 2 as a parameter. FIG. 4 is a block diagram showing a second embodiment of the invention. FIG. 5 is a block diagram showing a third embodiment of the invention. FIG. 6 is a circuit diagram showing an example of the frequency characteristic control circuit 10 of FIGS. 1, 4, and 5. FIG. 7 shows the cross-fade coefficient X shown in FIG. FIG. 3 is a diagram showing temporal changes in y. FIG. 8 shows that using the frequency characteristic control circuit 10 of FIG.
5 is a time chart showing a state in which filter characteristics are sequentially changed with respect to an attenuating reverberant signal. FIG. 9 is a diagram showing each filter characteristic used in the operation of FIG. 8. FIG. 10 is a circuit diagram showing an example in which the filters 16 and 18 in FIG. 6 are constructed as recursive filters. FIG. 11 is a block diagram showing a configuration example of the frequency characteristic control circuit 10 of FIG. 6, which is configured using an acyclic filter. FIG. 12 is a diagram showing the principle of an acyclic filter. FIG. 13 is a time chart showing the operation of the circuit of FIG. 11. FIG. 14 is a block diagram showing an example of the configuration of the reverberation adding circuit 12 in the embodiments of FIGS. 1 and 4. FIG. FIG. 15 is a time chart showing the operation of the circuit of FIG. 14. 16 and 17 are configuration diagrams of the frequency characteristic control circuit 10 and the reverberation adding circuit 12 for realizing the filter characteristic switching operation of FIG. 8 in the embodiment of FIG. 1. FIG. 18 is a block diagram showing an example of the configuration of the embodiment shown in FIG. FIG. 19 is a diagram showing an example of impulse response parameters stored in the coefficient memory 14 in FIG. 18. FIG. 20 shows the frequency characteristic control circuit 10 in FIG.
FIG. 3 is a diagram showing parameters of an impulse response to which a filter characteristic is output and which is given a filter characteristic. 10... Frequency characteristic control circuit (frequency characteristic control means)
, 11... Filter characteristic control means, 12... Reverberation Figure 1 Figure 4 Figure 5 Figure 2 y Figure 6

Claims (2)

[Claims] (1) A reverberation adding device that creates a reverberant sound of an input signal, which includes a frequency characteristic control means that adds a filter characteristic to the input signal itself or the created reverberant sound, and a filter characteristic variable means that adds a temporal change to the filter characteristic. A reverberation adding device comprising: (2) In a reverberation adding device that performs data calculation on input signal data based on predetermined coefficient data to create reverberant sound data of the input signal, the input signal data before creating reverberant sound or the reverberant sound is created. A reverberation adding device comprising: a frequency characteristic control means for adding a filter characteristic to the subsequent reverberation sound data or the coefficient data; and a filter characteristic variable means for adding a temporal change to the filter characteristic.