JPH03154487A - Digital still video camera - Google Patents

Digital still video camera

Info

Publication number
JPH03154487A
JPH03154487A JP1293601A JP29360189A JPH03154487A JP H03154487 A JPH03154487 A JP H03154487A JP 1293601 A JP1293601 A JP 1293601A JP 29360189 A JP29360189 A JP 29360189A JP H03154487 A JPH03154487 A JP H03154487A
Authority
JP
Japan
Prior art keywords
digital
clock
video camera
mode
still video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1293601A
Other languages
Japanese (ja)
Inventor
Takeoki Sakai
酒井　勇起
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Konica Minolta Inc
Original Assignee
Konica Minolta Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Konica Minolta Inc filed Critical Konica Minolta Inc
Priority to JP1293601A priority Critical patent/JPH03154487A/en
Priority to GB9024224A priority patent/GB2240446A/en
Priority to DE4035574A priority patent/DE4035574A1/en
Publication of JPH03154487A publication Critical patent/JPH03154487A/en
Priority to US07/844,932 priority patent/US5206730A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/21—Intermediate information storage
    • H04N1/2104—Intermediate information storage for one or a few pictures
    • H04N1/2112—Intermediate information storage for one or a few pictures using still video cameras
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/65—Control of camera operation in relation to power supply
    • H04N23/651—Control of camera operation in relation to power supply for reducing power consumption by affecting camera operations, e.g. sleep mode, hibernation mode or power off of selective parts of the camera
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/21—Intermediate information storage
    • H04N1/2104—Intermediate information storage for one or a few pictures
    • H04N1/2112—Intermediate information storage for one or a few pictures using still video cameras
    • H04N1/2137—Intermediate information storage for one or a few pictures using still video cameras with temporary storage before final recording, e.g. in a frame buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2101/00—Still video cameras

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Signal Processing For Recording (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Studio Devices (AREA)

Abstract

PURPOSE:To reduce current consumption by switching a clock frequency in response to the setting mode setting the consecutive photographing or the single photographing. CONSTITUTION:When the single photographing mode in the photographing mode is selected by an operation panel 11, a CPU 10 switches a changeover switch 9 to the position of fCLK/N. Thus, a low frequency clock is fed to a digital process circuit 5 and a data compression circuit 6 and a high frequency clock is fed to other sections. In this case, when a release switch 12 is depressed, an output signal of a CCD sensor 2 is converted into a digital picture data by an A/D converter section 3 and stored once in a frame memory. Then the processing is applied by the digital process circuit 5 driven by the fCLK/N and the data compression circuit 6. Thus, the digital processing is implemented by 1/N clock to reduce the power consumption per unit time to 1/N.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、静止画をディジタルデータとして記憶するデ
ィジタルスチルビデオカメラに関し、更に詳しくは、低
消費電流のディジタルスチルビデオカメラに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital still video camera that stores still images as digital data, and more particularly to a digital still video camera with low current consumption.

（発明の背景） 近年、静止画をビデオフロッピーに記録するスチルビデ
オカメラに代わり、メモリカードなどの半導体メモリに
画像を記憶させるディジタルスチルビデオカメラが使用
されることがある。(Background of the Invention) In recent years, digital still video cameras that store images in a semiconductor memory such as a memory card are sometimes used instead of still video cameras that record still images on a video floppy.

まず、第３図を参照して従来のディジタルスチルビデオ
カメラの概要について説明する。この図において、１は
ディジタルスチルビデオカメラの各部に周波数ｆ　ｅｌ
ｋのクロックを印加するＳＳＧ。First, an overview of a conventional digital still video camera will be explained with reference to FIG. In this figure, 1 indicates the frequency f el in each part of the digital still video camera.
SSG applying k clocks.

２は被写体からの光を受けて光電変換を行い画像信号を
生成する受光部としてのＣＣＤ、３はＣＣＤ２からの画
像信号をディジタル画像データに変換するＡ／Ｄ変換器
、４はディジタル画像データを一時的に蓄積するための
フレームメモリ、５はディジタル画像データをＹ、Ｉ、
Ｑ信号等に変換するディジタルプロセス回路、６はＹ、
Ｉ、Ｑ信号をデータ圧縮してデータ量を小さ（するため
のデータ圧縮回路、７はデータ圧縮回路からのディジタ
ル画像データを記憶するメモリである。このメモリ７は
、ディジタルスチルビデオカメラに内蔵された半導体メ
モリ若しくは着脱可能なＩＣカード（メモリカード）等
で構成されている。↑０は各部分を制御するＣＰＵ、１
１は各種動作モト（単写／連写を切り替える撮影モード
等）の操作、切り替え等を行う操作パネル、１２はレリ
ーズスイッチである。2 is a CCD as a light receiving unit that receives light from the subject and performs photoelectric conversion to generate an image signal; 3 is an A/D converter that converts the image signal from CCD 2 into digital image data; 4 is an A/D converter that converts the image signal from the CCD 2 into digital image data; Frame memory 5 for temporarily storing digital image data Y, I,
Digital process circuit that converts to Q signal etc. 6 is Y,
A data compression circuit compresses the I and Q signals to reduce the amount of data. 7 is a memory that stores digital image data from the data compression circuit. This memory 7 is built in the digital still video camera. It consists of a semiconductor memory or a removable IC card (memory card), etc. ↑ 0 is a CPU that controls each part, 1
Reference numeral 1 designates an operation panel for operating and switching various operations (such as a shooting mode for switching between single shooting and continuous shooting), and 12 a release switch.

このように構成したディジタルスチルビデオカメラの動
作は以下のとおりである。The operation of the digital still video camera configured as described above is as follows.

操作パネル１１の撮影モードで速写モードが選択されて
いる場合、レリーズスイッチ１２が押されると、ＣＣＤ
センサ２の出力信号はＡ／Ｄ変換器３でディジタル画像
データに変換されフレームメモリに一旦スドアされ、デ
ィジタルプロセス回路５でＹ、Ｉ、Ｑ信号に変換され、
これがデータ圧縮回路６で圧縮された後、メモリ７に記
録される。そして、この一連の動作をレリーズスイッチ
１２が押されている間は連続して行う。When the snapshot mode is selected in the shooting mode on the operation panel 11, when the release switch 12 is pressed, the CCD
The output signal of the sensor 2 is converted into digital image data by the A/D converter 3, stored once in the frame memory, and converted into Y, I, Q signals by the digital process circuit 5.
After this is compressed by the data compression circuit 6, it is recorded in the memory 7. This series of operations is performed continuously while the release switch 12 is pressed.

一方、操作パネル１１の撮影モードで単写モードが選択
されている場合、レリーズスイッチ１２が押されると、
ＣＣＤセンサ２の出力信号はＡ／Ｄ変換器３でディジタ
ル画像データに変換されフレームメモリに一旦スドアさ
れる。そして、この動作を１コマ分行なう。On the other hand, when the single shot mode is selected in the shooting mode on the operation panel 11, when the release switch 12 is pressed,
The output signal of the CCD sensor 2 is converted into digital image data by an A/D converter 3, and is temporarily stored in a frame memory. This operation is then repeated for one frame.

（発明が解決しようとする課題） 以上のようなディジタルスチルビデオカメラでは、１０
コマ／秒の連写を行う場合、１枚当たり１００ｓｓｅｃ
以内に撮像から最終処理までを行う必要がある。この１
００ｍ５ｅｃのうち３３．３ｉｓｅｃ　（１／８０ｓｅ
ｃ　）はＣＣＤセンサから読出してフレームメモリにス
トアするのに必要であるため、残余の６８．７ａ＋ｓｅ
ｃで信号変換（映像信号からＹ、！、Ｑ信号への変換）
及びデータ圧縮を行う必要がある。ＣＯＤの画素数を４
０万画素（Ｈ８００ＸＶ５００　）とすると、ディジタ
ルプロセス部にて、Ｙ、Ｉ、Ｑ信号は、Ｙ−８００ｘ５
００−０．４　Ｍバイト１−４００　ｘ５００−０．２
　ＭバイトＱ−４００Ｘ５００−０．２　Ｍバイトにな
る。すなわち、１画像が０．８Ｍバイトのデータに変換
される。(Problem to be solved by the invention) In the above digital still video camera, 10
When performing continuous shooting at frames/second, 100 ssec per frame
It is necessary to perform everything from imaging to final processing within a certain period of time. This one
33.3isec out of 00m5ec (1/80sec
c) is necessary to read from the CCD sensor and store it in the frame memory, so the remaining 68.7a+se
Signal conversion with c (conversion from video signal to Y, !, Q signal)
and data compression. The number of pixels of COD is 4
00,000 pixels (H800xV500), the Y, I, and Q signals are Y-800x5 in the digital processing section.
00-0.4 MB 1-400 x500-0.2
M byte Q-400X500-0.2 M byte. That is, one image is converted into 0.8 Mbytes of data.

従って、８Ｂ、７１ＳｅＣ１０，８Ｍバイト−８３，４
ｒ＋ｓｅｃ／バイトになる。これは、１バイト当たり８
３．４ｎｓｏｃでデータを処理する必要があることを示
している。Therefore, 8B, 71SeC10, 8M bytes - 83,4
It becomes r+sec/byte. This is 8 per byte.
This indicates that it is necessary to process data at 3.4 nsoc.

このように高速でデータ処理を行う場合には、ＣＭＯ３
ＩＣを使用し、上述の処理時間内で処理できるようなり
ロックで駆動されている。尚、このクロック周波数は、
連写時も単写時も同じである。When performing data processing at such high speed, CMO3
It uses an IC and is driven by a lock so that it can process within the processing time mentioned above. Furthermore, this clock frequency is
The same applies to continuous shooting and single shooting.

ところで、ＣＭＯ５の消費電力はクロック周波数に比例
して大きくなるため、プロセス回路とデータ圧縮回路と
で１ワット以上の電力を消費することになる。By the way, since the power consumption of the CMO 5 increases in proportion to the clock frequency, the process circuit and data compression circuit consume power of 1 watt or more.

このように、単写のように高速処理が必要ない場合にお
いても、高いクロック周波数で駆動するのは、非効率的
であり、消費電力の点で望ましくない。特に、バッテリ
ーの場合、消費電流が大きくなると、内部抵抗等の原因
により消耗が早くなるといった問題がある。すなわち、
消費電力（電圧×電流Ｘ時間）が同じ場合であっても、
短時間に大電流を流す場合は、小電流を長時間流す場合
に比較して効率が低下する。As described above, even in cases where high-speed processing is not required, such as in single shooting, driving at a high clock frequency is inefficient and undesirable in terms of power consumption. In particular, in the case of a battery, there is a problem in that when the current consumption increases, the battery wears out quickly due to internal resistance and the like. That is,
Even if the power consumption (voltage x current x time) is the same,
When a large current is passed for a short time, the efficiency is lower than when a small current is passed for a long time.

本発明は上記した問題点に鑑みてなされたもので、その
目的とするところは、消費電流が小さいディジタルスチ
ルビデオカメラを実現することにある。The present invention has been made in view of the above problems, and its object is to realize a digital still video camera with low current consumption.

（課題を解決するための手段） 上記課題を解決する本発明は、静止画をディジタルデー
タとして記憶するディジタルスチルビデオカメラにおい
て、連写若しくは単写を設定するモード設定手段と、モ
ード設定手段での設定モードに応じてクロック周波数を
切り替えるクロック周波数変更手段とを有することを特
徴とするものである。(Means for Solving the Problems) The present invention, which solves the above problems, provides a digital still video camera that stores still images as digital data. The present invention is characterized by comprising a clock frequency changing means for switching the clock frequency according to a setting mode.

（作用） 本発明のディジタルスチルビデオカメラにおいて、モー
ド設定手段での設定モードに応じ、クロック周波数設定
手段がクロック周波数を切り替える。単写モードでは連
写モードに比較してクロック周波数が低く設定されるた
め、消費電流が減少する。(Function) In the digital still video camera of the present invention, the clock frequency setting means switches the clock frequency according to the mode set by the mode setting means. In single shooting mode, the clock frequency is set lower than in continuous shooting mode, so current consumption is reduced.

（実施例） 以下図面を参照して、本発明の実施例を詳細に説明する
。(Example) Examples of the present invention will be described in detail below with reference to the drawings.

まず、第１図を参照して本発明のディジタルスチルビデ
オカメラの概要について説明する。この図において、１
はディジタルスチルビデオカメラの各部に周波数ｆ６．
．のクロックを印加するＳＳＧ、２は被写体からの光を
受けて光電変換を行い画像信号を生成する受光部として
のＣＣＤ、３はＣＣＤ２からの画像信号をディジタル画
像データに変換するＡ／Ｄ変換器、４はデ、イジタル画
像データを一時的に蓄積するためのフレームメモリ、５
はディジタル画像データをＹ、Ｉ、Ｑ信号等に変換する
ディジタルプロセス回路、６はｙ、ｉ。First, an overview of the digital still video camera of the present invention will be explained with reference to FIG. In this figure, 1
The frequency f6. is applied to each part of the digital still video camera.
．． 2 is a CCD as a light receiving unit that receives light from the subject and performs photoelectric conversion to generate an image signal. 3 is an A/D converter that converts the image signal from CCD 2 into digital image data. , 4 is a frame memory for temporarily storing digital image data; 5 is a frame memory for temporarily storing digital image data;
6 is a digital process circuit that converts digital image data into Y, I, Q signals, etc., and 6 is y, i.

Ｑ信号をデータ圧縮してデータ量を小さくするためのデ
ータ圧縮回路、７はデータ圧縮回路からのディジタル画
像データを記憶するメモリである。A data compression circuit compresses the Q signal to reduce the amount of data, and 7 is a memory that stores digital image data from the data compression circuit.

このメモリ７は、ディジタルスチルビデオカメラに内蔵
された半導体メモリ若しくは着脱可能なＩＣカード等で
構成されている。８は５ＳＧＩからの周波数ｆ６Ｉｋの
クロックを１／Ｎに分周する分周器、９はディジタルプ
ロセス回路５及びデータ圧縮回路６に供給するクロック
をｆ　ｅｌｋ若しくはｆｃ、ｍ／Ｎのいづれか一方に切
り替える切り替えスイッチ、１０は各部分を制御するＣ
ＰＵ、１１は各踵動作モード（単写／連写を切り替える
撮影モード等）の操作、切り替え等を行う操作パネル、
１２はレリーズスイッチである。１３はＣＰＵｌ０及び
操作パネル１１で構成されたモード設定手段、１４は分
局器８及び切り替えスイッチ９で構成されたクロック周
波数変更手段である。The memory 7 is composed of a semiconductor memory built into the digital still video camera, a removable IC card, or the like. 8 is a frequency divider that divides the clock of frequency f6Ik from 5SGI to 1/N, and 9 switches the clock supplied to the digital process circuit 5 and data compression circuit 6 to either f elk, fc, or m/N. Changeover switch, 10 is C that controls each part
PU, 11 is an operation panel for operating and switching each heel operation mode (shooting mode for switching between single shooting/continuous shooting, etc.);
12 is a release switch. Reference numeral 13 indicates a mode setting means composed of a CPU 10 and an operation panel 11, and reference numeral 14 indicates a clock frequency changing means composed of a branching device 8 and a changeover switch 9.

このように構成したディジタルスチルビデオカメラの動
作は以下のとおりである。The operation of the digital still video camera configured as described above is as follows.

操作パネル１１の撮影モードで速写モードが選択されて
いる場合、ＣＰＵｌ０はこれを検知し、切り替えスイッ
チ９をｆｅａｔ側に切り替えておく。When the snapshot mode is selected as the shooting mode on the operation panel 11, the CPU 10 detects this and switches the changeover switch 9 to the feat side.

従って、ディジタルプロセス回路５．データ圧縮回路６
及びそれ以外の各部に、高速速写に適した高い周波数ｆ
。１にのクロックが供給されている。Therefore, digital process circuit 5. Data compression circuit 6
And other parts have a high frequency f suitable for high-speed snapshots.
. 1 clock is supplied.

レリーズスイッチ１２が押されると、ＣＣＤセンサ２の
出力信号はＡ／Ｄ変換器３でディジタル画像データに変
換されフレームメモリに一旦スドアされ、ディジタルプ
ロセス回路５でＹ、Ｉ、Ｑ信号に変換され、これがデー
タ圧縮回路６で圧縮された後、メモリ７に記録される。When the release switch 12 is pressed, the output signal of the CCD sensor 2 is converted into digital image data by the A/D converter 3, stored in the frame memory, and converted into Y, I, and Q signals by the digital process circuit 5. After this is compressed by the data compression circuit 6, it is recorded in the memory 7.

そ（７て、この−連の動作をレリーズスイッチ１２が押
されている間は連続して行う。(7) This sequence of operations is performed continuously while the release switch 12 is pressed.

一方、操作パネル１１の撮影モードで単写モードが選択
されている場合、ＣＰＵｌ０はこれを検知し、切り替え
スイッチ９をｆｃ＋＊／Ｎ側に切り替えておく。従って
、ディジタルプロセス回路５データ圧縮回路６には周波
数の低いクロックが、それ以外の各部には高い周波数の
クロックが供給されている。このとき、レリーズスイッ
チ１２が押されると、ＣＣＤセンサ２の出力信号はＡ／
Ｄ変換器３でディジタル画像データに変換されフレーム
メモリに一旦スドアされる。そして、ｆ　ｅｌｋ／Ｎで
駆動されているディジタルプロセス回路５及びデータ圧
縮回路６で処理が行われる。この場合、単写であるので
、１コマの撮影の後には時間的余裕があり、プロセス処
理、データ圧縮処理及びメモリ７への書き込みを低速で
行なっても問題はない。On the other hand, if the single shooting mode is selected in the shooting mode on the operation panel 11, the CPU 10 detects this and switches the changeover switch 9 to the fc+*/N side. Therefore, a low frequency clock is supplied to the digital process circuit 5 and data compression circuit 6, and a high frequency clock is supplied to the other parts. At this time, when the release switch 12 is pressed, the output signal of the CCD sensor 2 is
The D converter 3 converts the data into digital image data and temporarily stores it in the frame memory. Processing is then performed by the digital process circuit 5 and data compression circuit 6 which are driven by felk/N. In this case, since it is a single shot, there is plenty of time after shooting one frame, and there is no problem even if the process processing, data compression processing, and writing to the memory 7 are performed at low speed.

このように、ディジタル処理を１／Ｎのクロックで行な
うと、単位時間当たりの消費電力も１／Ｎに低下する。In this way, when digital processing is performed with a 1/N clock, power consumption per unit time is also reduced to 1/N.

但し、クロックを１／Ｎにしたために、処理時間がＮ倍
になり、消費する電力量は等しくなる。ところが、バッ
テリーの特性により、大電流を短時間流すより、小電流
を長時間流す方が、バッテリーから取り出せる電力量が
大きくなることが知られている。これは、バッテリーの
内部抵抗等に起因するものであり、−次電池でも二次電
池でもほぼ同様である。一般に、ディジタルスチルビデ
オカメラはバッテリーで使用されることが多いため、本
実施例のような構成にすることにより、バッテリーを長
持ちさせることが可能になる。However, since the clock is set to 1/N, the processing time increases by N times, and the amount of power consumed becomes the same. However, due to the characteristics of batteries, it is known that the amount of power that can be extracted from the battery is greater when a small current is passed for a long time than when a large current is passed for a short time. This is caused by the internal resistance of the battery, and is almost the same for negative batteries and secondary batteries. In general, digital still video cameras are often used with batteries, so by configuring the camera as in this embodiment, it is possible to extend the life of the battery.

第２図は本発明の他の実施例の構成を示す構成図である
。この図で第１図と同一物には同一番号を付し、説明は
省略する。１５はＣＰＵｌ０により分周比が制御される
分周器である。従って、撮。FIG. 2 is a block diagram showing the structure of another embodiment of the present invention. Components in this figure that are the same as those in FIG. 1 are designated by the same numbers and their explanations will be omitted. 15 is a frequency divider whose frequency division ratio is controlled by CPU10. Therefore, take pictures.

影モードにより分周比が制御され、処理に最低限必要な
りロック周波数になるように制御される。The frequency division ratio is controlled by the shadow mode so that the lock frequency is the minimum required for processing.

この場合、撮影モードが単写／中速連写／高速連写など
のように複数ある場合でも、分周比をＣＰＵｌ０からの
指示で適宜変更することにより対応することができる。In this case, even if there are multiple shooting modes such as single shooting/medium-speed continuous shooting/high-speed continuous shooting, this can be handled by appropriately changing the frequency division ratio according to instructions from the CPU10.

従って、この実施例の場合も、バッテリーの電力を有効
に活用することができる。Therefore, in this embodiment as well, battery power can be used effectively.

（発明の効果） 以上詳捕に説明したように、本発明では、静止画をディ
ジタルデータとして記憶するディジタルスチルビデオカ
メラにおいて、連写若しくは単写を設定するモード設定
手段と、モード設定手段での設定モードに応じてクロッ
ク周波数を切り替えるクロック周波数変更手段とを有し
、モードに応じてクロック周波数を切り替えるようにし
た。従って、撮影のモードに応じて適切な処理速度で処
理をすることが可能になり、消費電流を少なく押さえる
ことでバッテリーを長持ちさせることが可能なディジタ
ルスチルビデオカメラを実現することができる。(Effects of the Invention) As explained in detail above, the present invention provides a digital still video camera that stores still images as digital data, including a mode setting means for setting continuous shooting or single shooting, and a mode setting means for setting continuous shooting or single shooting. The clock frequency changing means changes the clock frequency according to the setting mode, and the clock frequency is changed according to the mode. Therefore, it is possible to perform processing at an appropriate processing speed depending on the shooting mode, and it is possible to realize a digital still video camera that can extend the battery life by reducing current consumption.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の構成を示す構成図、第２図
は本発明の他の実施例の構成を示す構成図、 第３図は従来のディジタルスチルビデオカメラの構成を
示す構成図である。 １・・・ＳＳＧ　　　　　２・・ＣＣＤセンサ３・・・
Ａ／Ｄ変換器　４・・・フレームメモリ５・・・ディジ
タルプロセス回路 ６・・・データ圧縮回路 ７・・・メモリ　　　　８・・・分周器９・・・切り替
えスイッチ １０・・・ＣＰＵ　　　　１１・・・操作パネルＩ２・
・・レリーズスイッチ １３・・・モード設定手段 １４・・・クロック周波数変更手段FIG. 1 is a configuration diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a configuration diagram showing the configuration of another embodiment of the invention, and FIG. 3 is a configuration diagram showing the configuration of a conventional digital still video camera. It is a diagram. 1...SSG 2...CCD sensor 3...
A/D converter 4... Frame memory 5... Digital process circuit 6... Data compression circuit 7... Memory 8... Frequency divider 9... Changeover switch 10... CPU 11.・・Operation panel I2・
...Release switch 13...Mode setting means 14...Clock frequency changing means

Claims (1)

【特許請求の範囲】 　静止画をディジタルデータとして記憶するディジタル
スチルビデオカメラにおいて、 連写若しくは単写を設定するモード設定手段（１３）と
、 モード設定手段（１３）での設定モードに応じてクロッ
ク周波数を切り替えるクロック周波数変更手段（１４）
とを有することを特徴とするディジタルスチルビデオカ
メラ。[Claims] A digital still video camera that stores still images as digital data includes a mode setting means (13) for setting continuous shooting or single shooting, and a clock setting means (13) for setting a clock according to the setting mode in the mode setting means (13). Clock frequency changing means (14) for switching frequencies
A digital still video camera comprising:
JP1293601A 1989-11-10 1989-11-10 Digital still video camera Pending JPH03154487A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1293601A JPH03154487A (en) 1989-11-10 1989-11-10 Digital still video camera
GB9024224A GB2240446A (en) 1989-11-10 1990-11-07 Digital still video camera with selectable video signal processing speed
DE4035574A DE4035574A1 (en) 1989-11-10 1990-11-08 DIGITAL STILL VIDEO CAMERA
US07/844,932 US5206730A (en) 1989-11-10 1992-03-04 Still video camera having one-shot and serial shot modes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1293601A JPH03154487A (en) 1989-11-10 1989-11-10 Digital still video camera

Publications (1)

Publication Number Publication Date
JPH03154487A true JPH03154487A (en) 1991-07-02

Family

ID=17796826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1293601A Pending JPH03154487A (en) 1989-11-10 1989-11-10 Digital still video camera

Country Status (3)

Country Link
JP (1) JPH03154487A (en)
DE (1) DE4035574A1 (en)
GB (1) GB2240446A (en)

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WO2006137567A1 (en) * 2005-06-21 2006-12-28 Ricoh Company, Ltd. Imaging apparatus, imaging control method and recording medium readable by computer
US7606470B2 (en) 2003-09-17 2009-10-20 Casio Computer Co., Ltd. Image pickup apparatus having moving picture photographing function and moving picture photographing method thereof
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Publication number Priority date Publication date Assignee Title
JP4508452B2 (en) 2001-03-29 2010-07-21 三洋電機株式会社 Integrated circuit for image sensor
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Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0336317B1 (en) * 1988-04-08 1995-07-19 Fuji Photo Film Co., Ltd. Electronic still camera capable of selecting recording media

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US7808533B2 (en) 1998-06-30 2010-10-05 Nikon Corporation Electronic camera having signal processing units that perform signal processing on image data
US8878956B2 (en) 1998-06-30 2014-11-04 Nikon Corporation Digital camera and storage medium for image signal processing for white balance control
US7606470B2 (en) 2003-09-17 2009-10-20 Casio Computer Co., Ltd. Image pickup apparatus having moving picture photographing function and moving picture photographing method thereof
WO2006137567A1 (en) * 2005-06-21 2006-12-28 Ricoh Company, Ltd. Imaging apparatus, imaging control method and recording medium readable by computer
US8045035B2 (en) 2005-06-21 2011-10-25 Ricoh Company, Ltd. Imaging apparatus, imaging control method and recording medium readable by computer
KR100591796B1 (en) * 2005-11-11 2006-06-26 엠텍비젼 주식회사 Image processing method and apparatus
WO2007055450A1 (en) * 2005-11-11 2007-05-18 Mtekvision Co., Ltd. Image processing method and device
US8018499B2 (en) 2005-11-11 2011-09-13 Mtekvision Co., Ltd. Image processing method and device using different clock rates for preview and capture modes
JP2011029967A (en) * 2009-07-27 2011-02-10 Nikon Corp Digital camera

Also Published As

Publication number Publication date
DE4035574A1 (en) 1991-05-16
GB2240446A (en) 1991-07-31
GB9024224D0 (en) 1990-12-19

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