JPH03151635A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate recessed parts on the periphery of a trench of a thermal oxide film of buried material and realize positive flatness, by forming a protective film against etching on the periphery of the trench above the buried material. CONSTITUTION:A protective film 33 for the protection from etching on the periphery of a trench above buried material 31 after etching-back. By etching the buried material 31, the upper part of the buried material 31 is constituted in a recessed form. After the upper part of the buried layer 31 is constituted in the recessed form, the buried material 31 is thermally oxidized, so that a swelling on the central upper part of the trench 30a after thermal oxidation is relieved, recessed parts as the conventional example are not formed, and the step-difference between the surface and a thermal oxide film 32 is reduced. Thereby the surface is flattened, the short circuiting between adjacent gate wiring layers is not caused. Further the decrease of reliability caused by the disconnection of the gate wiring layer or the result that the resistance of this part becomes high can be avoided.

Description

[Detailed Description of the Invention] (Summary) Regarding a method for flattening the surface of a trench formed in a semiconductor substrate after filling it with a embedding material, the method further flattens the surface by eliminating a recess around the trench after thermal oxidation of the embedding material. For the purpose of ensuring this, a protective film is formed around the groove on the top of the ready-to-mount material, and the top of the potting material is etched to form a concave shape. A film made of the same material as the embedding material is formed on the part, and the upper part thereof is formed into a concave shape.

In step 2, or after filling the embedding material, an anisotropic etchback is performed to leave the embedding material (31) around the groove in the upper part, and one culm is included in which the upper part is formed into a concave shape.

[Industrial Application Field] The present invention relates to a method for filling a trench formed in a semiconductor substrate with a filling material and then flattening the surface thereof.

2. Description of the Related Art In semiconductor devices such as MOS transistors, so-called I-wrench isolation is used to isolate adjacent elements from each other. 1 In this case, the trench is filled with, for example, polycrystalline silicon as a filling material,
By thermally oxidizing the upper part of this polycrystalline silicon, it is turned into an insulating film to prevent short circuits with gate wiring layers of adjacent devices.

If the thermal oxide film on top of this polycrystalline silicon is not flat, the polycrystalline silicon layer for forming the gate wiring layer will remain around the trench, causing a short circuit with the adjacent gate wiring layer. must be kept flat.

(One Conventional Technology) Fig. 6 shows a manufacturing process diagram of an example of the conventional technology. In Fig. 6 (A), a thermal oxide film 2° and a nitride film 3 are formed on a semiconductor substrate 1, and this is patterned to create grooves. 4 is formed □, and a thermal oxide film 5 is formed on the side wall of the groove 4 by thermal oxidation.
The interior is filled with polycrystalline silicon ribbon 6 and etched back. In this case, overetching is performed so that no polycrystalline silicon 6 remains on the surface. Next, in FIG. 2B, the upper part of the polycrystalline silicon 6 is thermally oxidized to form a thermal oxide film 7 thereon. Furthermore, the nitride film 3 is removed, and polycrystalline silicon 8 is grown over the entire surface as shown in FIG. In this way, trench isolation is formed that separates adjacent elements.

[Problem to be solved by the invention]

In the conventional method, after over-etching the polycrystalline silicon 6, only the upper part thereof is thermally oxidized, so that the difference in level between the surface and the thermal oxide film 7 remains large. In addition to this, in general, the stress at the time of forming the thermal oxide film 7 acts strongly around the W44, so that not much thermal oxide film is formed, and the thermal oxide film 7 rises only in the central part of the trench 4. As a result,
A recess 9 is formed around the groove 4, and a gate wiring layer 8+,
The recess 9 becomes larger and deeper due to cleaning with noic acid in the pretreatment for forming the recess 82.

Therefore, as shown in FIG. 6(C), the gate wiring layer 8+
When growing polycrystalline silicon 8 to form , 82,
Since polycrystalline silicon generally has good coverage, it penetrates into the recess 9 by 4 minutes, so that the gate wiring layers 8+, 8
2, polycrystalline silicon 8' remains in the four parts 9, and the adjacent gate wiring layer 8
There was a problem that + and 82 were short-circuited.

In addition, because the recess 9 is large and deep, the gate wiring layers 8+ and 82 (polycrystalline silicon) on the recess 9 become constricted and turn dark blue, resulting in high resistance, resulting in lower reliability. . Furthermore, when metal is used for the gate wiring layer, cavities are formed in the four portions 9, causing the risk of wire breakage, lowering yield, and lowering reliability.

It is an object of the present invention to provide a method for manufacturing a semiconductor device that can further ensure planarization by eliminating concave portions around the trench after thermal oxidation of the embedding material. Figure 1 shows the principle diagram of the present invention.The problems of the conventional method are as follows.
As shown in Fig. 1<A), the embedded material 3 after etchback
Protective film 3 to protect from etching around the groove on top of 1
3, and etched the embedded material 31 to form the embedded material 3.
A method for manufacturing a semiconductor device, comprising the step of forming the upper part of the semiconductor device in a concave shape, or as shown in FIG.
A semiconductor device characterized by including a step of forming a film 31a made of the same material as the embedding material 31 around the groove above the embedding material 31 after etching back, and forming the upper part of the embedding material 31 in a concave shape after actual purchase. Alternatively, as shown in the same figure (C), after filling the embedding material 31, anisotropic etch-back is performed to form the embedding material 31 around the groove above the embedding material 31.
This problem is solved by a semiconductor device manufacturing method characterized by including a step of substantially forming the upper part of the embedding material 31 into a concave shape.

[Effect]

After making the upper part of the embedding material 31 into a concave shape, the embedding material 3
1 is thermally oxidized, the bulge in the upper center of the groove 30a after thermal oxidation is alleviated, and four parts are not formed around the groove as in the conventional example, and there is less level difference between the surface and the thermal oxide film. As a result, the surface can be made more flat than in the conventional example. Therefore, when polycrystalline silicon is grown on the surface to form a gate wiring layer and buttering is performed, the polycrystalline silicon will not get into this area because there are no four parts like in the conventional example around the upper part of the trench. There is no possibility of short-circuiting between adjacent gate wiring layers, and further, there is no possibility of disconnection of the gate wiring layer or high resistance of the gate wiring layer, which deteriorates reliability, as in the conventional example.

〔Example〕

FIG. 2 shows a manufacturing process diagram of the first embodiment of the present invention. In the same figure (A), thermal oxidation l! of silicon oxide on the semiconductor substrate 10 is shown. 11 to a thickness of 300, and CV
A silicon nitride film 12 is formed to a thickness of 1000 mm using the D method, and a PSG film 13 is further formed thereon to a thickness of 500 mm using the CVD method.
Grows to the thickness of 0 people. Next, patterning is performed using ordinary photolithography, and grooves 14 with an opening width of 1 μm and a depth of 3 μm are formed in the substrate 10 by patterning.
form. .

Next, the PSG film 13 is removed using an aqueous solution of hydrogen fluoride, and as shown in FIG.
A thermal oxide film 15 of 0 is grown. Next, in the same figure (C), the polycrystalline silicon is grown to a thickness of 12μ steel (broken line), and etched back using a uniform dry etching process to form a polycrystalline silicon layer in the groove 14. form 16. In this case, overetching is performed so that no polycrystalline silicon remains on the surface.

Next, in the same figure (D), silicon oxide 17a is grown by the CVD method (broken line), and a sidewall (silicon oxide) 17 is formed around the upper part of the groove 14 by anisotropic etching. In this case, silicon nitride may be used as the material for the sidewall. Next, in FIG. 1E, the polycrystalline silicon layer 16 is anisotropically dry etched using the sidewall 17 as a mask to form a recess 16a therein. In this case, the etching rate varies depending on the amount of oxidation of the polycrystalline silicon, but the etching rate is 0.
It may be about 1 μm to 0.4 μm.

Next, as shown in FIG.
People grow. In this case, since the polycrystalline silicon layer 16 is exposed in the center of the 14th layer, the thermal oxide film 18 of 6000 people is exposed.
However, the presence of the sidewall 17 in the peripheral area prevents the formation of a thermal oxide film, and only about 3,000 layers are formed. In other words, the center part of 14 is pre-determined by the recess 16.
a is formed, and the sidewall 17 is formed around it, so the thermal oxide film 1 is formed by thermal oxidation.
8, the bulge in the center of the vortex after thermal oxidation is relaxed, and the recess 9 (FIG. 6 (8)) unlike the conventional example is not formed, and the surface and thermal oxide film 18 are not formed. The difference between the
As a result, the surface of the thermal oxide film 18 as a whole can be made flatter than in the conventional example. Therefore, when polycrystalline silicon is grown and patterned to form gate wiring layers 81 and 82 as explained in FIG. Since the recess 9 unlike the conventional example is not formed, polycrystalline silicon does not enter into the recess 9, and there is no occurrence of a thin coat between the adjacent gate wiring layers 8+ and 82. In addition, unlike the conventional example, there is no recess 9 (FIG. 6(B)) and there is no step, so the gate wiring layers 8+ and 82 are not constricted and have high resistance, improving reliability. Even when metal is used for the wiring layer, there is no disconnection as in the conventional example, and the yield and reliability can be improved.

In addition, with the current etch-back technology, when polycrystalline silicon is etched back, a slight depression occurs toward the center, as shown in Figure 2 (C), but in the future, a technology with good edge-back characteristics will be developed. If the shape can be formed without sinking toward the center as shown in FIG. 3<A), thermal oxidation may be performed after removing the sidewalls shown in FIG. 2(D). That is, as a second embodiment of the present invention, after forming a polycrystalline silicon layer 16' in FIG. A side wall (silicon 112) 17' as shown in Figure (B) is formed, and using this side wall 17' as a mask, a recess 16a' is formed by cutting 6. Next, the sidewall 17' is removed and thermal oxidation is performed to form a thermal oxide film 18' as shown in FIG. In this case, because the edge-back characteristics are good, there is no sinking toward the center of the polycrystalline silicon layer 16', so even if the side wall 17' is removed and thermal oxidation is performed, a thermal oxide film is not formed around the trench. can be formed sufficiently, and the surface can be made more flat 1 2 without producing the four portions 9 (FIG. 6(B)) as in the conventional example.

FIG. 4 shows a manufacturing process diagram of a third embodiment of the present invention. In FIG. 2A, the steps up to the formation of polycrystalline silicon layer 16 are exactly the same as the steps shown in FIGS. 2A to 2C. In FIG. 4 (in A>, polycrystalline silicon 20a is grown on the surface to a thickness of 300 OA (broken line)), and a sidewall (polycrystalline silicon) 20 is formed in the upper peripheral part of the 14th layer by anisotropic etching. This side wall 20
and the upper surface of the polycrystalline silicon layer 16, substantially the second
It can be made into the same shape as the recessed part 16a shown in FIG.(E). Next, in FIG. 4(B), thermal oxidation is performed to form a thermal oxide film 21. In this case, since the polycrystalline silicon sidewall 20 is formed around the groove, the four parts 9 (FIG. 6(B)) unlike the conventional example do not occur, and the entire thermal oxide film 6 is removed. The surface of 21 can be made more flat.

FIG. 5 shows a manufacturing process diagram of a fourth embodiment of the present invention. Grooves 14 are formed by a method similar to that shown in FIGS. 2(A) and (B), and a polycrystalline silicon layer 25 is grown to a thickness of 1.2 .mu.m as shown in FIG. 5<A). do. Next, the groove 1 is etched back as shown in the same figure (B).
Sidewall (polycrystalline silicon) around the top of 4
25a is formed. In other words, anisotropic etching and sidewall formation are performed at the same time, and 2 parts are formed on the top of 14 parts.
Form 5b. In this case, ``one twisting due to anisotropy''
Is there 3000 people from the surface to the bottom of the recess 25b? degree. Next, in the same figure (C), thermal oxidation is performed to grow a thermal oxide film 26 of 6000 layers. In this case as well, a polycrystalline silicon sidewall 25a is formed around the groove, so that the fourth part 9 (see FIG. 6) is different from the conventional example.
B)) does not occur, and the surface of the thermal oxide film 26 can be made more flat as a whole.

The material (31) to be filled inside the groove is not limited to polycrystalline silicon, but may be Amorno? Sushirin or fast-crystal silicon may also be used. Furthermore, these various silicon films are not doped with Ge, P, B, A8, etc.

〔Effect of the invention〕

As explained above, according to the present invention, since thermal oxidation is performed after making the upper part of the embedding material concave, the surface of the thermal oxide film can be made more planar than in the conventional example. Since there is no concave part formed on the edge of the vortex layer, there is no possibility of a gap between adjacent gate wiring layers, and since there is no step, there is no risk of disconnection or constriction, which is different from the conventional method. Yield and reliability can be improved compared to 0.

14.308 is a groove, 16.16', 25 is a polycrystalline silicon layer, 16a, 1
6a', 25b are four parts, 17.17' Gluid wall (silicon oxide), 1
8.18', 21.26.32 is heat, oxide film, 20.
25a is a polycrystalline silicon; 31 is a embedding material; 318 is a film made of the same material as the embedding material; 33 is a protective film.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention, FIGS. 2 to 5 are manufacturing process diagrams of the first to fourth embodiments of the present invention, respectively, and FIG. 6 is a manufacturing process diagram of a conventional example.

Claims (6)

[Claims] (1) After filling the groove (30a) formed in the semiconductor substrate (30) with the embedding material (31), etching back is performed, and then thermal oxidation is performed to form the embedding material (31).
) a method of forming a thermal oxide film (32) on the top, forming a protective film (33) to protect from etching around the groove on the top of the embedding material (31) after the etchback;
The above-mentioned embedding material (31) is etched and the above-mentioned embedding material (31) is etched.
31) A method for manufacturing a semiconductor device, comprising the step of forming the upper part of the device into a concave shape. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the concave portion is formed by dry etching. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the thermal oxidation is performed with the protective film (33) remaining. (4) The method of manufacturing a semiconductor device according to claim 1, wherein the thermal oxidation is performed after removing the protective film (33). (5) After filling the groove (30a) formed in the semiconductor substrate (30) with the embedding material (31), etching back is performed, and then thermal oxidation is performed to perform the embedding material (31).
) In the method of forming a thermal oxide film (32) on the upper part, a film (31a) made of the same material as the filling material (31) is formed around the groove on the top of the filling material (31) after the etchback. A method for manufacturing a semiconductor device, comprising the step of substantially forming the upper part of the embedding material (31) into a concave shape. (6) After filling the groove (30a) formed in the semiconductor substrate (30) with the embedding material (31), etching back is performed, and then thermal oxidation is performed to form the embedding material (31).
) In the method of forming a thermal oxide film (32) on the upper part, after filling the embedding material (31), an anisotropic etch-back is performed to form the embedding material in the groove periphery of the upper part of the embedding material (31). (31), and substantially the above-mentioned embedding material (3).
A method for manufacturing a semiconductor device, comprising the step of 1) forming a concave upper part.