JPH03148769A - Layout pattern verification system - Google Patents

Abstract

PURPOSE:To verify an electric characteristic even to the layout pattern of a large-scale logical circuit by using a verification data calculated based on a reference circuit constant extracted from a layout pattern data and a given process parameter. CONSTITUTION:Before the verification of the electric characteristics of a logical circuit, the logical verification of the circuit connection data itself of the logical circuit corresponding to the layout pattern is executed by a logical circuit verification part 100. In such the case, the verification data which is used by a verification data decision part 104 when judging the normal/defective condition of the electric characteristic of the logical circuit is the data calculated by a verification data calculation part 103 based on the reference circuit constant extracted by a second data extraction part 102 from a layout pattern data d2 and the process parameter given by a process parameter giving means d3, that is, a data obtained without executing a circuit simulation. Thus, even for the layout pattern of the large-scale logical circuit, its electric characteristic can be verified easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a layout pattern verification system for verifying the electrical characteristics of a layout pattern forming a predetermined logic circuit.

[Conventional technology]

FIG. 14 is a block diagram showing a conventional logic circuit layout pattern verification system. As shown in the figure, circuit connection data D1 of a logic circuit corresponding to a layout pattern for which layout verification is to be performed is taken into circuit constant extraction means 1, and data D2 of a layout pattern for which layout verification is to be performed is input to circuit constant extraction means 2. be taken in. For example, when the target of layout pattern verification is the transistor size, the channel length Ll and channel width W1 of the transistor 10 are imported into the circuit constant extraction means 1 from the circuit connection data D1 as shown in the schematic diagram of FIG. Rarely, the channel length L2° and the channel width W2 are taken into the circuit constant extraction means 2 from the layout pattern data D2 as shown in the schematic diagram of FIG. In FIG. 16, reference numeral 11 indicates a diffusion region, and reference numeral 12 indicates a polysilicon region, and the portion where these regions 11 and 12 overlap is the transistor 10.
This is a transistor (gate) formation region 13.

The circuit constants (first
In the examples shown in FIGS. 5 and 16, Ll and Wl.

L2. W2) is taken into the verification unit 3. The verification unit 3 compares the verification data obtained from the circuit constant extraction means 1 with the verification data obtained from the circuit constant extraction means 2 to verify whether the layout pattern has been designed correctly.

If it is determined that there is an error, an error list EL is output in which a name for specifying the transistor, a gain coefficient ratio, etc. are described. In the examples shown in FIGS. 15 and 16, the layout pattern is verified by comparing the channel length L1 and channel width 2 and the channel widths W1 and W2, respectively.

Then, if it is Ll-L2 and Wl-W2, it is determined that the layout pattern is correctly designed. On the other hand, if L1≠L2 or W1≠W2, an error list EL is output.

When the error list EL is output, the designer corrects the layout pattern by referring to the error list EL, and changes the layout pattern data D to realize the intended circuit.
2 can be changed.

[Problem to be solved by the invention]

Conventional logic circuit layout pattern verification systems are configured as described above, and are used to verify transistor size, etc.
It merely verified the dimensional characteristics of the elements forming the logic circuit.

Therefore, in order to guarantee the electrical characteristics of the logic circuit in the designed layout pattern, it was necessary to separately perform a circuit simulation based on the circuit connection data D1.

However, in reality, it is extremely impractical to perform circuit simulation when the logic circuit to be verified has a large-scale circuit configuration.

For these reasons, the current layout pattern verification system has a problem in that it cannot guarantee the electrical characteristics of the target logic circuit.

In addition, as technology advances, the formation width of aluminum wiring and polysilicon layers becomes finer, and the design rules of wafer processes change, dimensions such as transistor size (channel length, channel width) etc. There was a problem in that the characteristics had to be changed from time to time.

This invention was made in order to solve the above-mentioned problems, and the circuit connection data does not have the dimensional characteristics of the circuit forming elements, and can be used even for layout patterns of large-scale logic circuits. The purpose of this invention is to obtain a layout pattern verification system that can verify physical characteristics.

[Means to solve the problem]

The layout pattern verification system according to the present invention includes:
A system for verifying the electrical characteristics of a layout pattern forming a predetermined logic circuit, which provides circuit connection data that defines the connection relationship of elements forming the logic circuit and the magnitude relationship of the charge supply capacity of a specific element. a circuit connection data providing means for providing layout pattern data defining a layout pattern of the logic circuit; a layout pattern data providing means for providing layout pattern data defining a layout pattern of the logic circuit;
11;1m a process parameter providing means for providing various necessary process parameters; and a first data extracting means for extracting the specific element for which the magnitude relationship of the charge supply capability is defined from the circuit connection data as a verification element. a second data extraction means for extracting circuit constants related to the charge supply capability of the verification element as reference circuit constants from the layout pattern data; A verification data calculation means for calculating verification data representing a charge supply capability ratio; and a verification data determination means for determining the quality of electrical characteristics of the logic circuit formed by the layout pattern based on the verification data. It is configured.

[Effect]

In this invention, the verification data used by the verification data determining means when determining the quality of the electrical characteristics of the logic circuit formed by the layout pattern is a reference circuit constant extracted from the layout pattern data by the second data extracting means. This data is calculated by the verification data calculation means based on the process parameters given by the process parameter provision means. Therefore, the verification data can be said to be data obtained without performing circuit simulation.

〔Example〕

FIG. 1 is a block diagram showing a layout pattern verification system according to a first embodiment of the present invention for verifying the gain coefficient ratio in a β ratio circuit forming a transistor gain coefficient ratio ratio ratio circuit.

As shown in the figure, circuit connection data 31dl of a logic circuit corresponding to a layout pattern for which layout verification is to be performed is taken into the logic circuit verification section 2o. An example of the β ratio circuit of the circuit connection data d1 is schematically shown in FIG. As shown in Figure 2, n connected in series between the power supply vDD and ground
Channel MOS) transistors Ql and Q2 are inserted. A transistor Q whose drain is connected to the power supply vDD
1 is a depression type, and its gate and source are commonly connected. On the other hand, the transistor Q2 whose source is grounded is of an enhancement type, and the input signal INI is applied to its gate.

And the source of transistor Q1 and transistor Q2
The signal obtained from the node N1 between the drains of the output signal OUT1 becomes the output signal OUT1. In addition, the signal strength label of transistor Q2, which is the charge supply capability expression value, is relatively “large J
(Strong) and 1. It is described that the signal strength level of transistor Q1 is relatively "weak".

In this β ratio circuit, the L” level input signal IN
When I is input, transistor Q1 is turned on and transistor Q2 is turned off, so the output signal OU of H" level
T1 is obtained. On the other hand, the input signal INI at °H" level
When input, both transistors Ql and Q2 turn on. At this time, the signal strength level of the transistor Q2 is stronger than the signal strength level of the transistor Q1, and the transistor Q2 is turned on more strongly, leading the potential of the node N1 to the ground level, so that the output signal OUTI at the 'L' level is obtained. In this way, an inverter of a β ratio circuit is constructed in which output signal values of different intensity levels compete with each other at the node N1 between the source of the transistor Q1 and the drain of the transistor Q2.

As described above, the circuit connection data d1, like the conventional circuit connection data D1, is connected to the transistor Ql.

It does not specify the dimensional characteristics such as channel length and channel width of Q2, and only clearly states that the signal strength level of transistor Q2 is higher than that of transistor Q1.

The logic circuit verification unit 20 verifies whether the logic circuit defined by the circuit connection data d1 described above operates correctly by performing logic simulation. Therefore, the logic circuit verification unit 2o can confirm in advance whether the charge supply capability expression value and the like of the circuit connection data d1 are correctly described. That is, when the logic circuit verification unit 2o performs a logic simulation and determines that the logic operation of the logic circuit defined by the circuit connection data d1 is performed normally, the logic circuit verification unit 2o uses the circuit connection data d1 as it is and sends it to the β ratio circuit forming transistor extraction unit. 21, and if it is determined that the logic operation is not performed normally, an error message EMI is output, prompting the designer to correct the circuit connection data d1.

The β ratio circuit forming transistor extraction unit 21 extracts transistors forming a β ratio circuit (hereinafter abbreviated as “β transistors”) from the circuit connection data d1 shown in FIG. 2, which has been logically verified by the logic verification unit 20. ) (Ql, Q2 in the example of FIG. 2), and designates the extracted β transistor to the β ratio circuit constant extracting section 22 of the next stage.

The β ratio circuit constant extraction unit 22 extracts the circuit constant of the β transistor designated by the β ratio circuit forming transistor extraction unit 21 from the layout pattern data d2.

FIG. 3 is a plan view schematically showing layout pattern data d2 at a location corresponding to circuit connection data d1 in FIG. In the figure, 31 is a diffusion region, 32 and 33 are polysilicon regions, and an input signal INI is applied to the polysilicon region 33. Also, 34 is the AI power line, 3
5 is the AIGND line, 36 is the contact part, 37 is the output A
This is the I signal line. A region 38 where the diffusion region 31 and the polysilicon region 32 overlap is a gate formation region of the transistor Q1, and a region 39 where the diffusion region 31 and the polysilicon region 33 overlap is a gate formation region of the transistor Q2. From such layout pattern data d2, the β ratio circuit constant extraction unit 22 extracts the circuit constants of the transistors Ql and Q2 that constitute the β ratio circuit.
Channel length L3. L4, channel width W3. W4 is extracted and output to the β transistor gain coefficient ratio calculation unit 23 at the next stage.

The β transistor gain coefficient ratio calculation unit 23 calculates the
Impurity concentration of the semiconductor layer to be formed.

Using the process parameter d3, which is a parameter such as film thickness, the gain coefficient ratio of the β transistor is calculated based on the circuit constant of the β transistor obtained from the β ratio circuit constant extraction unit 22. The calculation procedure will be explained below using the β ratio circuits shown in FIGS. 2 and 3 as an example.

The gain coefficient β of a transistor is generally given by the following equation (1).

oxL L: Channel length W: Channel width μ: Effective surface mobility of electrons in the channel ε: Dielectric constant of gate oxide film 1: Thickness of gate oxide film x Note that μ is a constant and β transistor gain coefficient The ratio calculation unit 23 holds ε. t can be obtained from the process parameter x parameter d3, and L and W can be obtained from the layout pattern data d2 as described above. Based on this equation (1), transistors Ql, Q
2 each gain coefficient β1. By finding β2,
Find the gain coefficient ratio β1/β2.

In this way, the β transistor gain coefficient ratio calculation unit 23
calculates the gain coefficient ratio and outputs it to the gain coefficient ratio verification section 24. The gain coefficient ratio verification unit 24 uses the margin data d4
This margin data d4 is compared with the gain coefficient ratio fetched from the β transistor gain coefficient ratio calculation unit 23 to determine whether the electrical characteristics of the β ratio circuit are good or bad. The margin data d4 is set by being input by the designer from the input device 25, taking into account the margin (noise margin, etc.) necessary for the next stage logic gate of the β ratio circuit to operate normally.

In the β ratio circuits of FIGS. 2 and 3, transistor Q1. Margin data d of Q2 gain coefficient ratio β1/β2
4 is set to, for example, 175 or less, the gain coefficient ratio verification unit 24 considers that the operating conditions are sufficiently satisfied if the gain coefficient ratio β1/β2<115, and therefore the electrical If it is determined that the characteristics are "good" and if β1/β2>115, it is determined that the electrical characteristics of the β ratio circuit are "bad", and this determination result is output to the verification result output section 26. .

When the verification result output unit 26 obtains a “defective” determination result based on the determination result obtained from the gain coefficient ratio verification unit 24,
Names that identify transistors that are "defective",
An error list EL1 containing the gain coefficient of the transistor is output.

By outputting this error list ELI, the designer is prompted to modify the layout pattern.

FIG. 4 is a flowchart showing a verification procedure when the layout pattern verification system of the first embodiment shown in FIG. 1 is implemented by a microcomputer. The processing procedure will be explained below with reference to FIG.

First, in step S1, a logic simulation of a logic circuit defined by circuit connection data d1 is performed. and,
In step S2, it is verified whether the logic circuit operates normally in the logic simulation, and if it does not operate normally, an error message is output in step S3, prompting the designer to correct the circuit connection data d1, finish.

On the other hand, when it is confirmed in step S2 that the logic circuit defined by the circuit connection data d1 operates normally, the process moves to step S4, and in step S4, a resistance ratio circuit is formed from the circuit connection data d1. Extract the transistor (β transistor) that is

Next, in step S5, the channel length and channel width, which are the circuit constants of the β transistor obtained in step Sl, are extracted from the layout pattern data d2.

Then, in step S6, the gain coefficient ratio of the β transistor is calculated based on the circuit constant of the β transistor obtained in step S5 and the process parameter d3.

Thereafter, in step S7, the quality of the electrical characteristics of the β ratio circuit is determined by comparing the gain coefficient ratio obtained in step S6 with the margin data d4.

Next, in step S8, based on the judgment result obtained in step S7, if it is "good J", the process ends as is; if it is "bad", an error list EL1 is output in step S9, and the designer is instructed to change the layout pattern. prompt.

FIG. 5 is a block diagram showing a layout pattern verification system, which is a second embodiment of the present invention, for verifying the resistance ratio in a resistance ratio circuit that forms a ratio circuit using resistance ratios.

As shown in the figure, circuit connection data d1 of a logic circuit corresponding to a layout pattern for which layout verification is to be performed is taken into a logic circuit verification section 50. An example of the resistance ratio circuit of the circuit connection data d1 is schematically shown in FIG. As shown in FIG. 6, a resistor R1 and an n-channel MOS transistor Q3 connected in series are inserted between the power supplies V, . . . and ground.

A human input signal N2 is applied to the gate of the transistor Q3 whose source is grounded. The signal obtained from the node N2 between the resistor R1 and the drain of the transistor Q3 becomes the output signal OUT2.

In addition, the on-resistance value of transistor Q3, which is an expression value of charge supply ability, is relatively "small" (signal strength Strong
), and it is described that the resistance value of the resistor R1 is relatively "large" (signal strength Weak).

In this resistance ratio circuit, the L level input signal IN
When 2 is input, transistor Q3 turns off, so
■” level output signal 0υT2 is obtained. On the other hand, when input signal 1N2 of ■ level is input, transistor Q
3 turns on. Now, since the resistance value of resistor R1 is sufficiently larger than the on-resistance value of transistor Q3, it is certain that node N
2, an output signal OUT2 of L'' level is obtained. In this way, the resistor R1 and the transistor Q3 constitute an inverter of a resistance ratio circuit.

As described above, the circuit connection data d1, like the conventional circuit connection data D1, includes the width of the diffusion layer forming the resistor R1,
It does not specify dimensional characteristics such as length, channel length of transistor Q3, channel width, etc., and only specifies that the resistance value of resistor R1 is sufficiently larger than the on-resistance of transistor Q3.

The logic circuit verification unit 50 verifies that the logic circuit defined by the above circuit connection data d1 operates correctly by performing logic simulation. Therefore, the logic circuit verification unit 5o can confirm in advance whether the charge supply capability expression value and the like of the circuit connection data d1 are correctly described. That is, when the logic circuit verification unit 50 performs a logic simulation and determines that the logic operation of the logic circuit defined by the circuit connection data d1 is performed normally, the logic circuit verification unit 50 extracts a resistance ratio circuit forming element model using the circuit connection data d1 as it is. If it is determined that the logical operation is not performed normally, it outputs an error message EM2 to prompt the designer to correct the circuit connection data d1.

The resistance ratio circuit forming element model extraction unit 51 extracts element models such as resistors and transistors forming the resistance ratio circuit (in the example of FIG. 6) from the logic-verified circuit connection data d1 as shown in FIG. Resistor R1, transistor Q
3) is extracted, and the extracted element model is specified to the resistance ratio circuit constant extraction section 52 at the next stage.

The resistance ratio circuit constant extraction unit 52 extracts circuit constants of resistors, transistors, etc. in the element model designated by the resistance ratio circuit forming element model extraction unit 51 from the layout pattern data d2.

FIG. 7 is a plan view schematically showing layout pattern data d2 at a location corresponding to circuit connection data d1 in FIG. In the figure, 61 is a diffusion region, 62 is a polysilicon region, and input signal I is applied to the polysilicon region 62.
N2 is applied, and an output signal OUT2 is obtained from the region 61a in the diffusion region 61. Also, 63 is the AI power line, 6
4 is an ANGND line, and 65 is a contact portion. A region 66 where the diffusion region 61 and the polysilicon region 62 overlap is a gate formation region of the transistor Q3. From such layout pattern data d2, the resistance ratio circuit constant extraction unit 52 extracts the formation width W5 of the diffusion region 61 and the diffusion region 6, which are the circuit constants of the resistor R1 and the transistor Q3 in the element model constituting the resistance ratio circuit.
1 grows from the Ap power supply line 63 to the transistor Q3 (not shown), and the channel length of the transistor Q3 is L6.
, the channel width W6 is extracted and output to the resistance ratio circuit output voltage calculation section 53 at the next stage.

The resistance ratio circuit output voltage calculation unit 53 uses the same process parameter d3 as described in the first embodiment,
Based on the circuit constants of the element model extracted by the resistance ratio circuit constant extraction section 52, the voltage V 2 of the output signal OUT2 when the transistor Q3 is turned on with full swing is calculated. The calculation procedure for OUT2 will be explained below using the resistance ratio circuits of FIGS. 6 and 7 as an example.

First, the formation width W5 of the diffusion region 61. The resistance value R1 of the resistor R1 is determined from the shape growth 5 and the diffusion concentration of the diffusion region 31 obtained from the process parameter d3.

Next, the channel length L6. of transistor Q3. From the channel width W6 and the constant obtained from the process parameter d3, the transistor Q is calculated based on equation (1) as in the first embodiment.
A gain coefficient β3 of 3 is calculated.

Resistance value of resistor R1 R Gain of transistor Q3 1'' After determining the gain coefficient β3, as shown below, the voltage V of the output signal OUT2 when the transistor Q3, which is the driver of the resistance ratio circuit, is turned on at full swing is calculated. Calculate.If the input voltage at which the transistor Q3 swings at full UT2 is expressed by vlN, the current I flowing through the transistor Q3 is expressed by the following equation (2).

■Low β3・((vIN−vth)voU□2−(V
) 2/2) OUT2 °-(2) In equation (2), threshold voltage of transistor Q3 In equation (3), ε. : Dielectric constant of free space 8, relative dielectric constant of semiconductor substrate 9 : Amount of electron charge N : Acceptor impurity concentration φ : Semiconductor substrate potential 0 : Gate oxide film capacitance per unit area (-ε/1
)
N , φ , and co can be obtained from the process parameter SAB meter d3.

On the other hand, the on-resistance value R of the transistor Q3 is determined by the following equation (0).

If the power supply voltage is V, the output voltage V is C0OU
T2 R.

Then, by substituting equation (4) into equation (5), the output voltage v
oUT2 is determined by the following equation (6).

(ol Xll Il-ne%” L, “Fnonce 7 W
j 77% Input voltage v1N that turns on at full swing
By substituting vCc as vCc, the output voltage V can be obtained.

OUT2 In this manner, the resistance ratio circuit output voltage calculation unit 53 determines the voltage V of the output signal OUT2 when the transistor Q3 is fully swing-on, and outputs this to the output voltage verification unit 54. The output voltage verification section 54 takes in the margin data d4 and compares this margin data d4 with the output voltage V taken in from the resistance ratio circuit output voltage calculation section 53 to determine the quality of the electrical characteristics of the resistance ratio circuit. do. As in the first embodiment, the margin data d4 is input from the input device 25, taking into account the margin (noise margin, etc.) necessary for the next stage logic gate of the resistance ratio circuit to operate normally.
It is set manually by the designer.

In the resistance ratio circuit shown in Figs. 6 and 7, if the voltage V of the output signal OUT2 when the transistor Q3 is fully swing-on is set to 2° OUT2 5 (v) or less, the output Voltage verification section 5
4 is V. If U12<2.5, it is considered that the operating conditions are sufficiently satisfied, and therefore the electrical characteristics of the resistance ratio circuit are determined to be "good", and V. UT2〉2-
If it is 5, it is determined that the electrical characteristics of the resistance ratio circuit are "defective", and this determination result is output to the verification result output section 55.

Based on the determination result obtained from the output voltage verification unit 54, the verification result output unit 55 outputs a name for identifying the “defective” transistor and an output voltage V when a “defective” determination result is obtained.
Outputs error list UT2 EL2 in which is written. By outputting this error list EL2, the designer is prompted to correct the layout pattern.

FIG. 8 is a flowchart showing a verification procedure when the layout pattern verification system of the second embodiment shown in FIG. 5 is implemented by a microcomputer. The processing procedure will be explained below with reference to FIG.

First, in step Sll-, a logic simulation of the logic circuit defined by the circuit connection data d1 is performed. Then, in step S12, it is verified whether the logic circuit operates normally in the logic simulation, and if it does not operate normally, an error message is output in step S13, prompting the designer to correct the circuit connection data d1. ,finish.

On the other hand, if it is confirmed in step S12 that the logic circuit defined by the circuit connection data d1 operates normally,
The process moves on to step S14, and in step S14, element models such as resistors and transistors forming the resistance ratio circuit are extracted from the circuit connection data d1.

Next, in step S15, the circuit constants of the element model obtained in step S14, such as the diffusion width and diffusion length of the diffusion layer forming the resistor, the channel length and channel width of the transistor formation region, etc., are determined from the layout pattern data d2. Extract.

Then, in step S16, the output voltage when the driver transistor of the resistance ratio circuit fully swings on is calculated based on the circuit constant of the resistance ratio circuit obtained in step S15 and the process parameter d3.

After that, in step S17, by comparing the output voltage obtained in step 516 and the margin data d4,
The electrical characteristics of the resistance ratio circuit are judged to be good or bad.

Next, in step S18, if the determination result is "good" based on the determination result obtained in step S17, the process ends, and if the determination result is "bad".
In this case, an error list EL2 is output in step S19 to prompt the designer to change the layout pattern.

FIG. 9 is a block diagram showing a layout pattern verification system according to a third embodiment of the present invention for verifying the capacitance ratio of a charge sharing effect circuit that performs a predetermined operation using the capacitance ratio.

As shown in the figure, circuit connection data d1 of a logic circuit corresponding to a layout pattern for which layout verification is to be performed is taken into the logic circuit verification section 90. An example of the charge sharing effect circuit of the circuit connection data d1 is schematically shown in FIG. 1st
As shown in FIG. 0, an n-channel DD MOS transistor Q4.0 is connected in series between a power supply V and ground. Q5 is inserted. An input signal IN3A is applied to the gate of the transistor Q4 whose drain is connected to the power supply vDD, and an input signal IN3B is applied to the gate of the transistor Q5 whose source is grounded. Then, signal line 1 is connected to node N3 between the source of transistor Q4 and the drain of transistor Q5.
1 through n-channel MOSI-transistor Q6. Q7
The drains of each are connected to each other.

A write signal W is applied to the gate of the transistor Q6, and its source is connected via a signal line I2 to the gate of an n-channel MOSI transistor Q8 whose source is grounded. On the other hand, a read signal R is applied to the gate of the transistor Q7, and its source is connected to the drain of the transistor Q8. and,
The signal obtained from node N4 between the source of transistor Q7 and the drain of transistor Q8 is output signal OUT3.
becomes. In addition, the signal line 11, which is the charge supply capability expression value,
It is described that the capacitance C1 associated with the signal line 12 is relatively "1" (Large), and the capacitance JlC2 associated with the signal line 12 is relatively "Small".

In this charge sharing effect circuit, for a predetermined period, the input signal I
When one of N3A and IN3B is set to H'' and the other to L, and then both are set to L°, an H or L'' charge is accumulated on the signal line 11 depending on which transistor among transistors Q4 and Q5 is turned on. be done.

Thereafter, writing to the signal line 12 is performed by setting the write signal W to H'' level, turning on the transistor Q6 strongly, and supplying the charge accumulated in the signal line 11 to the signal line 12. Depending on the accumulated charge, transistor Q8 is turned on or off.

After performing the above writing, when the read signal R is set to H" level, if the transistor Q8 is in the on state, the output signal OUT3 is at the L level, and if the transistor Q8 is in the off state, the output signal is at the H" level. The signal OUT3 is output, and the contents stored in the signal line 92 can be read out.

In this way, the circuit shown in FIG. 10 can perform the memory operation because the capacitance C1 attached to the signal line 91 is "larger" than the capacitance C2 attached to the signal line 12, that is, the signal line! The premise is that the charge supply capability of the signal line I2 is sufficiently larger than the charge supply capability of the signal line I2. Because, Cl
This is because if <C2, sufficient charge cannot be supplied from the signal line 1 to the signal line 12 during writing (write signal W=H).

As described above, the circuit connection data d1 includes the channel lengths and channel widths of the transistors Q4 to Q8, and the signal line j! as in the first and second embodiments. 1.12, the dimensional characteristics such as the formation width and shape growth are not specified, and the capacity MC attached to the signal line 12 is not specified.
2, it is only clearly shown that the capacitance C1 attached to the signal line 11 is larger than the capacitance C1 attached to the signal line 11.

The logic circuit verification unit 90 verifies whether the logic circuit defined by the circuit connection data d1 described above operates correctly by performing logic simulation. Therefore, the logic circuit verification unit 90 can confirm in advance whether the charge supply capability expression value and the like of the circuit connection data d1 are correctly described. That is, when the logic circuit verification unit 90 performs a logic simulation and determines that the logic operation of the logic circuit defined by the circuit connection data d1 is performed normally, the logic circuit verification unit 90 uses the circuit connection data d1 as it is to create a charge sharing effect circuit forming element model. If it is determined that the logical operation is not performed normally, an error message EM3 is outputted to prompt the designer to correct the circuit connection data d1.

The charge sharing effect circuit forming element model extraction unit 91 extracts logic-verified circuit connection data d1 as shown in FIG.
From the element model forming the charge sharing effect circuit (10th
In the example shown, signal lines 11, 12 and signal line ! 1. ! 2 are extracted, and the extracted element model is specified to the charge sharing effect circuit constant extraction unit 92 in the next stage. The charge sharing effect circuit constant extraction unit 92 extracts the circuit constants of the element model specified by the charge sharing effect circuit forming element model extraction unit 91 from the layout pattern data d2, and outputs them to the next stage capacitance ratio calculation unit 93. . In the circuit example of FIG. 10, the circuit constants of the element model are the signal 1111.12 and the signal line 11.12.
Contact area Al between the insulating films formed below, A2, width a of the drain (source) diffusion region of transistors Q4 to Q8
4 to a8, length b4 to b8, gate area A4 to A8, etc.

The capacitance ratio calculation section 93 takes in the process parameter d3 necessary for the calculation, and calculates the capacitance ratio of the charge sharing effect circuit based on the circuit constant obtained from the charge sharing effect circuit constant extraction section 92. The calculation procedure will be explained below using the circuit shown in FIG. 10 as an example.

The capacitance C1 associated with the signal line 11 is determined by the following equation (7).

Cl-C+C+C+C+C 11435D 6D 7D (7) In the formula (7). C is the wiring capacitance of a capacitor consisting of the signal line 11, an insulating film formed under the signal line 11, and a semiconductor layer formed under this insulating film, and is given by the following (8
) can be calculated using the formula.

ε1 ε1: Dielectric constant of insulating film tl: Insulating film thickness ε1 and tl described above can be obtained from the process parameter d3, and A1 can be obtained from the layout pattern data d2 as described above. On the other hand, in equation (1), Cs4 is the source diffusion capacitance of transistor -1Q4, and C, 5 to CD7 are drain diffusion capacitances of transistors Q5 to Q7, respectively. Generally, the drain (source) diffusion capacitance Cd< can be calculated using the following equation (9). ICd-a-
b -Ca+2 (a+b)cp-・-(9)I C Nidrain (source) diffusion region 81 (82) and the semiconductor layer directly below it (Junction capacitance per unit area (see Figure 11)) (C Nidrain diffusion Junction capacitance per unit area between region 81 (82) and the surrounding semiconductor layer (see Figure 11) a Width of drain (source) diffusion region 81 (82) (see Figure 11) b = drain (source) Diffusion region 81 (82) length (see Figure 11) In equation (9), C and C are determined by the process parameters -p and d3 and the conductivity type of transistors Q4 to Q8. The conductivity type allowance is for transistors Q4 to Q in the layout pattern data d2.
8 can be obtained from the conductivity type of the diffusion regions forming each. Also, a.

As described above, b can be extracted from the layout pattern data d2. This formula (9) is c94CD5~C
It can be applied to all D7.

Further, the capacitance c2 associated with the signal line 12 is determined by the following formula [lO].

C2-C+C+C! 2 D8 8G =°(”)1
In equation 10), C is the wiring capacitance of a capacitor composed of the signal line 12, an insulating film formed under the signal line 12, and a semiconductor formed under this insulating film, and is expressed as the following (11) ) can be calculated using the formula.

ε2 C12−−φA2 ・−(11)ε2
: Dielectric constant t2 of insulating film: Insulating film thickness ε2. t2 can be obtained from the process parameter d3, and A2 can be obtained from the layout pattern data d2, as described above.

On the other hand, in equation (10), CD6 is the transistor Q6
is the drain diffusion capacitance, which can be calculated using equation (9),
08G is the MOS gate capacitance of transistor Q8,
It can be calculated using equation (12).

C-C-A8...(12)8G
.

C(-ε/1) is the same as in the second embodiment.
A8 can be obtained from the layout pattern data d2 as described above.

Using equations (7)2 to (12) described above, the capacitance ratio calculation unit 93 calculates the capacitance ratio C associated with each of the signal lines Il and 12.
Find 2/Cl.

In this way, the capacitance ratio calculation unit 93 calculates the capacitance ratio of the charge sharing effect circuit, and outputs it to the capacitance ratio verification unit 94. The capacitance ratio verification section 94 takes in the margin data d4 and compares this margin data d4 with the capacitance ratio taken in from the capacitance ratio calculation section 93 to determine whether the charge sharing effect circuit is good or bad. The margin data d4 is manually set by the designer from the input device, taking into consideration the margin necessary for the charge sharing effect circuit to operate normally.

In the charge sharing effect circuit shown in FIG. 10, the capacitance ratio C2/Cl between the capacitance C1 attached to the signal line 11 and the capacitance C2 attached to the signal line 12 is set to, for example, 1/M (M>1) or less. In this case, the capacity ratio verification unit 94 determines that the capacity ratio C2/CI<
If C2/Cl>1/M, it is considered that the operating conditions are sufficiently satisfied, and therefore the electrical characteristics of the electric field sharing effect circuit are determined to be "good", and if C2/Cl>1/M, , it is determined that the electrical characteristics of the electric field sharing effect circuit are "defective", and this determination result is output to the verification result output section 25.

Based on the determination result obtained from the capacitance ratio verification unit 94, the verification result output unit 95 specifies the name that specifies the element model, the capacitance ratio, and the surrounding element models when a determination result of "defective" is obtained. Outputs an error list EL3 in which names are written. By outputting this error list EL3, the designer is prompted to correct the layout pattern data.

FIG. 12 is a flowchart showing the verification procedure when the layout pattern verification system for capacity ratio verification, which is the third embodiment shown in FIG. 9, is realized by a microcomputer.

The processing procedure will be explained below with reference to FIG.

First, in step S21, a logic simulation of the logic circuit defined by the circuit connection data d1 is performed. Then, in step S22, it is verified whether the logic circuit operates normally in the logic simulation, and if it does not operate normally, an error message is output in step S23,
The designer is prompted to modify the circuit connection data d1, and the process ends.

On the other hand, if it is confirmed in step S22 that the logic circuit defined by the circuit connection data d1 operates normally,
The process moves on to step S24, and in step S24, an element model forming the charge sharing effect circuit is extracted from the circuit connection data d1.

Next, in step S25, the circuit constants of the charge sharing effect circuit obtained in step S24, such as the formation width of the signal line, the shape growth, the formation width of the drain diffusion region of the transistor, the shape growth, and the conductivity type of the channel, are determined. Extracted from layout pattern data d2.

Then, in step S26, based on the circuit constant of the charge sharing effect circuit obtained in step S25 and the process parameter d3, the capacitance ratio in the element model of two or more signal lines, etc., which requires a magnitude relationship of the capacitance ratio is determined. calculate.

Thereafter, in step S27, the capacitance ratio obtained in step S26 is compared with the margin data d4 to determine whether the electrical characteristics of the charge sharing effect circuit are good or bad.

Next, in step 528, if the determination result is "good" based on the determination result obtained in step S27, the process ends and the determination result is "bad".
In this case, an error list EL3 is output in step S29 to prompt the designer to change the layout pattern.

FIG. 13 is a block diagram showing a layout pattern verification system including the first to third embodiments of the present invention.

As shown in the figure, circuit connection data d1 of a logic circuit corresponding to a layout pattern for which layout verification is to be performed is taken into the logic circuit verification section 100.

The logic circuit verification unit 100 performs a logic simulation of the logic circuit defined by the circuit connection data d1.
Verify whether the logical operation is normal or abnormal. If it determines that the logical operation is normal, it outputs the circuit connection data d1 as is to the first data extraction unit 101, and if it determines that the logical operation is abnormal, it outputs an error message EMO and informs the designer. Prompts modification of circuit connection data d1. The first data extraction unit 101 extracts from the circuit connection data d1,
Charge supply ability (transistor gain coefficient, resistance value.

At least two verification elements (transistors, resistors,
A signal line having a capacitor function, etc.) is extracted, and the designation of the extracted verification element is sent to the second data extraction unit 102 in the next stage.
Performed against.

The second data extraction unit 102 extracts a reference circuit constant (a channel constant in the first embodiment), which is a circuit constant related to the charge supply capability of the verification element specified by the first data extraction unit 101, from the layout pattern data d2. length, channel width, and the like described above in the second and third embodiments) and outputs them to the verification data calculation unit 103 at the next stage.

The verification data calculation unit 103 calculates verification data (
gain coefficient ratio, output voltage, capacitance ratio, etc.) and outputs it to the verification data determination section 104 at the next stage.

The verification data determination unit 104 takes in the margin data d4, and uses this margin data d4 and the verification data calculation unit 103.
It compares the obtained verification data with the verification data to determine whether the electrical characteristics of the logic circuit formed by the designed layout pattern are good or bad, and outputs the determination result to the verification result output unit 105. The margin data d4 is set by the designer using the human-powered device 25, taking into consideration the margin necessary to prevent the entire circuit from malfunctioning.

Based on the determination result obtained from the verification data determination unit 104, the verification result output unit 105 outputs an error list ELO in which the verification element and verification data are described if a determination result of “defective” is obtained. By outputting this error list ELO, the designer is prompted to modify the layout pattern.

As described above, the layout pattern verification system of the present invention extracts at least two verification elements whose charge supply capabilities are defined in magnitude from the circuit connection data d1 and the layout pattern data d2, and calculates the charge of these verification elements. By calculating the verification data related to the supply capacity, it is possible to verify the electrical characteristics of the logic circuit formed by the layout pattern data.

As a result, it is no longer necessary to perform large-scale circuit simulations using circuit connection data of logic circuits corresponding to layout patterns, as was the case in the past. Electrical characteristics can be easily verified.

Furthermore, even if the circuit connection data d1 does not have dimensional characteristics such as the channel length and channel width of the transistor as in the past, the circuit connection data d1 can be formed by a layout pattern according to various dimensional characteristics obtained from the designed layout pattern data. Since it is possible to verify the quality of the electrical characteristics of the logic circuit, there is no longer a need to specify dimensional characteristics in the circuit connection data d1 as in the past, and when it is necessary to have a size relationship in the charge supply capacity, , it is only necessary to specify whether the charge supply capability is "large" or "small" for the element concerned.

Therefore, with the advancement of technology, aluminum wiring.

Even if the formation width of the polysilicon layer is miniaturized and the design rules of the wafer process are changed, there is no need to specify the dimensional characteristics in the circuit connection data d1, so the circuit connection data dl will change as the elements become smaller. There is no need to make any changes to it.

In addition, before verifying the electrical characteristics of the logic circuit formed by the layout pattern data, the circuit connection data itself of the logic circuit corresponding to the layout pattern is verified, so the electrical characteristics of the layout pattern data can be verified. However, this will not be done based on incorrectly written circuit connection data.

〔Effect of the invention〕

As explained above, according to the present invention, the verification data used by the verification data determining means when determining the quality of the electrical characteristics of the logic circuit formed by the layout pattern is extracted from the layout pattern data by the second data extracting means. Based on the reference circuit constants extracted from and the process parameters given by the process parameter giving means,
The data calculated by the verification data calculation means, that is,
This data was obtained without performing circuit simulation. Therefore, based on this verification data, the verification data determination unit can determine whether the electrical characteristics of the logic circuit formed by the layout pattern are good or bad, and the electrical characteristics can be easily determined even for the layout pattern of a large-scale logic circuit. This has the effect of being able to verify specific characteristics. Further, since the first data extraction means does not extract the dimensional characteristics of the circuit forming element from the circuit connection data, the circuit connection data does not need to have the dimensional characteristics of the circuit forming element. Therefore, as the degree of integration of logic circuits increases, it is no longer necessary to create circuit connection data again.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a layout pattern verification system according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a β-ratio circuit in circuit connection data, and FIG. 3 is a block diagram showing an example of a β-ratio circuit in circuit connection data. FIG. 4 is a flowchart showing the verification procedure of the layout pattern verification system according to the first embodiment of the present invention; FIG. 5 is a plan view showing the corresponding layout pattern data; FIG. 5 is the layout pattern according to the second embodiment of the present invention. A block diagram showing the verification system, FIG. 6 is a circuit diagram showing an example of a resistance ratio circuit in circuit connection data, FIG. 7 is a plan view showing layout pattern data corresponding to FIG. 6, and FIG. A flowchart showing the verification procedure of the layout pattern verification system according to the second embodiment, FIG. 9 is a block diagram showing the layout pattern verification system according to the third embodiment of the present invention, and FIG. 10 shows charge sharing in circuit connection data. 11 is an explanatory diagram of drain (source) diffusion capacitance; FIG. 12 is a flowchart showing the verification procedure of the layout pattern verification system according to the third embodiment of the present invention; FIG. 13 is a circuit diagram showing an example of an effect circuit; The figure is a block diagram showing a layout pattern verification system including the first to third embodiments, FIG. 14 is a block diagram showing a conventional layout pattern verification system, and FIG. 15 is a circuit diagram showing conventional circuit connection data. , FIG. 16 is a plan view showing a layout pattern corresponding to conventional circuit connection data. In the figure, 100 is a logic circuit detection verification section, 101 is a first data extraction section, 102 is a second data extraction section, and 10
3 is a verification data calculation unit, 104 is a verification data determination unit, 1
05 is a verification result output section, d1 is circuit connection data, d2 is layout pattern data, d3 is a process parameter, d4 is margin data, and ELO is an error list. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A layout pattern verification system that verifies the electrical characteristics of a layout pattern forming a predetermined logic circuit, which defines the connection relationship of elements forming the logic circuit and the magnitude relationship of the charge supply capacity of a specific element. circuit connection data providing means for providing circuit connection data that defines a layout pattern of the logic circuit; layout pattern data providing means for providing layout pattern data that defines a layout pattern of the logic circuit; a first data extraction means for extracting, from the circuit connection data, the specific element in which the magnitude relationship of the charge supply capacity is defined as a verification element; a second data extraction means for extracting a circuit constant related to the charge supply capability of the verification element as a reference circuit constant; and verification data representing the charge supply capability ratio of the verification element based on the reference circuit constant and the process parameter. A layout pattern verification system comprising: verification data calculation means for calculating; and verification data determination means for determining the quality of electrical characteristics of the logic circuit formed by the layout pattern based on the verification data.