JPH03145833A - Demodulator for spread spectrum signal - Google Patents

Abstract

PURPOSE:To suppress the influence of an interference wave not eliminated by inverse diffusion and the deterioration in a transmission error rate by obtaining the sample value total sum in a detection axis optimized in the sample timing, selecting the optimum total sum in the total sum to decide the data. CONSTITUTION:A gate circuit 102 is opened in response to the output of M-set of delay circuits 113 to fetch M-set sample data in the sample timing. A phase correction quantity calculation circuit 106 calculates the phase correction quantity being a mean value of its phase point (complex number plane). When a phase correction quantity 107 is given, a phase correction circuit 105 applies phase correction to the sampled data. Then each corrected data is summed by an adder circuit 109. Then the total sum of the corrected data in M-set of sample timings is fed to a maximum value selection circuit 110, where the sum with maximum absolute value is selected in each sum. Thus, the selected sum is used to decide a signal to output an information bit 111 being a soft decision sum output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a demodulating device for a spread spectrum signal by direct spreading transmitted via a communication line in which frequency selective fading exists.

[Conventional technology]

Conventionally, there has been a demodulation device configured as shown in FIG. 2, which is described in "Digital Mobile Communication Technology" (published by Japan Industrial Technology Center, p. 116) as a method of demodulating spread spectrum signals by direct spreading. Further, FIG. 3 is a diagram showing the time waveforms of signals at each stage in the configuration diagram of FIG. 2.

The operation will be explained below.

A spread spectrum communication system based on a direct sequence system is a system in which a carrier wave is product-modulated using a PN code whose bit rate is much faster than the highest frequency of an information signal. This PN code has the bit rate Rd (=
'ri is a code sequence with a much higher bit rate Rc (-Tc).

First, on the transmitting side, spread modulation is performed by multiplying the information signal 1 and the PN code 2, and the carrier wave is binary phase modulated using the spread modulated signal 3, and a signal 4 is transmitted. Here, the carrier wave modulation methods are 0° and 18°.
0° binary phase modulation is often used.

On the receiving side, a phase modulated wave 7 whose bandwidth has been restored (despread) is obtained by correlation detection between the same PN code 6 and the received wave 5 as on the transmitting side, and this is multiplied by the carrier wave from the local oscillator. As a result, the information signal 8 is reproduced.

When the communication device described above is configured using hardware, a configuration using a digital processing method is required from the viewpoint of stability, reliability, simplicity, etc. of the device.

In the case of digital processing methods, discrete sequences are handled in contrast to continuous sequences processed using analog methods, but it is important to be able to keep up with high-speed transmission speeds and to reduce the amount of calculations in order to realize the equipment. requirements, and the number of samples per chip (unit of spread-modulated signal sequence) is naturally limited. When the number of samples is limited in this way, it is necessary to suppress the noise mixed in at the time of sampling as much as possible.
Modulation method without spreading modulation/despreading in Figure 2)
This is achieved by extending the concept of a matched filter in chip units. That is, by shaping the waveform of the PN code on the transmitting side and performing the same operation as the waveform shaping performed on the transmitting side on the receiving side before sampling the chip, it is possible to minimize the influence of noise at the time of sampling. Fourth
The figure is from “Digital Communications” by Proakis.
cations) J, McGraw-Hill
- Old 11), 1983. This is an example configured to minimize the influence of noise at the time of sampling mentioned above. By using this method, it is theoretically possible to achieve the same transmission error rate characteristics even in the one-chip, one-sample method.

[Problem to be solved by the invention]

Conventional demodulators on the reception side for spread spectrum signals using direct spreading are configured as described above, and it is true that the minimum transmission error rate can be achieved for a given signal energy in a white Gaussian channel. This was the optimal demodulation method in this respect. However, this is not necessarily the optimal demodulation method when a spread spectrum signal is transmitted through a communication line where frequency selective fading exists, because if selective fading exists, interference If the delay time of the delayed wave component that becomes a wave is one chip duration (Tc) or more with respect to the desired wave component, the delayed wave component is However, if the delay time of the delayed wave component is less than or equal to T, despreading processing alone will completely remove the influence of the delayed wave component. Because interference components still exist even after despreading,
It was necessary to optimize for interference waves and noise. Furthermore, since the delay time of the delayed wave component and the phase difference between the carrier wave and the desired wave component are not always constant, it is necessary to take some measure to keep the transmission error rate low.

This invention was made to solve the above problems, and it is a spread spectrum signal that can suppress the influence of interference waves that cannot be completely removed by despreading, and can also suppress the transmission error rate. The objective is to obtain a demodulator for this purpose.

[Means to solve the problem]

A demodulator for a spread spectrum signal according to the present invention generates several sample timings, samples a despread output wave at each sample timing, and divides each sample component so that the sum of the signal component outputs is maximized. The phase of each component is corrected with respect to the detection axis, the sum of the phase-corrected sample components is calculated, the sum with the maximum absolute value is taken, and signal judgment is performed using that sum.

[Effect]

In this invention, with the above configuration, the signal is judged using the sum of the sample values sampled at the optimum sample timing and detected on the detection axis where the signal component output is maximum. It is possible to suppress the influence of interference waves that cannot be completely removed by despreading, and it is also possible to suppress the transmission error rate to a low level.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a demodulating device for a spread spectrum signal according to an embodiment of the present invention.

In the figure, 101 is a despread output wave, 113 is a delay circuit that generates sample timing 114, 102 is a gate circuit that takes in data according to the output of each delay circuit 113, and 106 is a phase that calculates the amount of phase correction. The correction amount calculation circuit 1°4 is a delay circuit that holds the sampled data 103 until the phase correction amount is calculated. A phase correction circuit 105 corrects the phase of sampled data using a phase correction amount 107 and outputs corrected sample data 108. 1o9 is an addition circuit that adds up the corrected sample data that has been subjected to signal processing. Reference numeral 110 denotes a maximum value selection circuit that selects the one with the largest absolute value among the sums of corrected data at each sample timing, and uses it to perform signal determination.

Further, it is assumed that the sample timing is M, the number of spreading chips is N, the 1-chip interval is Tc (=MDc), the 1-information bit interval is Th (=NTc), and the sample timing interval is DC.

Next, the operation will be explained.

Each of the M delay circuits 113 has a DC time delay such that Tc=MDc, and the gate circuit 102 is opened according to the output of each delay circuit. Data is taken in, that is, sample data at M sample timings are taken in.

Here, in taking in sample data at each sample timing 114, one sample is taken in for one chip, so N sample data are taken in for one information bit made up of N chips.

Next, the phase correction amount calculation circuit 106 calculates the phase correction amount, which is the average value of the phase points (complex plane), after taking in the N samples. At this time, the captured data is held in the delay circuit 104 until the phase correction amount is calculated. Then, when the phase correction amount 107 is given, the phase of the sampled data is corrected in the phase correction circuit 105.

Thereafter, the individual corrected data are summed by an adder circuit 109. Then, the sum of the corrected data at each of the M sample timings is sent to the maximum value selection circuit 110,
Here, the one with the largest absolute value is selected from among the individual sums, and the signal is judged using it to output the information bit 111 which is the soft decision addition output.

Next, FIG. 5 is a diagram for optimizing sample timing to increase the added value of sample data, and the optimization of sample timing will be explained using this diagram.

First, Figure (a) shows a signal wave (desired wave), and Figure (b) shows a delayed wave (interference wave). In this case, the delay time of the delayed wave is (3/4)Tc and the phase difference is 180°, and the input signal to the receiver has a waveform as shown in Figure (C) in which these signals are superimposed. When this is despread at the timing of the signal wave, the waveforms shown in Figures (d) and (e) are obtained. Here, the arrows shown in each figure indicate sample timing.

At this time, it is clear that there is a difference between sampling each chip at the sample timing shown in Figure (d) and calculating the total sum, and when sampling at the sample timing shown in Figure (e) and calculating the total sum. The sample timing shown in e) provides a larger output.

In other words, it can be seen that it is not necessarily optimal to sample at the center point of the chip of the desired wave depending on the delay time.

In addition, Fig. 6 is a diagram explaining the optimization of the detection axis by phase correction, and the phase locus diagram of the signal is shown in Figs. a
), vector S indicates a signal wave, and vector T indicates an interference wave. Further, the phase difference between the interference wave and the signal wave is indicated by φ.

When there is no interference wave, the phase locus of the signal is at points α and β.
However, due to interference waves due to fading, the phase locus of the signal becomes four points, A, B, C, and D. When the signal changes from α to β, the phase locus changes in the order of A, B, and C, and when the signal changes from β to α,
The phase trajectory changes in the order of C, D, and A. When this is despread, the changes in both phase trajectories become J, which changes in the order of L, M, and J, as shown in (). The timing of sampling in the phase locus that changes in this way to maximize the signal output is determined by the shape of the waveform, the delay time of the delayed wave, and the phase difference φ, and can be determined simply from Figure 6. However, for example, if the waveform shape is
In the case shown in the figure, the phase difference is not 180°,
In a case like φ in FIG. 6, data at point J can always be taken in at a certain sample timing. In this case, unless phase correction is performed, the added value of the sample data will be as shown in the figure (
It is N times the value corresponding to the distance from O to γ in b), but if it is done by phase correction, in this case the phase correction amount is θ in figure (b), and the detection axis is from the I axis in figure ( ). Since it becomes a straight line OJ, the added value of the sample data is N times the value corresponding to the distance from 0 to J, and it is confirmed that the added value output increases.

Note that the number of sample timings is defined by the waveform shape, applied line, hardware scale, etc., and is not defined in this invention.

Furthermore, even when selective fading does not exist or when the influence of interference waves caused by selective fading is removed by despreading, the demodulator according to the present invention can of course be applied, and in that case, a Gaussian channel Since the optimum sample timing in is set at the center point of the chip symbol of the signal wave, exactly the same effect can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the sum of sample values on the detection axis optimized at each sample timing is obtained, and the optimum sum value is selected from the sum for data judgment, so that the delay time is 1. This has the effect of suppressing the influence of interference waves that could not be removed by despreading when the chip duration ('rc) or less, and suppressing the deterioration of the transmission error rate.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a conventional method of demodulating a spread spectrum signal by direct spreading, and FIG. Figure 4 is a diagram showing time derivation; Figure 4 is a diagram showing a conventional example of a data judgment method using the one-chip, one-sample method; Figure 5 is a diagram explaining optimization of sample timing to increase the sum of sample data; The figure is a diagram illustrating optimization of the detection axis by phase correction. 101 is a despread output wave, 102 is a gate circuit, 103 is sampled data, 104 is a delay circuit, 105 is a phase correction circuit, 106 is a phase correction amount calculation circuit, 107 is a phase correction amount, and 108 is corrected sample data. , 109 is a sample data addition circuit, 110 is a maximum value selection circuit, 11
1 is a soft-decision information bit, 112 is a clock signal,
113 is a delay circuit, and 114 is a sample timing. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a spread spectrum signal demodulator that performs despreading, synchronous detection, and data determination of a spread spectrum signal by direct sequence transmitted via a communication line where frequency selective fading exists, one spread chip interval is set to M( ≧2)
A delay circuit that is divided into M pieces and generates sample timing for each chip interval, a gate circuit that extracts a despread output wave according to each sample timing output from the delay circuit, and each of the above samples. A phase correction calculation circuit that calculates the phase correction amount for each detection axis so that the sum of the components sampled according to the timing is the maximum; a phase correction circuit that performs phase correction of the phase correction amount, a delay circuit that holds the sample value while the phase correction amount of the detection axis is calculated by each phase correction amount calculation circuit, and a total sum of the phase correction sample values of each detection axis. and a maximum value selection circuit that selects the sum with the largest absolute value from among the sums of individual corrected sample values and uses it to make a signal determination. Spread signal demodulator.