JPH03145319A - Surface acoustic wave device - Google Patents
Surface acoustic wave deviceInfo
- Publication number
- JPH03145319A JPH03145319A JP28382089A JP28382089A JPH03145319A JP H03145319 A JPH03145319 A JP H03145319A JP 28382089 A JP28382089 A JP 28382089A JP 28382089 A JP28382089 A JP 28382089A JP H03145319 A JPH03145319 A JP H03145319A
- Authority
- JP
- Japan
- Prior art keywords
- saw
- silicon substrate
- bias voltage
- reverse bias
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010897 surface acoustic wave method Methods 0.000 title claims description 44
- 239000000758 substrate Substances 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000010408 film Substances 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 239000000969 carrier Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 4
- 230000001629 suppression Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 230000005284 excitation Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野コ
本発明はスペクトラム拡散通信方式に用いられる狭帯域
干渉波の抑圧用フィルタ等として好適な弾性表面波装置
の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a surface acoustic wave device suitable as a narrowband interference wave suppression filter used in a spread spectrum communication system.
[発明の概要]
高抵抗第1導電型シリコン基板の表面部にストリップ状
に形成された高濃度導電型層を有する弾性表面波装置に
おいて、上記高濃度導電型層に逆バイアス電圧を印加す
ることにより電流をほとんど消費せず弾性表面波の伝搬
損失を可変できるようにしたものである。[Summary of the Invention] In a surface acoustic wave device having a high concentration conductivity type layer formed in a strip shape on the surface of a high resistance first conductivity type silicon substrate, a reverse bias voltage is applied to the high concentration conductivity type layer. This makes it possible to vary the propagation loss of surface acoustic waves while consuming almost no current.
[従来の技術]
金属/ZnO/酸化物/Si構造の弾性表面波装置にお
いて、Si中にnoあるいはP0領域を形成して順方向
電流を流し、つまりキャリアを注入することにより弾性
表面波(SAW)の伝搬損失を変え、一種のSAWの可
変減衰器として動作可能にしたものが提案されており、
この装置は種々の機能素子の構成要素として有効である
。[Prior Art] In a surface acoustic wave device having a metal/ZnO/oxide/Si structure, a surface acoustic wave (SAW) is generated by forming a no or P0 region in Si and flowing a forward current, that is, injecting carriers. ) has been proposed to change the propagation loss of the SAW, making it possible to operate as a type of SAW variable attenuator.
This device is useful as a component of various functional devices.
第5図はかかるSAW装置の一例を示すもので、例えば
狭帯域干渉信号の除去装置のある一つの中心周波数をも
つ1チャンネル分のSAW素子として使用される。FIG. 5 shows an example of such a SAW device, which is used, for example, as a SAW element for one channel having one center frequency with a narrowband interference signal removal device.
同図において、1はP”(n”)Si単結晶基板、2は
るその基板上に形成されたp(n)型Siエピタキシャ
ル膜層、3はさらにその上に形成された熱酸化膜層、4
はその熱酸化膜層上に形成されたZnO圧電薄膜、 5
,6.7はその上に形成された金属電極で各々入力用表
面波櫛形トランスデユーサ、出力用表面波櫛形トランス
デユーサ及びゲート電極である。8はトランスデユーサ
の全屈電極下のp(n)型Siエピタキシャル膜層2内
に形成された高濃度不純物拡散領域であり、トランスデ
ユーサの励振効率を向上させる役目を果たすものである
。9はゲート電極7の下のp(n)型Siエピタキシャ
ル膜層2内に形成されたn” (P”)不純物拡散領域
であり、SAW伝搬路にそって第1のpnダイオードア
レイが形成されている。このpnダイオードアレイの動
作は、ダイオードバイアスの制御でエピタキシャル膜層
内のキャリア密度が制御され、SAWとキャリアとの相
互作用によりSAWの減衰定数を100 d B /
am以上も大きく変化させる役目を果たしている。つま
りチャンネルのオン・オフを高速に行う機能がある。In the figure, 1 is a P"(n") Si single crystal substrate, 2 is a p(n) type Si epitaxial film layer formed on the substrate, and 3 is a thermal oxide film layer further formed on it. , 4
is a ZnO piezoelectric thin film formed on the thermal oxide film layer, 5
, 6.7 are metal electrodes formed thereon, which are respectively an input surface wave comb transducer, an output surface wave comb transducer, and a gate electrode. Reference numeral 8 denotes a high concentration impurity diffusion region formed in the p(n) type Si epitaxial film layer 2 under the fully bent electrode of the transducer, and serves to improve the excitation efficiency of the transducer. 9 is an n''(P'') impurity diffusion region formed in the p(n) type Si epitaxial film layer 2 under the gate electrode 7, and a first pn diode array is formed along the SAW propagation path. ing. The operation of this pn diode array is such that the carrier density in the epitaxial film layer is controlled by controlling the diode bias, and the interaction between the SAW and the carriers increases the attenuation constant of the SAW to 100 dB/
It also plays a role in significantly changing the value of am. In other words, it has the ability to turn channels on and off quickly.
10は入カドランスデューサの外側のp (n)型Si
エピタキシャル膜層2内に形成されたn(p)不純物拡
散領域であり、第2のpnダイオードアレイが形成され
る。11はpnダイオードアレイに接続された抵抗、1
2はDC電源である。13は入力信号がSAWに変換さ
れ、第2のpnダイオードアレイで検波された電圧信号
モニタ一端子であり、そのチャンネル(周波数範囲)内
の入力信号の強度(電力)が電圧変化としてl[Il’
lされる端子である。14は第1のpnダイオードアレ
イのバイアス制御端子である。10 is the p (n) type Si outside the input quadrature transducer.
This is an n(p) impurity diffusion region formed in the epitaxial film layer 2, and a second pn diode array is formed. 11 is a resistor connected to the pn diode array, 1
2 is a DC power supply. 13 is a voltage signal monitor terminal where the input signal is converted to SAW and detected by the second pn diode array, and the intensity (power) of the input signal within that channel (frequency range) is expressed as a voltage change l[Il '
This is the terminal that is used. 14 is a bias control terminal of the first pn diode array.
第6図に入力信号の電力とモニタ一端子のバイアスシフ
ト量の関係を示す。バイアスシフト量はSAWの電力(
入力信号電力)の2乗に比例する。FIG. 6 shows the relationship between the power of the input signal and the bias shift amount of one monitor terminal. The bias shift amount is the SAW power (
It is proportional to the square of the input signal power).
このように入カドランスデューサ外側に設けたpnダイ
オードアレイによってSAWのポテンシャルが2乗検波
され、ベースバンド信号として入力信号強度が得られる
。In this way, the SAW potential is square-law detected by the pn diode array provided outside the input transducer, and the input signal strength is obtained as a baseband signal.
従って各々中心周波数の異なった上述のSAW素子を複
数チャンネル並列に接続して構成することで入力信号の
周波数スペクトル強度分布の情報が容易に得られる。Therefore, information on the frequency spectrum intensity distribution of the input signal can be easily obtained by configuring a plurality of channels of the above-mentioned SAW elements each having a different center frequency connected in parallel.
第7図に上述した構造のSAW素子をnチャンネルを並
列接続して成る適応型狭帯域干渉抑圧フィルタシステム
(A I S Fシステム: AdaptiveInt
erference 5uppression Fil
ter 5yste+*)の構成例を示す。FIG. 7 shows an adaptive narrowband interference suppression filter system (AIS F system: AdaptiveInt) consisting of n channels of SAW elements having the above-described structure connected in parallel.
erference 5uppression File
ter 5yste+*) is shown below.
第7図中の入カドランスデューサ群17と第2のpnダ
イオードアレイ群20で構成されている部分が、入力ス
ペクトラムの強度分布をモニターする部分である。入出
カドランスデューサ群17゜18が入力信号を周波数に
応じて分類し、伝搬させて、 再び合成する分類フィル
タ(sortingfilter)の機能を果たしてい
る。The part in FIG. 7 consisting of the input quadrature transducer group 17 and the second pn diode array group 20 is a part that monitors the intensity distribution of the input spectrum. The input and output quadrature transducer groups 17 and 18 function as a sorting filter that classifies input signals according to their frequencies, propagates them, and synthesizes them again.
各チャンネル毎に設けられたSAW伝搬路上の第1のp
nダイオードアレイ群19が各チャンネルのSAWの減
衰定数を制御する。The first p on the SAW propagation path provided for each channel
An n-diode array group 19 controls the attenuation constant of the SAW of each channel.
第7図のAI SFシステムの動作は次の通りである。The operation of the AI SF system shown in FIG. 7 is as follows.
入力信号が入カドランスデューサ群17でSAWに変換
され、第2のpnダイオードアレイ群20のバイアスシ
フト量をモニターしてそれに応じて、伝搬制御用の第1
のpnダイオードのバイアス電圧をバイアス制御回路2
1が制御するにのバイアス制御回路21の機能は、各チ
ャンネルの信号強度に応じた第2のpnダイオード20
のバイアスシフト量を増幅し、シフト址が大きいチャン
ネルのpnダイオード19のバイアスを逆方向にバイア
スすることである。または、単に増幅するだけでなく、
あるしきい値を設定して、比較器により第1のpnダイ
オード19のバイアスをON(順方向バイアス)、OF
F (逆方向バイアス)する機能を有する。The input signal is converted into a SAW by the input quadrature transducer group 17, and the bias shift amount of the second pn diode array group 20 is monitored and the first signal for propagation control is converted into a SAW signal.
Bias control circuit 2 controls the bias voltage of the pn diode.
The function of the bias control circuit 21 is to control the second pn diode 20 according to the signal strength of each channel.
The purpose is to amplify the amount of bias shift of , and bias the pn diode 19 of the channel having a large shift amount in the opposite direction. Or, rather than just amplifying
By setting a certain threshold value, the comparator turns the bias of the first pn diode 19 ON (forward bias) and OF
F (reverse direction bias) function.
[発明が解決しようとする課題]
さて上述した従来のSAW装置の動作原理ではキャリア
を注入するので、電流が流れ、消費電力が無視できない
。またキャリアとSAWのポテンシャルとの相互作用を
利用しているため、高温時でのキャリアの移動度が劣化
するので、高温時にSAWの損失が増大する欠点がある
。[Problems to be Solved by the Invention] According to the operating principle of the conventional SAW device described above, carriers are injected, so a current flows and power consumption cannot be ignored. Furthermore, since the interaction between the carriers and the potential of the SAW is utilized, the mobility of the carriers at high temperatures deteriorates, so there is a drawback that the loss of the SAW increases at high temperatures.
[発明の目的コ
従って本発明の目的は消費電流がほとんど無視できる程
度に低消費電力であると共に温度特性の良好な、電流を
流さないでSAWの損失を可変とした動作原理のSAW
装置を提供するにある。[Objective of the Invention] Therefore, the object of the present invention is to provide a SAW that has low power consumption to the extent that the current consumption is almost negligible, has good temperature characteristics, and has an operating principle in which the loss of the SAW is variable without flowing current.
We are in the process of providing equipment.
[課題を解決するための手段]
本発明のSAW装置は上記目的を達成するため高抵抗第
1導電型シリコン基板と、上記シリコン基板表面部にス
トリップ状に形成された高濃度第2導電型層と、上記シ
リコン基板上に形成された圧電膜と、上記高濃度第2導
電型層に逆バイアス電圧を印加する手段と、を備えたこ
とを要旨とする。[Means for Solving the Problems] In order to achieve the above object, the SAW device of the present invention includes a high-resistance first conductivity type silicon substrate and a high concentration second conductivity type layer formed in a strip shape on the surface of the silicon substrate. and a piezoelectric film formed on the silicon substrate, and means for applying a reverse bias voltage to the high concentration second conductivity type layer.
[作用]
高濃度第2導電型層に逆バイアス電圧が印加されると、
高抵抗第1導電型シリコン中に空乏層が拡がりキャリア
密度が極めて小さくなる。そのためSAWの伝搬損失を
キャリア注入せず、つまり電流を−流さずに極めて小さ
くできる。[Function] When a reverse bias voltage is applied to the high concentration second conductivity type layer,
A depletion layer spreads in the high-resistance first conductivity type silicon, and the carrier density becomes extremely small. Therefore, the propagation loss of the SAW can be extremely reduced without injecting carriers, that is, without flowing current.
[実施例]
以下図面に示す実施例を参照して本発明を説明する。第
1図は本発明によるSAW装置の一実施例を示す。同図
において、30は第1導電型シリコン基板、例えば50
〜5000Ω■のp (n)型Si基板、 31は該基
板の表面部のSAW伝搬路中にダイオードアレイを構成
するために、ストリップ状に形成された高濃度第2導電
型層をなしているn” (p”)拡散領域、32はオー
ミック電極、33はS io、絶縁膜34を介して又は
介さずに上記Si基板30上に形成された圧電膜、35
は上記圧電膜33上の上記領域31のほぼ真上に設けら
れた金属ゲート電極、36及び37は夫々入力及び出力
用トランスデユーサ、39及び40はトランスデユーサ
の励振効率向上用の高濃度不純物拡散領域である。[Examples] The present invention will be described below with reference to examples shown in the drawings. FIG. 1 shows an embodiment of a SAW device according to the present invention. In the figure, 30 is a first conductivity type silicon substrate, for example 50
A p (n) type Si substrate of ~5000Ω■, 31 is a highly concentrated second conductivity type layer formed in a strip shape in order to configure a diode array in the SAW propagation path on the surface of the substrate. n"(p") diffusion region, 32 is an ohmic electrode, 33 is Sio, a piezoelectric film formed on the Si substrate 30 with or without an insulating film 34, 35
is a metal gate electrode provided almost directly above the region 31 on the piezoelectric film 33, 36 and 37 are input and output transducers, respectively, and 39 and 40 are high concentration electrodes for improving the excitation efficiency of the transducer. This is an impurity diffusion region.
ゲート電極35にはシリコン表面がフラットバンドとな
るような電圧VGを印加する。A voltage VG is applied to the gate electrode 35 so that the silicon surface forms a flat band.
第2図は表面波(Acousto)−電気(Elect
ric)効果(以下AEと称する)によるSAW損失と
シリコン基板の抵抗率との関係を示す。なおこの実施例
ではシリコン基板はp型としたが、n型でも同様な特性
となる。第2図から明らかなようにSAWの損失を大き
くとるにはシリコン基板の比抵抗は50〜5000Ω■
のものが好適である。Figure 2 shows surface waves (Acousto) - electricity (elect).
ric) effect (hereinafter referred to as AE) and the relationship between the resistivity of the silicon substrate. In this example, the silicon substrate is of p-type, but the same characteristics can be obtained even if the silicon substrate is of n-type. As is clear from Figure 2, in order to increase the SAW loss, the specific resistance of the silicon substrate must be 50 to 5000 Ω.
Preferably.
さて、第1図の実施例において、n”(p”)拡散領域
31に、ゼロバイアス電圧あるいはわずかに順方向バイ
アス電圧−VBを印加すると、第2図から明らかなよう
にSAWの伝搬損失が極めて大きい。Now, in the embodiment shown in FIG. 1, when zero bias voltage or a slight forward bias voltage -VB is applied to the n''(p'') diffusion region 31, the propagation loss of the SAW increases as is clear from FIG. Extremely large.
次に上記拡散層31に逆バイアス電圧+vBを深くかけ
ると、高抵抗領域であるp型シリコン基板3o中に空乏
層38が拡がる。この空乏層38中にはキャリアがほと
んど存在しないので、上記AE相互作用による損失は無
視できるほど小さくなる。このようにSAWの伝搬損失
を制御するダイオードバイアスが逆方向バイアスである
のでシリコン基板30中には電流が流れないにもかかわ
らず、AE損失を極めて小さくすることができる。Next, when a reverse bias voltage +vB is deeply applied to the diffusion layer 31, a depletion layer 38 spreads into the p-type silicon substrate 3o, which is a high resistance region. Since almost no carriers exist in this depletion layer 38, the loss due to the AE interaction becomes negligibly small. As described above, since the diode bias that controls the propagation loss of the SAW is a reverse bias, the AE loss can be made extremely small even though no current flows in the silicon substrate 30.
第3図はダイオードアレイを構成するn゛拡散領域31
に逆バイアス電圧千■Bをかけ空乏層38を拡げた場合
の空乏層幅とAE損失の関係を示す。Figure 3 shows the n diffusion region 31 constituting the diode array.
The relationship between the depletion layer width and the AE loss when the depletion layer 38 is expanded by applying a reverse bias voltage of 1,000 B is shown.
同図から10μm程度空乏層が拡がると、AE損失はほ
とんど無視できること明らかである。It is clear from the figure that when the depletion layer expands by about 10 μm, the AE loss can be almost ignored.
第4図はn+拡散領域31に+Va=+10Vを印加し
て逆バイアス状態にした場合のキャリア分布を示し、縦
軸は深さ、横軸は距離をあられす。FIG. 4 shows the carrier distribution when +Va=+10V is applied to the n+ diffusion region 31 to create a reverse bias state, where the vertical axis represents the depth and the horizontal axis represents the distance.
同図より、空乏層は1o・μm以上拡がり+IOV程度
の逆バイアスでSAWの伝搬損失を極めて小さくできる
ことがわかる。From the same figure, it can be seen that the depletion layer spreads by 10.mu.m or more, and the propagation loss of the SAW can be extremely reduced with a reverse bias of approximately +IOV.
[発明の効果]
以上説明したように本発明によれば、SAWの損失が可
変であり、消費電流が非常に小さく、従って低消費電力
で温度特性の良好なSAW装置を提供できる。[Effects of the Invention] As described above, according to the present invention, it is possible to provide a SAW device in which the SAW loss is variable and the current consumption is very small, so that the SAW device has low power consumption and good temperature characteristics.
なお、本発明のSAW装置は、例えば、第7図に示す多
チャンネルの構成とすることにより、狭帯域干渉抑圧フ
ィルタとして使用できる。Note that the SAW device of the present invention can be used as a narrowband interference suppression filter by having the multi-channel configuration shown in FIG. 7, for example.
第1図は本発明の一実施例を示す概略図、第2図はAE
効果によるSAW損失とシリコン基板の抵抗率との関係
を示す特性図、第3図は逆バイアス電圧印加時の空乏層
幅とAE損失の関係を示す特性図、第4図は逆バイアス
状Jフ時のキャリア分右図、第5図は従来のSAW装置
の一例を示す概略図、第6図は第5図の装置における入
力信号の電力とモニタ一端子のバイアスシフト量の関係
を示す特性図、第7図はnチャンネルのSAW素子から
成る狭帯域干渉抑圧フィルタシステムを示す図である。
30・・・・・・・・・p(n)型シリコン基板、31
・・・・・・・・・n“(p+)拡散領域、33・・・
・・・・・・圧電膜、35・・・・・・・・・ゲート電
極、38・・・・・・・・・空乏層。FIG. 1 is a schematic diagram showing an embodiment of the present invention, and FIG. 2 is a schematic diagram showing an embodiment of the present invention.
A characteristic diagram showing the relationship between the SAW loss due to the effect and the resistivity of the silicon substrate, Figure 3 is a characteristic diagram showing the relationship between the depletion layer width and AE loss when a reverse bias voltage is applied, and Figure 4 is a characteristic diagram showing the relationship between the depletion layer width and the AE loss when a reverse bias voltage is applied. Fig. 5 is a schematic diagram showing an example of a conventional SAW device, and Fig. 6 is a characteristic diagram showing the relationship between input signal power and bias shift amount of one monitor terminal in the device shown in Fig. 5. , FIG. 7 is a diagram showing a narrowband interference suppression filter system consisting of n-channel SAW elements. 30...P(n) type silicon substrate, 31
......n"(p+) diffusion region, 33...
...Piezoelectric film, 35...Gate electrode, 38...Depletion layer.
Claims (1)
濃度第2導電型層と、 上記シリコン基板上に形成された圧電膜と、上記高濃度
第2導電型層に逆バイアス電圧を印加する手段と、 を備えたことを特徴とする弾性表面波装置。[Scope of Claims] A high-resistance first conductivity type silicon substrate; a high concentration second conductivity type layer formed in a strip shape on the surface of the silicon substrate; a piezoelectric film formed on the silicon substrate; A surface acoustic wave device comprising: means for applying a reverse bias voltage to the highly concentrated second conductivity type layer.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28382089A JPH03145319A (en) | 1989-10-31 | 1989-10-31 | Surface acoustic wave device |
US07/521,142 US5196720A (en) | 1989-05-15 | 1990-05-08 | Narrow band interference signal removing device |
GB9010364A GB2235105B (en) | 1989-05-15 | 1990-05-09 | Narrow band interference signal removing device |
FR9006001A FR2650925A1 (en) | 1989-05-15 | 1990-05-14 | DEVICE FOR REMOVING INTERFERENCE SIGNALS ON NARROW BAND |
DE4015620A DE4015620A1 (en) | 1989-05-15 | 1990-05-15 | DEVICE FOR ELIMINATING NARROWBAND INTERFERENCE SIGNALS |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28382089A JPH03145319A (en) | 1989-10-31 | 1989-10-31 | Surface acoustic wave device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03145319A true JPH03145319A (en) | 1991-06-20 |
Family
ID=17670572
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28382089A Pending JPH03145319A (en) | 1989-05-15 | 1989-10-31 | Surface acoustic wave device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03145319A (en) |
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1989
- 1989-10-31 JP JP28382089A patent/JPH03145319A/en active Pending
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