JPH03142777A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To eliminate the need for a special control circuit in an external part and to shorten average access time by providing a row register file between a memory cell array and a column data selector. CONSTITUTION:Between a memory cell array 7 and a column data selector 9, a row register file 8 is provided to combine plural row registers to store addresses and data while pairing an arbitrary row address and the data of a row block to be designated by the row address, and a control circuit 11 is provided to determine which row register is selected to be used out of the row register file 8, and to control data transfer between the memory cell array 7 and the row register and between the row register and the row data selector 9. Thus, memory capacity is made equivalent with a D-RAM or a ROM, performance is obtained with the average access speed close to that of an S-RAM and the necessity of the external control circuit is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory used in computers, word processors, etc., and particularly to a semiconductor memory for configuring a frame buffer in a graphics display device or an image processing device.

[Background Art] Technology related to semiconductor memory is rapidly developing, and efforts are being made to increase storage capacity and access speed. However, there is an increasing demand for semiconductor memories with even larger storage capacities and faster access speeds. However, semiconductor memories generally have contradictory characteristics in terms of storage capacity and access speed, and it is difficult to satisfy both requirements at the same time. in particular,
D-RA is a typical semiconductor memory commonly used.
M (Dynamic Random Access
Memory), S-RAM (Static
Random Access Memory) and R
OM (Read Only Memory) exists, but when compared with the same level of manufacturing technology, D-RA
Compared to 5-RAM, M and ROM have larger storage capacity but slower access speed.

Therefore, conventionally, in an attempt to satisfy the conflicting demands of storage capacity and access speed at the same time, a semiconductor memory called a D-RAM with high-speed access mode and a memory control method called a cache memory method have been used.

D-RAM with high-speed access mode is a general R-RA
M is loaded with control circuitry and has a special high-speed access mode. There are three typical types of high-speed access modes: nibble mode, high-speed page mode, and static column mode. Although there are some differences in the access methods, they are similar in principle. In a normal D-RAM, for each memory access, a selection is first made in the row direction, and then a selection is made in the column direction for memory cells arranged in a two-dimensional manner. The memory cell corresponding to the specified address is selected.

On the other hand, in D-RAM with high-speed access mode,
If it is known in advance that the current memory access will select the same row as the one selected in the previous memory access, the selection in the row direction has already been made, so the selection in the column direction is omitted and only the selection in the column direction is performed. . By doing this, the aim is to improve access speed.

On the other hand, memory control using the cache memory method is a method that attempts to take advantage of the advantages of both main memory, which consists of large-capacity memory, and cache memory, which consists of high-speed memory, in a hierarchical manner. be. By storing frequently accessed data in main memory in this cache memory,
Reduce access time to that data.

Cache memory configuration methods include a set associative method and a direct associative method, but here a fully associative method cache memory will be briefly explained using FIGS. 5a and 5b. The cache memory consists of two parts: a data memory section 51 that stores multiple words of data, and an address tag section 52 that stores an address indicating where the data is located in main memory. Here, the address tag section 52 is configured as an associative memory,
Comparison circuit 5 for manually entered address and address tag value
4, and if they match, a match signal is output. A pair of address tag and data memory is called one entry, and usually consists of one hundred or more entries.

Further, the size of the data memory in each entry is generally less than ten bytes.

When the processor makes a read access to the cache memory, the entered address 53 is divided into a tag part and an index part, and the tag part is entered into the address tag part 52. If any address tag outputs a match signal here, the data selected by the index section is read from the data memory in that entry and output to the data bus. If none of the address tags match, the data for that address does not exist in the cache, so the main memory is accessed again and the data is read.

This data is input to the processor via the data bus and is also input to the cache memory to update its contents.

In the case of write access, a write-through method or a copy-back method is generally used. In the write-through method, the cache memory and main memory are simultaneously updated each time a write access is made. In the copy-back method, only the cache memory is updated during write access, and the main memory is updated only when necessary.

The reason why these two writing methods are used is because of the problem of data identity.

In the case of a system with a multiprocessor configuration, there is a cache memory for each processor and a main memory as a common memory.
A common configuration is memory.

When a write access is performed in such a system, if only the cache memory is updated, the cache memory and main memory will be updated to the same address.
The contents of the memory will be different, causing an inconvenience. Therefore, the write-through method updates the main memory every time a write access is made. Normally, only the cache memory is updated, and the main memory is updated only when the updated address is accessed from another processor.・The copy-back method updates the memory.

By the way, hit rate and miss penalty time are factors that affect the performance of cache memory. A hit is an access completed in cache memory,
This is when the access to main memory is unnecessary, and if it is not hit, it is called a miss hit. The hit rate is the ratio of the number of accesses in which the cache is hit to the total number of accesses. The miss penalty time is the time required to access the main memory and update data in the cache in the event of a miss hit. In order to improve the performance of cache memory, it is necessary to increase the hit rate and reduce the miss penalty time.

[Problems to be Solved by the Invention] The above-described conventional D-RAM with a high-speed access mode can utilize the high-speed access mode only when accessing the same row continuously.

For example, in neighborhood calculations in image processing, it is necessary to access several rows of needle data alternately, but there is a drawback that no speed improvement effect can be obtained for such applications. Additionally, the device accessing the semiconductor memory must determine whether consecutive accesses are to the same row, but devices with such a function are not common. do not have.

In the memory system using the cache memory method described above, the main memory and the cache memory exist separately, so a problem of data identity occurs. That is, in the write-through type, the main memory must be accessed each time a write access is made in order to maintain data identity, resulting in a low hit rate. Also copy/
In the back method, the circuit for maintaining data identity becomes extremely complex, and the error penalty time also tends to increase.

Furthermore, in general, when the storage capacity of the cache memory is fixed, it is better to increase the size of the data memory per entry in order to increase the hit rate. but,
A paradox arises in that as the data memory becomes larger, the miss penalty time due to data transfer also increases.

Furthermore, in image processing, image data is often read in order, subjected to simple calculations, and then written again. In such a case, the image data cannot fit into the cache memory, so the cache memory at a certain point
It is easy to get into a situation where the contents of memory are only data that has been processed, and data that is to be processed from now on is not cached. In other words, even if a cache memory method is applied to image processing, the hit rate will not increase, and on the contrary, there is a high possibility that the speed will be slower than when no cache memory is used due to the miss penalty.

[Differences between the invention and the prior art] The problem with the prior art described above is that in a D-RAM with a high-speed access mode, its capability only extends to one row of the memory cell array, and that the high-speed access mode This is due to the fact that the accessing side must determine whether or not it can be used. Another problem with the cache memory method is that the cache memory and main memory are separate, and data must be transferred between them using an external bus.

Therefore, in the present invention, a row register file is provided between the memory cell array of the semiconductor memory and the column data selector, and the row register file is controlled in the same manner as the cache memory. Furthermore, by integrating all of these on one chip, much more information can be transferred to each other in a shorter time than using an external bus. This makes it possible to realize a large storage capacity semiconductor memory that does not require any special external control circuit and has an average access time faster than conventional ones.

As a result, high-speed, large-capacity semiconductor memory can now be used in fields such as image processing, where conventional high-speed access technology has been difficult to use.

[Means for Solving the Problems] As described above, in order to improve the average access speed without providing an external special control circuit, the semiconductor memory of the present invention is arranged in a two-dimensional matrix. a memory cell array; a row decoder for selecting a specific row block designated by a row address from within the memory cell array; and a row decoder for selecting a particular row block designated by a column address from within the block. In a semiconductor memory having a column data selector for selecting cells, a set of an arbitrary row address and data of a row block specified by the row address is arranged between the memory cell array and the column data selector. A line register file configured by combining multiple line registers configured to store data as
a control circuit that determines which row register to use from the row register file and controls data transfer between the memory cell array, the row register, and the row register and the column data selector; There is.

[Embodiment] Next, a first embodiment of the present invention will be described in detail with reference to the drawings. The first embodiment has a memory cell array with R
This is an example of the configuration of a semiconductor memory using OM and 5-RAM for the row register file.

FIG. 1 is a block diagram of the first embodiment, and FIG. 2 is a detailed block diagram of the control circuit in FIG. 1.

In Figures 1 and 2, 1 is a row address bus, 2 is a column address bus, 3 is a chip selector input (C3), 5 is a valid output, 6 is a row decoder, 7 is a memory cell array, and 8 is a Row register file, 9 is a column data selector, 10 is a column decoder, 11 is a control circuit, 12 is a data output buffer 7.15.16 is an ATD circuit, 17 is a timing generation circuit, 18 is an LRU circuit, 20...・21 is a main word line, 22...23 is a main bit line, 24...25 is a row word line, 26...27 is a row bit line, 28...29 is a column decode line, 30 3 is an associative output bus, 31 is a data bus, 32 is a lock signal to be executed, 3
3 is a column clock signal.

The operating principle of the semiconductor memory of the present invention will be explained.

In this first embodiment, a 64 kilobit ROM is used as the memory cell array 7, and a 1 kilobit S-RAM is used as the row register file 8.

The 16-bit address bus input from the outside is internally divided into two, an 8-bit row address bus 1 and an 8-bit column address bus 2, and row addresses are sent to the rows of the row decoder 6 and the row register file 8. To the address field and control circuit 11, the column address is input to the column decoder 10 and control circuit 11. Memory access operation is like this 2
This is done in two stages depending on the type of address.

In the first stage of memory access operation, the chip select signal 3 rises and changes in the row address are detected as ATD (Address Tran) in the chip selected state.
The detection is started by the location detection circuit 15. This detection result is input to the timing generation circuit 17 and transmitted to the entire circuit as a lock 32° column clock 33. All circuits operate according to these clocks.

First, the row decoder 6 selects 256 main word lines 20...21 corresponding to the input 8-bit row address.
Activate one. Memory Cell ♦ When the main word lines 20...21 are activated, the array 7 activates the corresponding row block and starts an operation for reading data in that row block.

At the same time, the timing generation circuit 17
Instructs the row address field of file 8 to start associative comparison. That is, the row address input is compared with the value of the row address field in each row register to determine if there is a hit. The comparison result is sent to the associative output bus 30 along with the row register number in case of a hit.
The signal is manually input to the LRU circuit 18 and the timing generation circuit 17 via the LRU circuit 18 and the timing generation circuit 17.

LRU (Least Recently Used
) The circuit 18 refers to the row address in each access, and selects empty row registers in which no data has been stored yet from the entire row register file 8, or registers that have been accessed in the past and have become less necessary. Execute the LRU algorithm to find a possible row register, and four row word lines 24...250 corresponding to that row register are executed.
This is a circuit that activates one.

When a row address input to the row register file 8 is hit, the row word line 24...2501 corresponding to the hit row register is activated by the function of the row register itself.
One is made active, and the process moves to the next second stage of memory access operation. The aforementioned row decoder 6 and memory cell
The operation in array 7 is forcibly terminated.

If the manually entered line address is a mistake or hit, LR
U circuit 18 selects one row register from row register file 8 by activating one of four row word lines 24 . . . 25 . Then, the data of the previously activated row block is transferred and stored into the data field of that row register via the 256 main bit lines 22...23 of the memory cell array, and the row address is - Store the row address in the field.

At the end of the first phase, the data of the row block corresponding to the specified row address is stored in the row register whose row word lines 24...25 are active.

The second stage memory access operation may be performed subsequent to the first stage, or may be initiated by ATD circuit 16 detecting a change in column address. First, the row register file 8 outputs the contents of the data field of the row register selected by the row word lines 24...25 to the column data selector 9 via 256 row bit lines 26...27. do. At the same time, column decoder 10 activates one of 256 column decode lines 28 . . . 29 in response to the manually entered 8-bit column address.

Finally, the column data selector 9 selects the row bit lines 26 and 29 corresponding to the activated column decode lines 28 and 29.
. . 27 is outputted onto the data bus 31 via the data output buffer 12. Access to this row register is similar to access to general 5-RAM.

The respective timings mentioned above are shown in FIG.

In FIG. 6, tdt represents the time from inputting a row address to the row decoder 6 until the data in the memory cell array 7 is stored in the row register file 8. td
2 represents the time it takes for the data in the row register file 8 to be output from the data output buffer 12. 1++ inputs a row address into the row address field of row register file 8, then performs an associative comparison to identify hits/misses.
Represents the time until human judgment is completed. Each has a relationship of taH<t a2<<t dt. The hit signal is a signal indicating that the row register is hit, and the valid output 5 is a signal indicating that the data output is valid.

The explanation will be given in descending order of access speed. In case of a miss hit, tds, in order to transfer the data of the memory cell array 7 to the row register file 8 from the change in row address.
Since it takes a time of td2 to output the data of the row register file 8 to the data bus 31, the access time becomes t(11+t(12). This access time is
This is approximately the same as the access time of a normal D-RAM. In the case of a hit, it takes time tdn to determine the hit, and time td2 to output data from the hit row register to the data bus 31, so the access time is ta.
It becomes s+td2. If only the column address is changed without changing the row address, the hit determination is also unnecessary, so the access time is td2. td2 is approximately equal to the access time of a normal 5-RAM.

Table 1 Next, the specific operation of the row register file will be explained using Table 1. In the row register entry in Table 1, a hyphen (-) indicates that the row register is empty, and a square frame (b) indicates the row register currently being accessed. In the current state, the data of the first block is stored in the zeroth row register, the data of the second row block is stored in the first row register, and the second and third row registers are empty (TO). T
1 to T4 in that state, the row address is set to 3. 1
．． This figure shows the change in the row address field when access is performed with a change of 4.5. While an empty row register exists, the data of the row block by the current access is stored there and row < (TLT3). If the value of the row address field matches the row address to be accessed, it is a hit, and the hit row register is directly accessed (T2). There is no space in the row register,
In the case of a miss hit, the contents of the row register indicated by the LRU output are replaced with the data of the row block by the current access (T4).

In this first example, if the access is a hit or a miss,
Depending on whether the hit occurs, the memory access speed seen from the outside will change. This access speed is valid output 5
can be known by indicating the valid period of output data. Normally, by connecting this valid output to the wait control circuit of the processor, it is possible to configure a system that automatically and appropriately responds to changes in access speed.

Next, a second embodiment of the present invention will be described with reference to the drawings.

3 is a block diagram of the second embodiment, and FIG. 4 is a detailed block diagram of the control circuit in FIG. 3, but FIG. 3 corresponds to FIG. 1 in the first embodiment. , FIG. 4 corresponds to FIG.

3 and 4, the differences from FIGS. 1 and 2 are as follows: 4 is a read/write manual, 13 is a data output buffer, 14 is a multiplexer, 19 is a refresh control circuit, and 34 is a data output buffer. A refresh address bus, 35 a write-back address bus, 36 an address select signal, and 37 a control field signal.

The second embodiment includes D/RAM in the memory cell array 7.
is an example of the configuration of a semiconductor memory using a 5-RAM in the row register file 8. In the first embodiment, the memory
Since ROM was used for the cell array, only read access was required.

In this second embodiment, by using a readable/writable RAM in the memory cell array, write access and refresh operations are newly required. Therefore, the explanation will also focus on this point.

First, the memory access operation is performed in three stages.

The first two steps are similar to the first embodiment.

That is, the first stage is data transfer from the memory cell array 7 to the row register file 8, or row address hit determination. The second stage is the data in the row register.
This is read/write access to the field. 4
256 column decode lines 28...2 in the row register selected by one row word line 24...250 of the book
90 Read/write access is performed to the memory cell indicated by one. This access is limited to the general 5-
It can be considered to be similar to accessing RAM. At this point, the write data has only been written to the row register and has not been written to the memory cell array 7.

The third stage is the write-back cycle. If there is no space in the row register file 8 and there is a miss hit, it is necessary to replace one of the row registers with the row address in the current access. At this time, if writing has been performed in the past to the row register to be replaced, it is necessary to write back the contents of the row register to the memory cell array 7. If there is no write, the contents of that row register can be discarded.

A control field is provided in the row register to determine whether a writeback needs to occur.

This control field stores information indicating whether there has been a write access to the row register.

(Hereinafter, blank space) Table 2 A specific write-back cycle will be explained with reference to Table 2. In the row register items in Table 2, a hyphen (-) indicates that the row register is empty, a square frame (b) indicates the sum of the row registers that are being accessed at that time, and W indicates that the row register is being written. - Indicates that there has been access. First, consider miss-hit access when there is an empty row register.

At this time, the data of the row block accessed in the first stage memory access operation is stored in the empty row register (TI, 72a, T3). The LRU circuit 18 then checks the number of remaining empty row registers.

If there are still free row registers, there is no need to perform a write-back cycle, so this memory access is terminated (TI). If there are no more free row registers, control is performed to make one row register free in preparation for the next miss-hit access. In other words, the control field of the row register specified by the LRU circuit 18 is checked, and the
If it indicates that there has been no access, the contents of that row register are discarded and a free row register is created (T 2
b).

Since this discard procedure is performed in the LRU circuit 18, timings T2a and T2b are performed at the same time. If there was a write access in the past, the value of the row address field of that row register is output to the write-back address bus 35. By inputting this to the row decoder 6 through the multiplexer 14 and selecting a row block for writing back, the contents of the row register are written back to the memory cell array (T4).

The above control is performed at the beginning of memory access.
This is to ensure that at least one row register is free and to reduce the penalty in the event of a miss hit.

By the way, D-RAM cells require refresh operations in addition to normal access. This means that there are 256 main word lines 20...2 for the memory cell array 7.
This can be done by activating 1 in turn at regular intervals. First, the refresh control circuit 19 uses a built-in timer to know when refresh is required. Then, when refresh becomes necessary, the timing generation circuit 17 is notified of this fact. The timing generation circuit 17 arbitrates between this refresh request and memory access, and if refresh is possible, inputs the refresh address from the refresh control circuit 19 to the row decoder 10 through the multiplexer 14 to perform refresh. If refreshing is not possible, wait until it becomes possible.

The non-refreshable timing is a period during which data is transferred between the memory cell array 7 and the row register file 8 due to a miss hit.

Conversely, if there is a memory access during the refresh period, if the access hits the row register file 8, the access can be made normally. Miss
If it is a hit, timing generation circuit 17 delays access to memory cell array 7 until refresh is completed.

In this second example, hits, misses.

The memory access speed seen from the outside changes due to competition with refresh. This access speed can be known by valid output 5 indicating the valid period of output data in the case of read access, or the period during which write data must be kept valid in the case of write access. Normally, by connecting this valid output 5 to the wait control circuit of the processor, it is possible to configure a system that automatically and appropriately responds to changes in access speed.

[Effects of the Invention] As explained above, according to the present invention, the storage capacity is
Equivalent to AM and ROM, average access speed is 5-RAM
We were able to create a semiconductor memory that has performance close to that of 2000 and does not require an external control circuit. In other words, if the access hits the row register file, it can be accessed at the same speed as 5-RAM, and even if it misses, the D-R
It can be accessed at speeds comparable to AM.

The present invention can be applied to a conventional D-RA with high-speed access mode.
Compared with M, the following advantages arise.

(1) High-speed access is possible even when accessing across multiple row addresses.

(2) Since comparison of row addresses is automatically performed internally, there is no need for judgment regarding row addresses on the accessing side.

Furthermore, compared to the conventional cache memory method, the following advantages arise.

(3) Since the memory cell array and row register file exist on one chip, data for one row block can be transferred at once using the internal bus. Therefore,
No bus neck problems occur due to data transfer.

(4) Since the entire circuit is on one chip, there is no need to consider data identity with main memory, unlike cache memory.

(5) Once a row is accessed, the entire row is stored in the row register file, so all subsequent accesses to the row will be hits. Therefore,
In the case of accesses with locality, the hit rate becomes very high.

Furthermore, as in the second embodiment, D is added to the memory cell array.
- When a RAM is used: (6) While the row register file is hit, access to the memory cell array is not performed, so there is a margin in the timing for the refresh operation.

For these reasons, memory for storing programs that has a high probability of accessing addresses continuously, and memory for images that require alternating access to multiple rows or sequential read/write processing of large amounts of data. The present invention is very effective in improving access speed.

In the embodiment, the memory cell array is 256.
Although the explanation has been given assuming that the number of rows and columns is 256 and the row register file is 4 rows, as is clear from the gist of the invention,
It is clear that the memory cell array may be generalized to m rows by n columns and the row register file to be two rows. Also, although the LRU algorithm is used to control the row register file, other algorithms may also be used.

The point is that when multiple row blocks are stored in a row register file, it is sufficient to be able to specify a particular row register for discarding or writing back.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a circuit configuration of a first embodiment of the present invention, FIG. 2 is a detailed block diagram of the control circuit in FIG. 1, and FIG. 3 is a block diagram of a second embodiment of the present invention. 4 is a detailed block diagram of the control circuit in FIG. 3, FIG. 5a is a block diagram showing the principle of a fully associative cache memory, and FIG. 5b is an address tag section. FIG. 6 is a timing chart for explaining the present invention in detail. 1...... Row address bus, 2......
. . . Column address bus, 6 . . . Row decoder, 7 . . . Memory cell array, 8 .
・・・・・・Row register file, 9・・・・・・・
...Column data selector, 10...Column decoder, 11...Control circuit, 15.16...ATD circuit, 17......・Timing generation circuit, 18...
・ ...LRU circuit, 20...21... Main word line, 22...
23... Main bit line, 24...25...
- Row word line, 26...27... row bit line.

Claims (1)

[Claims] A memory cell array arranged in a two-dimensional matrix, a row decoder for selecting a specific row block specified by a row address from the memory cell array, and a row decoder for selecting a specific row block specified by a row address from among the row blocks. A semiconductor memory having a column data selector for selecting a specific memory cell specified by a column address.
A row register file configured by combining a plurality of row registers configured to store an arbitrary row address and data of a row block specified by the row address as a set, between the array and the column data selector. , a control circuit that determines which row register from the row register file to use and controls data transfer between the memory cell array, the row register, and the row register and the column data selector. A semiconductor memory characterized by