JPH03142597A - Device and method for transmission processing - Google Patents

Abstract

PURPOSE:To reduce probability for erroneous data to be set by storing new processing data, which are sent from a central monitoring device, to the memory of a transmission processor in a terminal and updating a buffer based on the contents of the memory corresponding to an instruction from the central monitoring device. CONSTITUTION:The processing of data transfer between the central monitoring device and the terminal is executed through a control part 20 based on the processing data stored in the buffer built in the control part 20 of a transmission processor 10 on the terminal side. The new processing data to be sent from the central monitoring device are written into a non-volatile memory 21 of the processor 10 and corresponding to the command from the central monitoring device, the contents of the buffer are updated based on the contents of the memory 21. Accordingly, the change command can be outputted at the original logical address or transmission speed while specifying the transmission processor and the probability is reduced for the erroneous processing data to be set. Then, reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transmission processing device and a transmission processing method used in terminal devices and the like that transmit information to and from a central supervisory control device.

[Conventional technology]

In general, in monitoring and control systems such as disaster prevention systems and crime prevention systems, a central monitoring and control system mainly controls various detection devices such as temperature sensors, smoke concentration sensors, and security sensors, and various controlled devices such as alarms, which are placed in various parts of the building. Centralized monitoring and control is implemented. At this time, terminals are provided corresponding to the various detection devices and various control devices, and the central monitoring and control device connects the various detection devices and various controlled devices via the corresponding terminals. It is meant to be controlled. That is, the central supervisory control device transmits various commands for control to the terminal devices, and the terminal devices respond to these and send predetermined information back to the central supervisory control device.

Each terminal device processes commands and information transmitted to and from the central monitoring and control device, sends information from the pet detection device to the central monitoring and control device, or receives commands from the central monitoring and control device to be controlled. A transmission processing device is installed to perform processing such as giving information to devices, and the transmission processing device contains physical addresses, logical addresses, and transmission speeds so that address polling can be performed from the central monitoring and control device. They are set individually. For example, to perform the initial setting of a logical address, the central supervisory control unit first sends out a physical address, identifies the terminal with this physical address, and then changes the number of bits of the physical address (for example, 23 bits). A logical address is set for this terminal device by sending a logical address with a much smaller number of bits (e.g. 8 bits). After the logical address is set in this manner, the central supervisory control unit quickly polls the terminal device using the logical address, which has a smaller number of bits than the physical address.

By the way, when attempting to change the logical address or transmission speed, the central monitoring and control unit sends out the currently set logical address, identifies the terminal device with this logical address, and then changes the new logical address or transmission speed. However, with conventional transmission processing equipment, when a new logical address or transmission speed is sent, the terminal device transmits the data.
It was now stored directly in the same location where logical addresses and transmission speeds were previously stored.

[Problem to be solved by the invention]

As a result, even if the new logical address or transmission speed from the central monitoring and control unit is incorrect, the new logical address or transmission speed will be directly set on the terminal device. When the speed is set, the previously set logical address and transmission speed are erased, so the central monitoring and control unit sends the new logical address and transmission speed to the terminal so that the new data can be set correctly. If the new logical address or transmission speed is incorrectly set for some reason, it will not match the logical address sent from the central monitoring and control unit within this terminal device. In this case, there is a problem in that complicated operations and labor are required to index the terminal device.

The present invention makes it possible to easily check even if the logical address or transmission speed data sent from the central monitoring and control device is incorrect when changing the logical address or transmission speed. It is an object of the present invention to provide a transmission processing device and a transmission processing method that can significantly reduce the probability that a wrong logical address or transmission speed will be set and improve reliability.

[Means to solve the problem]

In order to achieve the above purpose, the present BJI provides a transmission processing device that performs transmission processing with a central monitoring and control device, which includes a control unit that performs predetermined control regarding transmission processing, and a writable The control unit includes a buffer in which data necessary for transmission processing between the central supervisory control device and the transmission processing device is set, and the memory includes a New data sent from the central supervisory control unit to change the set data is held, and the new data held in memory is set in the buffer according to instructions from the central supervisory control unit. It is now possible to do so.

Further, it is preferable that the memory is non-volatile and mounted on the same substrate as the control section.

Furthermore, as a transmission processing method, when the data necessary for transmission processing between the central supervisory control unit and the terminal device is set in the terminal unit, new data to change the data or the central supervisory control unit When the data is sent from the central monitoring and control unit, the terminal temporarily holds the new data and sets the new data in place of the old data when an instruction is sent from the central monitoring and control unit.

[Effect]

When a transmission processing device such as the one described above receives new data for changing the logical address or transmission speed from the central supervisory control unit, it holds this data for - hours and then returns it to the central supervisory control unit. In a central monitoring and control unit, for example,
After confirming whether the new data held in the transmission processing device is correct, a command is issued after confirming that the new data is correct. Based on this command, the transmission processing device changes the stored new logical address and transmission speed. Set the data in place of the old data and change the data. In the above procedure, the transmission processing device is set to the previous logical address and transmission speed until new data is set, so the central monitoring and control device identifies the transmission processing device using this logical address and changes the transmission processing device. Can issue commands.

[Actual travel example]

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a schematic block diagram of a supervisory control system to which a transmission processing device of the present invention is applied. Referring to FIG. 1, at least one terminal device 2 is connected to a central supervisory control device 1 via a common transmission line 3. As shown in FIG. FIG. 2 is a configuration diagram of each terminal device 2. As shown in FIG.

Each terminal device 2 includes a temperature sensor 1 a smoke concentration sensor, 1115
It is provided corresponding to each of the detection equipment 4 such as a crime sensor and the controlled equipment 5 such as a V alarm, and the terminal 2 receives information from the detection equipment 4 and sends it to the central monitoring and control device 1. A detection device 4. Analyzes the control sent and commands sent from the central monitoring and control device 1. A transmission processing device 10 that performs predetermined control on the controlled equipment 5, and processing that converts information TX sent from the transmission processing device 10 to the central monitoring and control device 1 into a form suitable for the central monitoring and control device 1@. An input/output circuit 11 that performs processing such as converting information as a command sent from the central monitoring and control device 1 into information RX in a format suitable for the transmission processing device 10.
and is provided.

FIG. 3(a) is a diagram showing an example of the format of a command sent from the central monitoring and control device 1 to the terminal device 2, and this command includes a header HD, a transmission type MT,
It includes address ADDR, data DT1, and return timing TM.

As will be described later, the transmission type MT is information for giving various types of instructions to the terminal device 2, and as the address ADDR, a physical address or a logical address can be specified. FIG. 3(b) is a diagram showing an example of the format of information sent from the terminal device 2 to the central monitoring and controlling device 1 in response to a command from the central monitoring and controlling device 1. Contains return data DT2 sent in response to timing TM.

FIG. 4 is a block diagram of the transmission processing device 10 of this embodiment, and the transmission processing device 10 includes a control section 20 that performs predetermined control regarding transmission processing, and a writable section 20 that holds predetermined information. A memory 21 is provided.

FIG. 5 is a diagram showing a more specific configuration example of the transmission processing device 10 shown in FIG. 4. Referring to FIG.
The reception interface 30 that receives X, and the transmission that stores the transmission type MT, address ADDR (physical address or logical address), and data DT1 sent following the header HD among the information Rx from the central supervisory control device 1, respectively. Type register 31. Address register 32.
The transmission type MT stored in the data register 33 and the f-transmission type register 31 is identified, and the transmission type M
A type identification unit 34 that performs control according to T, and a terminal device 2
A physical address buffer 35 in which a physical address specific to the terminal device 2 is set, a logical address buffer 36 in which a logical address specific to the terminal device 2 is set, and a physical address buffer 36 in which a physical address is stored in the address register 32. an address comparator 37 that compares the logical address with the physical address set in 35 and also compares it with the logical address set in the logical address buffer 36 when the logical address is stored in the address register 32;
Data D T 1 stored in the data register 33
Detection equipment 4. A digital signal is sent to the controlled device 5. When a latch circuit 38 that outputs a digital signal and a sensor that internally compares a detection signal with a predetermined value and outputs a digital signal are used as the detector 4, the digital signal D1 from the detection device 4 is input. digital signal D
When an analog sensor is used as the detection device 4 and three sampling circuits that perform sampling processing on the detection device 4, the analog signal A from the detection device 4 is input,
An A/D converter 40 that converts this into a digital signal, and return data in which data F from three sampling circuits or the A/D converter 40 or information F2 read from the memory 21 is stored as return data DT. The central supervisory control device 1 uses the register 41 and the return data DT stored in the return data register 41 as information TX.
a transmission interface 42 for transmitting to
The magnitude of the threshold value TH stored in the data F1 from the A/D converter 40 is compared with the magnitude of the data F1 from the A/D converter 40, and, for example, when the data F1 is larger than the threshold value TH, the alarm signals A, M are sent to the controlled device 5. The frequency division ratio is determined by the magnitude comparator 44 that outputs the data, the transmission speed buffer 46 that stores the transmission speed data when it is read out from the memory 21 as information F2, and the data of the transmission speed buffer 46. It is equipped with a black/yellow generator 45 having a frequency dividing circuit.

The writable memory 21 is, for example, an EEPROM, and the new logical address and transmission speed for change sent from the central supervisory control device 1 are written and stored in the memory 21, as shown in FIG. It is now possible to do so. In addition to the new logical address and transmission speed, threshold values, maintenance and inspection data, etc. may also be written.The new logical address and transmission speed held in the memory 21 may be written to the central monitoring and control unit The logical address buffer 36 and the transmission speed buffer 46 are read by the command from 1.
Either the data is transferred to the return data register 41 and stored there, or it is transferred to the return data register 41 and then sent back to the central supervisory control unit 1 via the transmission interface 42. Such switching control for writing to and reading from the memory 21 is performed by analyzing the transmission type MT from the central supervisory control device 1 in the type identification unit 34. The designation of the buffer and register to be transferred after reading the information, and the address of the memory 21 are designated based on data DT1 from the central supervisory control unit 1 held in the data register 33.

Next, a transmission processing procedure between the terminal device 2 having the transmission processing device 10 having such a configuration and the central supervisory control device (2) will be explained.

The transmission processing device 10 includes the central monitoring and control device 1 to FIG.
It operates when information in the format shown in a) is sent, and the operation mode at that time is the central monitoring and control unit 1.
is indicated by the transmission type MT.

When the transmission processing device 10 of this embodiment is used in the terminal device 2, the central supervisory control device 1 sets the transmission type MT to a predetermined location in the memory 21 of the transmission processing device 'It, 10 in addition to the existing mode. A mode MD1 in which information from the central monitoring and control device 1 is written to AD, and a mode M in which predetermined information is continuously written from a predetermined location AD in the memory 21 of the transmission processing device 10.
D2 can be newly defined.

FIGS. 7(a) and 7(b) are diagrams showing an example of the format of a command from the central monitoring and control unit 1 when modes MD and MD2 are specified, and in modes MD1 and MD2, for example, a logical address is used as the address ADDR. Specify the logical address set in the buffer 36. Further, as data D T , in mode MD1, information F2 to be written into the memory 21 and address AD of the memory 21 to which this information is written are specified, while in mode MD2, information read out from the memory 21 is specified. The buffer (or register) BUFF to which F2 is transferred and the address AD of the memory 21 to which this information F2 is successively output are specified.

Processing when such modes MD and MD2 are newly added and, for example, the logical address is changed using the memory 21 will be explained using the flowchart of FIG. Note that before this process is performed, a physical address unique to the terminal device 2 is preset in the physical address buffer 35, and the central monitoring and control device l identifies the terminal device 2 having this physical address by polling. Assume that the logical address buffer 36 is preset with a predetermined logical address sent from the central supervisory control device.

When attempting to change the logical address set in the logical address buffer 36, the central supervisory control device 1
In order to first hold the new logical address in the memory 21, a memory write command as shown in FIG. 7(a) is sent to the terminal device 2 (step Sl). At this time, transmission type M
T is mode MD1, the logical address currently set in the logical address buffer 36 of the terminal device 2 is specified as address ADDR, a new logical address is specified as information F2 of data DT1, and this address is specified as address AD. Specifies the address in memory 21 to which the new logical address is to be written. When such a memory write command is sent,
In each terminal device 2, the address comparator 37 first compares the logical address sent as the address ADDR with the logical address currently set in the logical address buffer 36. If the results match, it is determined that the address has been polled from either the terminal 2 or the central monitoring and control unit 1, and a new logical address is written to a predetermined location in the memory 21 of the terminal 2 (step S2).

Next, the central supervisory control device 1 issues a memory read command to the terminal device 2 as shown in FIG. 7(b) in order to confirm whether the new logical address written in the memory 21 is correct. transmit (step S3), at this time, the transmission type MT is mode M D 2, and the address ADDR
In this example, the same logical address as specified in step S1 is specified, the return data register 41 is specified as the buffer BUFF, and the address AD in the memory 21 in which the new address is written is specified. When such a memory read command is transmitted, the same terminal device 2 as specified in step S2 is specified by the address ADDR, and the new logical address written in the predetermined location of the memory 21 of this terminal device 2 is read. is read out and stored in the return data register 41, and then this new logical address is sent back to the central supervisory control device 1 via the transmission interface 42 (step S4).

The central monitoring and control device 1 confirms whether the returned new logical address is correct (step S5).

If this is not correct, it is determined that the new logical address was specified by mistake during transmission in step S1, and the process returns to step S1 to retransmit the correctly specified new logical address. .

In this way, in step S5, after confirming that the new logical address written in the memory 21 is correct, in order to transfer the new logical address written in the memory 21 to the logical address buffer 36, 7th
A memory read command as shown in FIG. Specify the logical address and
Also, the logical address buffer 36 is used as a buffer BUFF.
, and the address AD in the memory 21 where the new address is written is designated. When such a memory read command is sent, step 32. The same terminal device that was identified in S4 is identified,
The new logical address written in the predetermined location of this memory 21 is read out and stored in the logical address buffer 36. As a result, the logical address previously set in the logical address buffer 36 is changed to a new logical address, and after the logical address is changed, the terminal device 2 is polled by the new logical address from the central supervisory control device 1. Ru.

Also, when changing the transmission speed, this can be done using processing method III similar to that described above.

In this way, when attempting to change the logical address or transmission speed, in this embodiment, the new logical address or transmission speed sent from the central supervisory control device 1 is directly transferred to the logical address buffer 36 or the transmission speed buffer 46. The new logical address and transmission speed held in the memory 21 are sent back to the central monitoring and control unit 1 to confirm whether they are correct, and then the data is stored in the memory 21 without being written. Logical address buffer 36 and transmission speed buffer 4
6, the probability that an incorrect logical address will be set in the logical address buffer 36 due to a change or an incorrect transmission speed will be set in the transmission speed buffer 46 due to a change is significantly reduced. As a result, the reliability of the monitoring and control system can be significantly improved. The central monitoring and control device 1 also includes a terminal device 21
The above-mentioned series of verification procedures to determine whether the new logical address and transmission speed received at 11j are correct is performed by polling the terminal device with the logical address that has been set in the logical address buffer 36. Therefore, even if the new logical address or transmission speed for change received by the terminal device 2iP1 is incorrect for some reason, the central monitoring and control device 1 can change the specific terminal device without being affected by this. It can be determined immediately, and it is easy to check whether the new logical address and transmission speed that have been sent are correct, and if they are not correct, the correct logical address and transmission speed can be immediately resent. Can be done.

By providing the memory 21 in the transmission processing device 10 in this way, the logical address and transmission speed can be changed reliably and easily. At this time, the memory 21 only needs to be writable, such as the above-mentioned E
It does not have to be an EPROM, but may be an ordinary register with the necessary number of bits to hold data such as logical addresses and transmission speeds. Therefore, it is preferable to mount it on the same board as the control unit 20. Also, if it is inconvenient for the contents to be erased when the power of the terminal unit 2 is cut off for some reason, the memory 21 It is preferable to use a non-volatile memory 7, for example, an EEPROM as described above, thereby significantly increasing the security of the system. In addition, there are conventional transmission circuit technologies that incorporate memory, but in this case, they were used together with the CPU, and were configured to be external to the CPU, so they were not suitable for miniaturization. .

Further, the transmission processing device 10 configured as described above can also be realized using a one-chip CPU.

〔Effect of the invention〕

As explained above, according to the present invention, when new data for changing the logical address or transmission speed is sent from the central supervisory control unit, it is held for - time and when an instruction from the central supervisory control unit is received. Since the data is changed by setting it in place of the old data when the new logical address is set, it is possible to significantly reduce the probability that incorrect data is set and improve reliability. Until the change is made, the central monitoring and control unit can identify the transmission processing unit using the logical address before the change, so even if a new logical address for change is sent by mistake, the central monitoring and control unit will not be affected by this. It is possible to immediately identify a specific transmission processing device without having to do so, and it is possible to easily check whether the new logical address and transmission speed held in the transmission processing device are correct as described above.

Further, in the transmission processing device, if a memory for storing new data is provided on the same board as the control section, the device can be kept compact. Additionally, by making the memory non-volatile, system safety can be ensured.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a supervisory control system to which the transmission processing device of the present invention is applied, FIG. 2 is a configuration diagram of a terminal device, and FIG.
Figures (a) and (b) show the format of commands sent from the central monitoring and control device, and the format of information sent from terminals in response to commands from the central monitoring and control device, respectively. 4 is a block diagram of the transmission processing device,
5 is a diagram showing a specific configuration example of the transmission processing device shown in FIG. 4, FIG. 6 is a diagram showing an example of contents held in memory, and FIGS. 7(a) and (b) are modes. FIG. 8 is a flowchart showing the format of the command from the medium-fire monitoring control device when MD and MD2 are specified, and FIG. 8 is a flowchart showing the flow of the process for changing the logical address. 1... Central monitoring and control device, 2... Terminal device, 3...
Transmission line, 10... Transmission processing device, 11... Input/output circuit, 20... Control unit, 21... Memory, 36...
・Logical address buffer, 41...Return data register, 45...Clock generator, 46...Transmission speed buffer

Claims (1)

[Claims] 1) A transmission processing device that performs transmission processing with a central supervisory control device, the transmission processing device comprising a control unit that performs predetermined control regarding transmission processing, and a writable memory. The control unit has a buffer in which data necessary for transmission processing between the central supervisory control device and the transmission processing device is set, and the memory stores the data set in the buffer. The new data sent from the central supervisory controller to change the data is stored, and the new data stored in the memory is set in the buffer according to instructions from the central supervisory controller. A transmission processing device characterized by: 2) The transmission processing device according to claim 1, wherein the memory is nonvolatile and is mounted on the same substrate as the control section. 3) When data necessary for transmission processing between the central monitoring and control device and the terminal device is set in the terminal device, when new data for changing the data is sent from the central monitoring and control device, A transmission processing method characterized in that a terminal device temporarily holds new data and sets the new data in place of the old data when an instruction is sent from a central monitoring and control device.