JPH03141476A - Sorting device - Google Patents

Abstract

PURPOSE:To prevent such a case where the sorting of a processing object is affected by the break of a pattern, the noises, the rotation, etc., by securing an AND among the sorting data stored in blocks and deciding the sorting from an entire processing object. CONSTITUTION:The sorting data storage means 7a - 7d are provided to blocks B1 - B4 respectively and the bit length of these storage means are decided in response to the sorting number. An object is converted into the quantization data for each basic element and all quantization data are arranged in the prescribed order for production of the address information on the means 7a - 7d for each of blocks B1 - B4 consisting of selected basic elements. Then the accesses are given to the addresses shown by the produced address information and the bits corresponding to the sorting are set to the blocks B1 - B4 respectively. In a read state, the accesses are also given to the addresses shown by the address information and the sorting data are read out of the blocks B1 - B4. Then an AND arithmetic means 9 performs an AND operation for each corresponding bit and decides the sorting of an entire object. Thus the sorting is attained with high resistance to the noises and despite a partial defect of the object.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a classification device for classifying various processing objects such as characters, figures, sounds, control signals, etc., and in particular, the present invention relates to a classification device for classifying various processing objects such as characters, figures, sounds, control signals, etc. The present invention relates to a classification device that performs classification based on combinations.

[Conventional technology]

Pattern recognition is widely used in character recognition, graphic recognition, speech recognition, etc., and is recognized by classifying patterns into predetermined classification data. Various techniques such as a template matching method and a structural analysis method are conventionally known as pattern recognition techniques. The template matching method recognizes a pattern based on the degree of similarity between a part of a standard pattern prepared in advance and a part of an input pattern. On the other hand, the structural analysis method divides a pattern into predetermined blocks, analyzes the structure of the blocks based on a predetermined algorithm, and recognizes the pattern by combining them (for example, Japanese Patent Laid-Open No. 1-93874). ).

[Problem to be solved by the invention]

However, in the structural analysis method, constituent elements (=pixels) are divided into blocks during the recognition process, and judgments are made for each block, so if noise gets mixed into the block, there is a risk that judgment will become impossible, making it vulnerable to noise. . Furthermore, the structural analysis method has the problem of requiring a long time for computer processing for analysis processing.

Another problem common to both is that when humans recognize patterns, they consider the entire pattern when making a decision, so they can recognize the pattern even if the pattern has defects such as some chipping, adhesion of dust, dirt, etc. In the above-mentioned two conventional recognition techniques, recognition is performed by focusing on a part of the pattern or in accordance with a certain algorithm, so if a defect occurs in part of the pattern, it may not be recognized.

Furthermore, in the above-mentioned technology, pre-processing such as normalization processing is performed before processing, but if noise occurs due to defects in the pattern, the pre-processing will not be performed correctly, and subsequent processing will also not be performed correctly. there were.

The present invention has been made in view of the above circumstances, and when storing classified data in the classified data storage means, the target basic elements are divided into predetermined blocks, and the state quantities of all basic elements for each block are quantized. , arranges the quantized data in a predetermined order to generate address information, determines the bit length of the classification data storage means in relation to the classification, sets the bit corresponding to the target classification of the accessed address, and sets the bit length of the classification data storage means in relation to the classification, The data is stored as classification data, and when read, it performs an AND operation on the corresponding bits of the accessed address of each block, determines the entire object, and outputs the classification data, making it resistant to noise. It is possible to classify even when defects occur, and by performing recognition processing without using an algorithm, it is possible to prevent recognition errors caused by algorithms, and it is possible to perform high-speed processing with simple hardware. The purpose is to provide a classification device.

[Means to solve the problem]

The classification device according to the present invention classifies objects configured by combining basic elements based on state quantities indicating the states of the basic elements, and converts the state quantities into quantized data for each basic element. quantization means for converting, and address generation means for arranging quantized data of all basic elements of the block in a predetermined order for each block constructed by selecting the basic elements, and outputting it as address information of the block. and a classification data storage means provided for each block, accessed by the address information, and storing classification data in which a bit corresponding to the classification of the object is set, and the classification data storage means for all blocks, The apparatus is characterized by comprising a logical product calculation means for performing a logical product calculation for each corresponding bit of the classification data.

[Effect]

In the present invention, the classification data storage means provided for each block has its bit length determined in relation to the number of classifications, and when storing the classification data, converts the object into quantized data for each basic element, and converts the object into quantized data for each basic element. For each block configured by selecting , the quantized data of all the basic elements of the block are arranged in a predetermined order, address information of the classification data storage means of each block is generated, and the address indicated by the generated address information is accessed. Then, set the bits corresponding to the classification for each block. When reading, the address indicated by the generated address information is accessed, the classification data of each block is read out, and the logical product operation means performs a logical product operation for each corresponding bit to determine the classification of the entire object.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof. 1 and 2 are schematic block diagrams showing the configuration of a mark identification and classification device, which is a classification device according to the present invention. FIG. 1 shows the configuration when storing classification data, and FIG. The configuration at the time of classification is shown respectively. In FIG. 1, 1 is a mark that is an object for manually inputting classification data, and this mark 1 has a deviation that can be moved in three directions: up and down, left and right, and a rotational direction within a plane defined by the above two directions. It is attached to device 2. Mark 1 is 10 from O to 9
It is a diagram showing the numbers, and is classified into 11 types, 0 to 9 and 10 indicating unclassifiable.

The mark l attached to the deflection device 2 is, for example, 64 x 64
The image is captured by the camera 3 with a pixel resolution. The camera 3 converts the captured image of the mark 1 into an analog signal AS for each pixel and sends it to the binarization processing section 4. - The binarization processing unit 4 binarizes the analog signal AS for each pixel using a dark value TD sent from the CPU s, which will be described later. Binarized image signal BS
is given to the blurring processing unit 5, which is a quantization means, where it is subjected to blurring processing, and the image signal O5 of 64×64 pixels is converted into binary data BDI of 8×8 basic elements, with 8 pixels in the vertical and horizontal directions as basic elements. .

In the blurring process here, for example, if there are pixels of "1" in 8×8=64 pixels that are equal to or greater than a predetermined value a, the basic element is set to “1#”.

Binary data BDI of 64 basic elements from the blur processing unit 5
are four blocks Bl, B2 . consisting of 8 basic elements horizontally and 2 basic elements vertically. B3. It is given to the address generation unit 6 for each block B4, and the upper left of the binary data BDI for each block is MSB,
Four classification data storage units 7a, 7 are provided for each block based on 16-bit address information with the lower right being the LSB.
Generate a 16-bit address for b...

The bit length of the classification data storage units 7a, 7b, etc. is required to be equal to or greater than the number of classifications, and here, a RAM with a data length of 8 bits is used.
Two of these are used for one block, achieving a data length of 16 bits. Note that this is a RAM with a length of 11 bits or more.
Alternatively, any ROM may be used.

The classification data storage units 7a, 7b... are marks 1 to 1.
Mark the classification data of 0. When the mark l is "0", set the first bit, and when it is "9", set the 10th bit to "1".
This is to set and store the 11th bit when discrimination is not possible, and the classification data RD for each block that is accessed by the address information generated by the address generation unit 6 and stored therein. is output to a logical product operation section 9, which will be described later. The logical product operation unit 9 outputs the classification signal SD to the CPII 8 when storing the classification data, and outputs the classification signal SD to the CPU s
determines whether valid data has already been set at the accessed address.

Note that when the classification data is stored, nothing is stored there, so there is no classification data RO to be read out, and the CPU 8
The classification data WD is written by a write command R/-.

The CPU s outputs the dark value TD to the binarization processing unit 4, the write command R/W and classification data 〇 to the classification data storage units 7a, 7b, etc., and outputs the deviation signal D to the deviation device 2.
Output S. Further, the CPU s can directly output binary data BD2 to the address generation section 6. This is used when binary data BD2 that cannot be generated by imaging with the camera 3 is directly input to the address generation section 6.

This allows classification data to be written directly to unstored addresses in the classification data storage units 7a, 7b, . . . .

On the other hand, during the data classification shown in FIG. 2, the deflection device 2 is not necessary, and the binarization processing section 4 binarizes the data using a predetermined dark value. The binarized image signal BS is similarly processed by the blur processing unit 5 into 24if! of 8×8 basic elements. The data is converted into data BD1 and given to the address generation unit 6, where 16-bit address information is generated for each block, and the classified data storage units 7a, 7b, etc. are accessed, and the classified data 1 of the address is generated. The mouth is read out, and the logical product calculation unit 9
The imaged mark 1 is classified.

Is the logical product operation section 9 a classification data storage section? The classification data RD from a, 7b, etc. are subjected to an AND operation for each corresponding bit, and the mark 1 inputted into the classification of the bit whose result is "1" is classified.For example, the 7th bit of the operation result is is “1”
In this case, mark 1 is identified as "6#", and its classification signal SD="6" is output.

Next, the operation of the apparatus of the present invention configured as described above will be explained.

FIG. 3 is a flowchart explaining the storage operation of classification data by camera imaging, and FIG. 4 is step S2 in FIG. 3.
．． It is a figure explaining the processing content of S4.36. For example, when setting mark 1 of classification 8 for the first time, 1 (=8) is set in CPU 8 (step Sl). Next, when the mark 1 of classification 8 is attached to the deflection device 2, the mark 1 is imaged by the camera 3 (step S2). The mark l imaged by the camera 3 is output as an analog signal AS,
Binarization is performed using 64×64 pixels (step S3).

Next, the blur processing unit 5 binarizes with 8×8 basic elements (
Step S4). Then, the binary data BDI in the binarized state is divided into four blocks B1 . B2...
・, and arrange them in order from the beginning to provide address information for each block (for example, in FIG. 4, the first block B1 is "IC").
22") is generated (step S5). Next, based on the generated address, the classified data storage unit 7a for each block,
7b... is accessed, the classification data RD of each block stored therein is successively outputted to the AND operation unit 9, and the corresponding bit of each block (for example, the 9th
(bit), and check whether valid classification data is already stored there by checking whether the corresponding bit of the operation result is "l" (step S6).
. When no classification data is stored there, the 9th bit of the classification data storage sections 7a, 7b, etc. is set to "l" in order to store the classification data D="8" from the CPU s at that address. (Step S?). Further, if the classification data is already stored, step S7 is skipped.

At this time, for example, the first mark of "2' and "3"
Similarly, when the block address is “IC22”, the fourth
As shown in the figure, the 3rd and 4th bits are already set to "1", but since the 3rd and 4th bits are not set in other blocks, the result of the logical product is that the 9th bit is "1".
It will only become 1”.

Next, the CPU 8 determines whether or not deflection of the deflection device 2 is necessary (step S8), and if necessary, a deflection signal OS is output.
The deflection device 2 is deflected by a predetermined amount (step S9). Then, the operations from step S2 are repeated to generate address information. If the address obtained by the deviation is equal to the previously generated address, the answer is YES in step S6.
S, and the classification data WD is not written. If they are different, it is determined NO in step S6, and each classification data storage unit? The 9th bit of the generated address of a, 7b, . . . is set, and classification data WD="8" is written. Thereafter, deviation is performed within a certain range in the same manner, and the 9th bit of the generated address is set, and classification data WD="8" is written. Similarly, O~7.
Classification data is also written for marks 9 and 10.

Next, the storage operation of the classification data by the CPU 8 will be explained. Depending on the image taken by the camera 3, the classification data storage units 7a, 7
Since the classification data HO cannot be written to the entire address space of 2blind' (=65.536) of b-, the classification data storage unit ? A, 7b, . . . all addresses are generated, and an operator judges the classification data based on a pattern created by the addresses of each block and writes it into the classification data storage section 7a, 7b, .

FIG. 5 is a flowchart illustrating the storage operation of classification data by the CPU 8. First, set the address to 1 (step 510), and each classification data storage section 7a, 7
Read the classification data RD at address 1 of b... (step 511), performs an AND operation in the AND operation section 9, and depending on whether any bit of the operation result is "1", the data is read there in step S12. Determine whether classification data is already stored.0 If classification data is not stored, 8×
The bit pattern of 8 is displayed on the display of the CPU s, and the operator looks at the pattern to judge the classification data.Step 514) Inputs the classification data of 0 to 10, and stores the classification data storage units 7a and 7b at that address.・・・
・Set the corresponding bit to "1" and store the classification data (step 515), where the classification data="1"
0'' indicates that it is impossible to determine the classification of the displayed pattern. Then, the address is incremented by 1 (step 516), and it is determined whether access to all addresses has been completed (step 517), and it has not been completed. If so, return to step Sll and access the next address.
The process ends when all addresses have been accessed, and if the classification data has already been stored in step S12, steps 313 to 515 are skipped. In this way, some classification data is stored in the entire address space.

Next, the mark classification operation will be explained. FIG. 6 is a flowchart showing the classification operation. Operations from image capture by camera 3 to address generation (steps S21 to 5)
24) is the same as the classification data storage operation shown in FIG. 3, and the explanation thereof will be omitted. However, as the dark value in the binarization processing section 4, the center value at the time of storage operation is used. When an address is generated, the data storage unit is classified according to the generated address? a,
7b... is accessed, the classification data RD is read out (step knob 525), and is output to the AND operation unit 9, where the AND operation of the corresponding bits of each proc is performed (
step 526).

Next, it is determined whether the classification signal SD is "10' or not based on the calculation result in the AND calculation unit 9 (step 527), and when the classification signal SD="10' is output, it is impossible to distinguish mark 1. This is thought to be due to changes in the surrounding environment such as the illuminance of the mark surface and fluctuations in the darkness value, so C.
Based on instructions from PII 8, operating conditions such as changing the illuminance on the mark surface and changing the darkness value are performed (step 528).
, the image is taken again from step S21, and the classification is performed. Note that if the operating conditions are not changed during the classification operation, the CPU 8 is not required.

In this embodiment, the present invention was applied to a single identification and classification device that images and classifies marks, but the present invention is not limited to this and can be applied to various signals such as characters, voices, control signals, etc. that contain noise. It can be used in devices that classify and obtain output accordingly.

Further, in this embodiment, the classification data is stored in all addresses of the classification data storage unit, but the present invention is not limited to this, and the classification data does not necessarily need to be stored in all addresses, but the classification data is stored in the address. If you do not remember anything, it may be determined that it is impossible to determine.

〔effect〕

As explained above, in the present invention, the logical product of the classification data stored in blocks is taken and the classification is determined based on the entire processing target, so the classification of the processing target is affected by missing patterns, noise, rotation, etc. In addition to being less susceptible to such effects, preprocessing such as normalization is not required because the entire object is classified without using an algorithm during recognition, and failure to classify due to misrecognition caused by algorithms and preprocessing is avoided. . It can also be used in a control device that performs optimal control using signals obtained from various sensors, but even if the error rate would be high if sensor signals were processed individually, the present invention judges the error rate as a whole. It is possible to achieve a low level of Furthermore, since the object can be classified by accessing each classification data storage means once when classifying the object, an equivalent effect can be achieved in which high-speed processing is possible with simple hardware.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing the configuration of a mark identification and classification device, which is a classification device according to the present invention, when storing classification data;
FIG. 2 is a schematic block diagram showing the configuration of the mark identification device during mark identification and classification, FIG. 3 is a flowchart showing the storage operation of classification data by the camera, and FIG. 4 is step S2 of FIG. Figure 5 explaining the processing contents of S4 and S6.
The figure is a flowchart showing the storage operation of classification data by the CPU, and FIG. 6 is a flowchart showing the mark classification operation. Generation unit 7a, 7b... Classified data storage unit 9... Logical product operation unit

Claims (1)

[Claims] 1. In a classification device that classifies objects configured by combining basic elements based on state quantities indicating the states of the basic elements, the state quantities are converted into quantized data for each basic element. quantization means for converting; and address generation means for arranging quantized data of all basic elements of the block in a predetermined order for each block constructed by selecting the basic elements, and outputting the quantized data as address information of the block. and a classification data storage means provided for each block, accessed by the address information, and storing classification data in which a bit corresponding to the classification of the object is set; and the classification data storage means for all blocks; A classification device comprising: logical product operation means for performing a logical product operation for each corresponding bit of the classification data.