JPH03140997A - Display control device - Google Patents

Abstract

PURPOSE:To improve a plotting speed by executing the initialization of all shift count registers by one time of I/O access in the case of execution of a writing operation to display memories without using a shift function. CONSTITUTION:A CPU 10 sets data in color registers 20 to 25 and a bit mask register 26 in the case of the execution of writing of the data into the display memories 70 to 72. The shift count register 42 for controlling the bit mask shifter and the shift count registers 40, 41 for controlling the writing data shifter are initialized at one time by an initializing means 45 when the writing data and the bit mask data are not shifted. The execution of the plotting at the high speed is possible in this way.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a display control device suitable for a display unit of a personal combinator, a work stage controller, a word processor, etc. The present invention relates to a display control device for performing writing at high speed.

[Conventional technology]

As a method for writing to multiple display memories at high speed, Hitachi Personal Combitor 3316 Series B
As described in the 14HX hardware technical data (issued September 1985, pages 68 to 72), a color register is provided for each display memory, and the write data and bit mask data are shifted. There is a way to access display memory simultaneously.

The prior art of the first generation will be explained using FIG. 10.

10 is central processing! i device (CPU), 70.71.72
is display memory with bit mask function (hereinafter referred to as display memory)
, 20.21.22, 25.24.25 are color registers that hold data written to the display memories 70, 71.72.

26 is a bit mask register which holds bit mask data. 50.51.32.35,
'54.55 is a chic for shifting write data. tz, 40 is a shift count register that controls shifts of shifters 30, 32, and 34, and 41 is a shift count register that controls shifts of shifters 30, 32, and 34.
1.55.55 shift operation fife is a shift count register that controls. 50#i arithmetic unit p and shifters 30, 31, 32, 35, 34, and 35 shift the write data. 36 is a bit mask shifter that shifts bit mask data. Further, 42 is a bit mask shift count register that controls the shift operation of the bit mask shifter 36. 60 selects 4S with the selector, selects bit mask data 91 and write data 8B, 84, 85,
Output to display memory 70°71.72.

Next, the writing operation to the display memory 70 will be explained in detail. The CPU 1 writes data to the display memory 70.
G to the color registers 20 and 21. Also,
Bit mask data is also set in the bit mask register 26 from the CPU 10. The data in color registers 20.21 are shifted by shifters 30.51, respectively, based on the data set in shift count registers 40.41. The data 81.82 which is f-shifted by the shifter 30.51 is subjected to a :jD operation by the arithmetic unit 50, and the result becomes the final write data 85 to the display memory 70.

On the other hand, bit mask data for performing bit-by-bit write control' of write data is held in the bit mask register 26 and then shifted by the bit mask shifter s6 based on the set value of the bit mask shift count register 42. Only the 11° bit of this shifted bit mask data 91 is written.

Then, the write data 8S and the shifted bit mask data 91 are selected by the selector 60, and the display memory 70
Output to and write.

In the case of the display memories 71 and 72, data is written in the same manner as in the case of the display memory 70.

[Problem to be solved by the invention]

In the above conventional technology, even when data is written to the display memory without using the write data shift function or the bit mask shift function, after setting the data in the color register, as shown in the chart 311, Sequentially, shift count registers 40 and 41 are set to °0.
(refer to Figure 12), and further sets the bit mask shift count register 42K to “0” (for the first s
(see figure) is necessary. In other words, even if the shift function is not used, a setting process is required for the 5BO register so that no shift operation is performed.
After that, a write had to be made to the display memory. Therefore, there is a problem in that the overhead becomes large and the drawing process takes time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display control device that improves the method of writing to a display memory and can perform drawing at high speed.

Means for Solving Problem C] In order to achieve the above object, a display control device according to the present invention includes a central processing unit, a plurality of display memories, a bit mask shifter that shifts bit mask information, and a control device for controlling the bit mask shifter. In the display control device, the display control device includes a shift count register for shifting write data, a write data shifter for shifting write data, a shift count register for controlling the write data shifter, and a write control circuit for controlling write operations for the plurality of display memories. a shift count register for bitmask shifter control;
The present invention is characterized in that an initialization means is provided for initializing the shift count register for controlling the write data shifter and the shift count register at the same time.

[Operation] When writing data to the display memory, first the CP
U sets data in color register and bit mask example vinegar and others. This process is the same as the conventional one.

When writing data and bit mask data are not shifted, writing to the display memory can be performed by simply setting the reset register ["1"i] in the initialization means, as shown in chart 70 of FIG. .

If the shift count register and the bit mask shift count register can be reset independently, it is possible to cope with the case where only the bit mask data is shifted.

According to the present invention, when write data and bit mask data are not shifted, it is not necessary to set all the plurality of shift count registers as in the prior art, and it is possible to increase the speed of drawing.

〔Example〕

Examples of the present invention will be described in detail below.

First, the configuration of an embodiment of the present invention is shown in FIG.

10 in FIG. 1 is a CPU, and 70, 71, and 72 are display memories. 15 is a system clock generator.

12 is a system clock signal.

11 is I10 write command signal C or lower l0WC signal)
It is. 20, 21, 22, 23, 24, 25 are color registers that hold data from the CPU. 5O131, 52, 55, 54, 55 are shifted by shifter, color register 20.21.22.2S respectively
, 24.25. 26 is a bit mask register that holds bit mask data. 36 is a bit mask shifter, which shifts bit mask data.

40 is a shift count register that controls the shift operation of the shifter 5O152,54. 41 is shifter 51.3
This is a shift count register that controls the 5.35 shift operation. 42 is a bit mask shift count register which controls the shift movement of the shifter 56. 45
is initialization means for initializing the shift count registers 40 and 41 and the bit mask shift count register 42t at once. 50 is an arithmetic unit and a shifter 50
．． 31, 52, and 35, and the write data shifted in S4.55 is calculated. 60 is selected with the selector,
Bit mask data 91 and write data 85.84.
85 and output to display memories 70, 71, and 72. 105.106.107 are shift count register 40.41 and bit mask shift count register 42
This is the reset signal for

Next, the writing operation to the display memory according to the present invention will be explained. CPU 10 to color register 20.21.2
2. Set write data on 23.24.25.

Alternatively, the bit mask data is also set in the CPU 10 error mask register 26. The data in each color register is shifted to shifters 30, 31, 32, 55, 54, and 55 based on the data set in shift count register 40, 41. Said shifter 30%51.52
．． The data shifted by 55, 34.55 is calculated by the calculation unit 50, and the result is displayed in the display memory 70.7.
The final write data to 1.72 is 85, 84.85.

On the other hand, the bit mask data held in the bit mask register 26 is also shifted to the bit mask shifter 56 based on the set value of the one bit mask shift count register 42.

Then, the data is shifted to the write data 85.84.85, selected by the 9-bit mask data 91t-selector 60, and output to the display memory 70.71.72 for writing.

Here, if the write data shift and bit mask data shift functions are not used, the initialization means 45
Using the reset signals 105.106.107't'', it is possible to initialize the shift count register 40.41 and the bit mask shift count register 42 at once.

FIG. 6 shows the configuration of the initialization means 45. Initialization means 4
5 is a shift count reset register 105, a D clip 70 (hereinafter referred to as DFF), and an AND circuit 10.
Shift count reset register 105
After setting the data to system clock signal 12,
This circuit generates reset and reset signals 105, 106, and 107 for each clock. Shift count reset register 1
05 is composed of 7 lip-flops with a reset terminal.

The output signal 101 of the DFF 104 is l as shown in FIG.
The falling edge of 0WC9i911 becomes active low is delayed by one clock from 9, and becomes low by one clock, and becomes high by one clock delayed from the rising edge of l0WC signal 11. Therefore,
The reset M number 102 of the shift count reset register 105 goes low in synchronization with the falling edge of the xowe signal 11, meaning the reset is released, and goes high one clock delay from the rising edge 9 of the WC signal 11, meaning it is reset again. It takes. This shift count reset register 10'
5 is released, the l0WC signal 1
Data DO to D2 are taken into the shift count reset register 105 in synchronization with the rising edge 9 of 1. The value set in the shift count reset register 103 is the reset signal 105, 106, 10 to the shift count register 40, 41 and bit mask shift count register 42 for one clock until the reset is applied.
It is output as 7. Therefore, shift count register 40.41, bit mask shift count register 4
2 is initialized to readiness by reset signals 105, 106, and 107 from shift count reset register 105. That is, if 1111 is set as data DO to D2 in the shift count reset register 106 in the system shown in FIG.
6.107 is output and shift count register 40.4
1. All bit mask shift count registers 42 can be initialized.

As a result, when writing to the display memory without using the f'11''t shift function, all shift count registers can be initialized in one I10 as shown in the flowcharts of FIGS. 2 and 5. You can go there by accessing.

That is, FIG. 2 shows 70- when neither the write data nor the bit mask data is shifted. First, the color registers 20 to 25 and the bit mask register 26 are set (621, 822), and then the 11' (4th shift count reset register 10!1)
In the example in the figure, D2 to DO are all set to 1°) (8
25).

Therefore, writing to the display memories 70 to 72 is performed (82
4).

Figure 3 shows 7 when only bit mask data is shifted.
0-, and as in the case of FIG. In the example shown, the D.O.
1Dl only snow 1-) Set all (835). Next, after setting the shift amount in the bit mask shift count register 42 (S34), writing to the display memories 70 to 72 is performed (855).

In both 70- of FIG. 2 and FIG. 3, there is no need to initialize each shift count register separately as in the prior art shown in FIG. 11, and the drawing speed is about 1.5 times faster than the conventional method. can be done.

Next, FIG. 8 shows an embodiment of an initialization means 45 in which the reset signals of a plurality of shift count registers are combined into one, and FIG. 9 shows its internal configuration.

In this embodiment, as shown in FIG. 5, by writing -11t- to the Dθ bit of the shift count reset register 10S, the operation is similar to that of the embodiment shown in FIG.
It is possible to initialize the shift count registers 40, 41 and the bit mask shift count register 42 at once. Therefore, this embodiment also provides the same effect as the embodiment shown in FIG.

Although this embodiment has been described with reference to five types of shift count registers, the same effect can be obtained even when there are two or four or more types of shift count registers.

〔Effect of the invention〕

According to the present invention, when performing the write operation f')'' to the display memory without using the shift function, all shift count registers can be initialized with one I/O access. It is no longer necessary to initialize each shift count register separately in the conventional process 9, and the drawing speed can be improved.

In addition, the present invention requires only one I10 access instruction instead of multiple I/O access instructions in the conventional system, and thus the program capacity can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIGS. 2 and 5 are flowcharts explaining the procedure for writing to the display memory when the present invention is used, and FIGS. 4 and 5 6 is a diagram showing the bit configuration of the shift count reset register 105, FIG. 6 is a circuit diagram of the initialization means of FIG. 1, and FIG.
6 is a timing chart of the circuit of FIG. 6, FIG. 8 is a block diagram showing the configuration of another embodiment of the present invention, and FIG. 9 is a timing chart of the circuit of FIG.
10 is a block diagram showing the configuration of an embodiment of the prior art, FIG. 11 is a flowchart explaining the procedure for writing to the display memory in the case of the prior art, and FIG. 12 is a circuit diagram of the initialization means 45 shown in the figure. shift count register 40.410
Bit Configuration Diagram: FIG. 15 is a bit configuration diagram of the bit mask shift count register 42. Explanation of symbols 30.51.52.53.54.55.56...
・Shift count register 40.41...Shift count register 42・
...Bit mask shift count register 45.
...Initialization means 70.71.72...Display memory 103...
...Shift count reset register Fig. 12 Shift count registers 40, 41 Fig. 13

Claims (1)

[Claims] 1. A central processing unit, a plurality of display memories, a bit mask shifter that shifts bit mask information, a shift count register that controls the bit mask shifter, a write data shifter that shifts write data, and the write data. A display control device including a shift count register for controlling a shifter and a write control circuit for controlling write operations to the plurality of display memories, the shift count register for controlling the bit mask shifter and the shift count for controlling the write data shifter. 1. A display control device comprising initialization means for initializing a register and a register at once.