JPH03129986A - Video signal transmitting equipment - Google Patents

Abstract

PURPOSE:To efficiently transmit a video signal by converting the moving vector of plural frames into the moving vector of one frame to transmit the obtained vector in the case of transmitting the moving vector of a prescribed frame separated from a reference frame by plural frames. CONSTITUTION:In the case of detecting a moving vector MV3P from the reference frame A0, executing intra-frame coding processing using the vector MV3P and transmitting a video signal B3, the moving vector MV3P of a frame B3 separated from the reference frame A0 by plural frames is converted into the moving vector of one frame from the reference frame A0 up to the frame B3 separated from the frame A0 by plural frames, the optimizing processing of the converted moving vector is executed and the processed result is transmitted. Consequently, the partial deterioration of picture quality can be suppressed and the video signal can be highly efficiently transmitted.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Outline of the invention C. Conventional technology Problems to be solved by the invention (Figures 19 and 20)
Figure) Means for solving problem E (Figures 15 and 16) 1 Effect (Figures 15 and 16) Example G (Figures 1 to 18) (G1) Video signal transmission Principle (Figures 1 and 2) (G2
) Configuration of the embodiment (G2-1) Configuration of transmitter (Figure 3) (G2-2) Motion vector detection circuit (Figures 4 to 9) (G2-3) Run length Huffman? 'f coding circuit (IR10 diagram - 1st
(Figure 6) (G2-4) Configuration of receiving device (Figures 17 and 18)
(G3) Operation of the embodiment (64) Effects of the embodiment (G5) Other embodiments H Effects of the invention A Industrial application field The present invention relates to a video signal transmission device, and in particular to highly efficient encoding processing of moving video signals. This is suitable for application when transmitting data.

B. Summary of the Invention The present invention improves efficiency by converting a motion vector of a predetermined frame a plurality of frames away from a reference frame into a motion vector for one frame and transmitting the motion vector in a video signal transmission device. video signals can be transmitted.

C. Prior Art Conventionally, in so-called video communication systems that transmit video signals consisting of video images to remote locations, such as video conference systems and video telephone systems, in order to efficiently utilize the transmission capacity of the transmission line, The inter-frame correlation of the video signal is utilized, thereby increasing the transmission efficiency of significant information.

That is, on the transmitting device side, a motion vector is detected between frames, and deviation data between a frame image reproduced using the motion vector and the original frame image is transmitted together with the motion vector.

The receiving device reproduces the original frame image by displacing the frame image (hereinafter referred to as the reference frame) that is the reference for motion vector detection by the amount of the motion vector, and then adding the transmitted deviation data.

In this way, since there is a correlation between frames in the video signal, the transmission efficiency can be significantly improved compared to the case where the original frame image is directly transmitted.

D Problems to be Solved by the Invention By the way, when detecting a motion vector and transmitting a video signal in this way, it is necessary to transmit the frame image that is the reference for motion vector detection. A method of transmitting frame images using a transmission procedure as shown in FIG. 19 can be considered.

That is, one reference frame image aFM is subjected to, for example, intraframe encoding processing and transmitted.

On the other hand, for frame images F1, F2, F3, etc. that are continuous from frame image FM, the immediately preceding frame images FM, Fl, F2, and so on are set as the reference frame. Motion vector V,, V□, ■,...
...and transmit deviation data.

In this way, after the frame image F1 is reproduced from the frame image FM, the subsequent frame image F2 can be reproduced based on the reproduced frame image F1, and successive frame images can be transmitted with high efficiency. .

In this method, the next frame image is reproduced based on the immediately previous frame image, so if a -long transmission error occurs, the error propagates to the subsequent frame image.

For this reason, for example, a transmission procedure as shown in FIG. 20 can be considered.

That is, for each predetermined frame, the frame image FM is subjected to intra-frame encoding processing and transmitted.

Furthermore, the frame image FM and the frame images Fl, F between the frame images to be subsequently subjected to intra-frame encoding processing and transmitted.
2. In F3..., frame image FMI
The motion vector and deviation data are transmitted based on the .

In this way, error propagation can be prevented and image quality deterioration can be effectively avoided.

However, in this method, if the motion vector V1 is detected within a range of ±7 pixels between frame images FM and 11, for example, the motion vector V1 is detected within a range of ±14 pixels at maximum between frame image FM and the following frame image F2. It is necessary to detect 2.

Furthermore, between frame images FM and FM 13, it is necessary to detect motion vector v3 within a range of ±21 pixels at most, and there is a problem that the code length of the motion vector to be transmitted increases accordingly.

One method to solve this problem is to encode the motion vector so that the code length becomes shorter for a value with a higher probability of occurrence when transmitting the motion vector (i.e., by optimization processing). is possible.

However, when transmitting motion vectors between one frame, two frames, etc., each motion vector value has a different probability of occurrence, so a simple configuration can reduce the overall amount of data. There was a problem that it was not possible to perform optimization processing to make the value smaller.

The present invention has been made in consideration of the above points, and when transmitting motion vectors between frames separated by multiple frames,
This paper attempts to propose a video signal transmission device that can optimize and transmit motion vectors with a simple configuration.

Means for Solving Problem E In order to solve this problem, the present invention detects a motion vector MV3P from a predetermined reference frame AO, and performs interframe coding processing using the motion vector MV3P to generate a video image. In the video signal transmission bag W1 that transmits the signal VVN (B3), a plurality of frames 3 from the reference frame AO
The motion vector MV3P of the distant frame B3 is converted into a motion vector DVI for one frame from the reference frame AO to the frame B3, which is a plurality of frames 3 distant, and is subjected to optimization processing and transmitted.

Frame B is a plurality of frames 3 away from the action reference frame AO.
If the motion vector MV3P of No. 3 is converted into a motion vector DVI for one frame from the reference frame AO to frame B3, which is several frames away from the reference frame AO, the data has the same probability of appearance as the motion vector of the frame adjacent to the reference frame AO. It can be converted into .

Therefore, motion vectors of frames adjacent to the reference frame AO can be optimized and transmitted using a table similar to that of frames adjacent to the reference frame AO.
Accordingly, motion vectors can be transmitted efficiently with a simple configuration.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(Gl) Principle of Video Signal Transmission When the video signal encoding method according to the present invention is applied to a video signal transmission system, the video signal is transmitted using the method shown in FIG.

That is, the transmitter sequentially transmits frame data FO1Fl,
Continuous video signal DV of F2, F3...
FIG. 1(A)) is divided into predetermined frame groups and processed.

That is, in this embodiment, the transmitting device divides the frame data FO, Fl, F2, F3, . Transmit after intraframe encoding processing.

Here, the intra-frame encoding process executes a compression process that calculates the difference between pixel data adjacent one-dimensionally or two-dimensionally along the scanning line direction, and thereby the amount of data for each image. This is a process that uses compressed transmission frame data.

Therefore, in the receiving device, regarding the transmission frame data that has been subjected to the intra-frame encoding process, by sequentially adding up the transmission frame data of 5 frames and 1 frame, 1
Frame data for one frame can be reproduced.

On the other hand, the transmitter transmits frame data Fl, F2, F other than the first frame data FO1F6 of each frame group.
3... are subjected to interframe coding processing and transmitted.

Here, in the interframe encoding process, first a motion vector is detected between the frame data of the predicted frame serving as a reference and the frame data to be encoded, and then the frame data of 3 cough predicted frames is extracted by the amount of the motion vector. The displaced frame data (hereinafter referred to as prediction result frame data) is processed, and the deviation data between the prediction result frame data and the frame data to be encoded is encoded together with the motion vector to generate transmission frame data. It is the process of forming .

Therefore, in the transmitter, frame data F1, F2, and other frame data other than the first frame data FO and F6 of each frame group
Regarding F3..., motion vectors are detected for each predetermined predicted frame, and interframe encoding processing is performed.

Further, at this time, in the transmitting device, two predicted frames are allocated to each of the frame data F1, F2, F3, . . . , and a motion vector is detected for each predicted frame.

Furthermore, the transmitting device forms prediction result frame data from the frame data of each predicted frame based on the two detected motion vectors, and then interpolates the two prediction result frame data to create an interpolated prediction result frame. The data is formed, and the frame data with the smallest amount of deviation data is selected from the frame data of the prediction result and the frame data of the interpolated prediction result, and subjected to interframe encoding processing (i.e., selective prediction processing). Hereinafter, the frame data input manually before the frame data to be encoded is pre-predicted, and the frame data input after the frame data to be encoded is used as the predicted frame. A predicted frame is called post-prediction, and a prediction using frame data as a result of interpolation prediction is called interpolation prediction).

As a result, the transmitting device selectively performs interframe encoding processing to minimize the amount of transmitted frame data, thereby improving transmission efficiency and transmitting video signals.

Furthermore, when performing interframe encoding processing, the transmitter first sets the frame data FO, F6, F6, and F12 before and after the fourth frame data F3 and F9 of each frame group as predicted frames. After performing interframe encoding processing (hereinafter referred to as level 1 processing)
, followed by the remaining frame data Fl, F2, F4, F5
...... frame data FO and F3 before and after it
, F3 and F6, . . . are set as predicted frames and subjected to interframe encoding processing (hereinafter referred to as level 2 processing).

In other words, interframe encoding processing has the characteristic that the amount of data to be transmitted can be reduced compared to intraframe encoding processing, so when transmitting a video signal, more frame data is subjected to interframe encoding processing. Then, the video signal as a whole can be transmitted with a smaller amount of data.

However, as the amount of frame data to be subjected to interframe coding increases, frame data of frames further away from the reference predicted frame must be subjected to interframe coding.

Therefore, motion vectors must be detected between frame data that are separated by that much distance, making motion vector detection processing complicated, and especially when performing selective prediction processing, the number of motion vectors to be detected increases. The configuration of the transmitting device becomes complicated.

However, as in this embodiment, frame data FO and F6 are set as predicted frames, and frame data F3 is
After first performing interframe encoding processing, the current frame data F3 and frame data FO, F6 are set as predicted frames, and the frame data F1, F2, F4 between them are
, F5, . . . , motion vectors need only be detected between comparatively close frame data, and the video signal can be efficiently transmitted with a correspondingly simple configuration.

Thus, in the level 1 interframe encoding process, the transmitting device sets the first frame data FO of the frame group and the first frame data F6 of the following frame group as predicted frames that serve as the reference for motion vector detection, and uses the previous prediction for each. and predict later.

In other words, the transmitter transmits the frame data FO and F6.
and the fourth frame data F3, motion vectors MV3P and MV for forward prediction and backward prediction, respectively.
After detecting 3N (Fig. 1(B)), the motion vector Mv
The frame data FO and F6 of the predicted frame are displaced by 3P and Mv3N to form the frame data FP and FN of the prediction results for the previous prediction and the subsequent prediction.

Next, the transmitting device linearly interpolates the frame data FP and FN to obtain frame data FPN as a prediction result for interpolation prediction.
form.

Furthermore, the transmitting device transmits frame data FP, FN and FP.
N and deviation data ΔFP, ΔFN of frame data F3
After obtaining ΔFPN and ΔFPN, the deviation data ΔFP, ΔFN
and ΔFPN, the deviation data Δ with the smallest amount of data
Select FP, ΔFN or ΔFPN to calculate motion vector M
Along with V3P and MV3N, transmission frame data F3X
(Fig. 1 (D)).

In this manner, the receiving device reproduces the original frame data FO and F6 from the transmission frame data FOX and F6X formed by intraframe encoding processing, and then reproduces the reproduced frame data FO, , F6 and transmission frame data F3X. Based on this, the original frame data F3 can be reproduced.

On the other hand, in level 2 processing, the transmitter transmits the first and second frame data F of each frame group.
1 and F2, F7 and F8, . . . , the first frame data FO and F6 and the fourth frame data F3 and F9 are set as predicted frames, and forward prediction and backward prediction are performed, respectively.

Therefore, in the transmitter, frame data FO and F
3, the motion vectors MVIP and MVIN,M
After detecting V2P and MV2N (FIG. 1(C)), the motion vectors MVIP and MVINSMV2P and M
Based on V2N, frame data FP and FN of prediction results are respectively formed, and frame data FPN of interpolation prediction results is formed.

Furthermore, after obtaining deviation data ΔFP, ΔFN, and ΔFPN based on the frame data FP, FN, and FPN, respectively, the deviation data ΔFP, ΔFN, or ΔFPN with the smallest amount of data is selected from the deviation data ΔFP, ΔFN, and ΔFPN. , motion vector MvIP and MVI
N, MV2P and MV2N are converted into transmission frame data FIX and F2X.

Similarly, regarding the fifth and sixth frame data F4 and F5, FIO and Fll,...
The fourth frame data F3 and the first frame data F6 of the following frame group are set as predicted frames, and forward prediction and backward prediction are performed, respectively.

Here, the motion vectors MV4P and MV4N, respectively,
When MV5P and MV5N are detected, the transmitting device detects motion vectors MV4P and MV4N, MV5P and MV5N.
Based on the prediction result frame data FP,
After forming FN and FPN to obtain deviation data ΔFP, ΔFN and ΔFPN, from the deviation data ΔFP, ΔFN and ΔFPN, the deviation data ΔF with the smallest amount of data is obtained.
Select P, ΔFN or ΔFPN to calculate the motion vector Mv
4P, MV4N, MV5P and MV5N are converted into transmission frame data F4X and F5X.

In this way, the frame data is divided into 6 frames,
By transmitting a combination of intra-frame encoding processing and inter-frame encoding processing, frame data FO, F6, etc. that were transmitted after intra-frame encoding processing are reproduced, and the remaining frame data are sequentially transmitted. Therefore, even if an error occurs, it is possible to prevent the error from propagating to other frame groups, which makes it possible to apply it to compact discs and the like to transmit high-quality video signals with high efficiency. can.

Furthermore, even with reverse playback and random access, frame data can be reliably reproduced, image quality deterioration can be effectively avoided, and video signals can be transmitted with high efficiency.

Furthermore, in this embodiment, the transmission frame data FOX to F5X in each frame group are rearranged and transmitted in the order in which they are subjected to intra-frame encoding processing and inter-frame encoding processing (Fig. 1 (E)). At this time, each of the transmission frame data FOX to F5X is added with identification data representing the predicted frame data and the intraframe-encoded transmission frame data before being transmitted.

That is, for frame data F1, F2, F4, and F5, frame data FOSF3, F3, and F6 of predicted frames are required for encoding and decoding, respectively.

On the other hand, in frame data F3, frame data FO1 of the predicted frame is used for encoding and decoding.
F6 is required.

Therefore, as shown in FIG. 2, in the transmitting device, if frame data to be intra-frame encoded is represented by symbol A, and frame data to be processed at levels 1 and 2 are represented by symbols B and C, transmission frame data DATA ( (Figure 2 (A
)), frame data AO5B3, C1, C2, C4
, C5 are output in sequence.

At this time, the transmitting device sends a prediction index PIN for identifying the previous prediction, backward prediction, and interpolation prediction along with the transmission frame data.
DEX, the front prediction reference index PID (FIG. 2 (B)) and the rear prediction reference index NID (FIG. 2 (C)) representing the predicted frames of the front prediction and the rear prediction, respectively, are transmitted, and thereby the reception The device is designed to easily decode the transmitted frame data.

(G2) Configuration of Example (G2-1) Configuration of Transmitter In FIG. After efficiency encoding and conversion into transmission frame data DATA, the data is recorded on a compact disc.

The transmitting device 1 supplies the input video signal V D I N to the image data input section 2 , where the luminance signal and color difference signal constituting the human video signal VD, N are converted into digital signals, and then the data amount is reduced to 174. Reduce to

That is, the image data input unit 2 supplies the luminance signal converted into a digital signal to a one-field dropping circuit (not shown) to delete one field, and then outputs the luminance signal for the remaining one field into one line. Thin out every once in a while.

Further, the image data manual unit 2 deletes one field of the two color difference signals converted into digital signals, and then selectively outputs them alternately every l line.

Further, the image data input section 2 converts the thinned luminance signal and the selectively outputted color difference signal into data at a predetermined transmission rate via a time axis conversion circuit.

Thereby, the human video signals VD, H are subjected to preliminary processing via the image data input section 2, and the continuous image data Dv of the above-mentioned sequential frame data is generated.

When the start pulse signal ST is input, the rearrangement circuit 4 sequentially sorts the frame data AO, C1, C2, B3, C4.
, C5, A6, C7, . . . After dividing the image data Dv manually in the order of 6 frames into frame groups, the encoding processing order is AO2A6, B3, C1,
, C2, C4, C5, A]2, B9, C7,...
- Sort and output.

By rearranging and processing frame data in the order of encoding processing in this manner, subsequent intraframe encoding processing and interframe encoding processing can be simplified accordingly.

Furthermore, when the end pulse signal END rises, the rearrangement circuit 4 rearranges the frame data that was input just before that, and then stops outputting the frame data.

Furthermore, the rearrangement circuit 4 includes a frame group index GOF, a pre-prediction reference index PID, and a post-prediction reference index NI whose signal level rises at the beginning of each frame group.
D and a temporary index TR representing the order of frame data in the frame group.

The motion vector detection circuit 6 receives the rearranged image data D□, divides each frame data into predetermined macro unit blocks, and processes the divided data.

At this time, the motion vector detection circuit 6 outputs the frame data AO1A6, . Frame data B3, ClO2, C4, etc. to be subjected to inter-encoding processing
..., the motion vectors MVP and MVN are calculated based on a predetermined predicted frame for each macro unit block.
Detect.

Furthermore, at this time, the motion vector detection circuit 6 obtains deviation data between the frame data of the prediction result and the frame data to be subjected to interframe coding processing in the absolute value sum circuit, and generates error data ER which is the sum of the absolute values of the deviation data. It is made to obtain.

Thus, in this embodiment, the error data ER is used to switch the quantization step size, etc., thereby effectively avoiding deterioration of image quality and efficiently transmitting the video signal. .

Further, the motion vector detection circuit 6 uses the rearranged image data DVN as well as the frame group index GOF,
The previous prediction reference index PID, the subsequent prediction reference index NrD, and the temporary index TR are delayed by the motion vector detection processing time and output to the subsequent processing circuit for each macro unit block.

The subtraction circuit 8 creates deviation data D2 by obtaining difference data between the prediction data DP□ and the image data Dvu output from the adaptive prediction circuit 10, and outputs the deviation data D2 to the discrete cosine transformation circuit 12.

In the intraframe encoding process, the adaptive prediction circuit 10 outputs the average value of image data of each pixel for each macro unit block as prediction data DPI+.

On the other hand, in the interframe encoding process, the adaptive prediction circuit 10 executes the selective prediction process to select the previous prediction, the backward prediction, or the interpolation prediction, and then transfers the frame data of the selected prediction result to the predicted frame. Output each macro unit block as data DP□.

As a result, deviation data Dz (deviation data ΔFP, ΔF with the smallest amount of data in FIG.
NP and ΔFN), whereas for frame data subjected to intra-frame encoding processing,
Deviation data D2 from the average value can be obtained.

The discrete cosine transform circuit 12 has a DCT (d
iscrete cosine transform)
The deviation data D is calculated for each macro unit block using the method of
Convert 2.

The multiplication circuit 14 weights and processes the output data of the discrete cosine transform circuit 12 based on the control data output from the weight control circuit 16 .

Thus, in this embodiment, by weighting the coefficients formed by the output data of the discrete cosine transform circuit 12, image quality deterioration is effectively avoided and video signals are efficiently transmitted.

The requantization processor 8 requantizes the output data of the multiplication circuit 14.

At this time, the requantization circuit 20 changes the output data amount of the discrete cosine transform circuit 12, the input data amount of the buffer circuit 21, and the error by switching the quantization step size based on the control data output from the data control circuit 20. The quantization step size is switched based on the data ER, and thereby the output data of the discrete cosine transform circuit 12 is requantized to reflect the characteristics of the image, effectively avoiding image quality deterioration and converting each frame data. It is designed to transmit a fixed amount of data.

The inverse quantization circuit 22 receives the output data of the requantization circuit 18, performs requantization processing that is inverse to that of the requantization circuit 18, and thereby reproduces the manual data of the requantization circuit 18.

The inverse beam multiplication circuit 24 multiplies the output data of the inverse quantization circuit 22 in the opposite way to the multiplication circuit 14, thereby reproducing the input data of the multiplication circuit 14.

The discrete cosine inverse transform circuit 26 transforms the output data of the inverse beam calculation circuit 24 in the opposite manner to the discrete cosine transform circuit 12, thereby reproducing the input data of the discrete cosine transform circuit 12.

The addition circuit 28 converts the prediction data D, □ output from the adaptive prediction circuit 10 into the discrete cosine inverse transform circuit 2.
After adding it to the output data of No. 6, it is output to the adaptive prediction circuit 10.

Therefore, in the adaptive prediction circuit 10, the frame data DF can be obtained by reproducing the input data of the subtraction circuit 8 via the addition circuit 2, and thereby the frame data Dr can be selectively taken in to generate a predicted frame. Set,
Subsequently, a selected prediction result is obtained for the frame data input to the subtraction circuit 8.

In this way, by manually rearranging the frame data in the processing order, the adaptive prediction circuit 10 only needs to sequentially and selectively take in the frame data D and detect the selected prediction result, resulting in a simpler configuration. Video signals can be transmitted.

The run-length Huffman encoding circuit 30 subjects the output data of the requantization circuit 18 to Huffman encoding processing, which is a variable length encoding process, and then outputs the data to the transmission data synthesis circuit 32 .

Similarly, the run-length Huffman encoding circuit 34 converts the motion vectors MVN and MVP into optimized Huffman codes for each macro unit block, and then outputs them to the transmission data synthesis circuit 32.

The transmission data synthesis circuit 32 synchronizes with the frame pulse signal S
4 output data, prediction index PINDEX, previous prediction reference index PID, subsequent prediction reference index N
The ID and temporary index TR are outputted in a predetermined order along with the weighted control information of the control circuit 1G and the data seal control circuit 20.

At this time, the transmission data synthesis circuit 32 performs processing for each macro unit block, each block unit group, and each frame data.
A header is arranged for each frame group, and data such as a prediction index PINDEX is added to the header, so that the receiving device can decode the transmitted data based on the data added to the header. ing.

The rearrangement circuit 33 rearranges the output data of the transmission data synthesis circuit 32 in the order of encoding processing for each frame group and outputs the rearranged data to the buffer circuit 21, thereby reducing the buffer times v.
1121, transmission frame data DATA is output.

In this way, it is possible to obtain the transmission frame data DATA obtained by highly efficiently encoding the input video signal VDIN, and by recording the transmission frame data DATA together with the synchronization signal etc. on a compact disc, image quality deterioration can be effectively avoided. Video signals can be recorded at high density.

(G2-2) Motion Vector Detection Circuit As shown in FIGS. 4 and 5, the motion vector detection circuit 6 has a previous prediction reference index PID, a subsequent prediction reference index NID, a temporary index TR ( The image data DVN output from the rearrangement circuit 4 is processed based on A), (B), and (C)).

That is, in the motion vector detection circuit 6, the read-only memory circuits 72 and 73 receive the previous prediction reference index PID and the subsequent prediction reference index NID, respectively, and when the previous prediction reference index PrD and the subsequent prediction reference index NID have a value of 3, the read-only memory circuits 72 and 73 perform a logic Switching control data SWI and SW2 whose level falls (Fig. 5 (D)
) and (E)).

The read-only memory circuit 74 receives the temporary index TR, and stores intra-frame encoding processing control data whose logic level rises when the temporary index TR has a value of 0 (that is, it corresponds to frame data to be intra-frame encoded). PINTRA (Figure 5 (F))
Create.

Similarly, read-only memory circuit 75.76.77.78
．． 79, the temporary index TR is the value 3.
．． 1.2.4.5 (that is, corresponding to the frame data B3, C1, C2, C4, C5 of the interframe coding process), the logic level rises to the interframe coding process control data WB3, WCl, WC2, WC4, WC5
Create.

The delay circuit 80 receives interframe encoding processing control data WC.
5 is delayed, and switching control data BON (FIG. 5(G)) is created in which the logic level rises at the head of the given frame group sequentially from the second frame group.

The OR circuit 82 includes interframe encoding processing control data WC.
5 and intraframe encoding processing control data PINTRA, thereby creating frame memory control data WAP (FIG. 5(H)).

Thus, the motion vector detection circuit 6 operates based on these control data created by the read-only memory circuits 73 to 79, the delay circuit 80, and the OR circuit 82.

The blocking circuit 84 receives image data Dv sequentially input in synchronization with the frame pulse signal 5FP (FIG. 5(I)).
(IN) (FIG. 5(J)), each frame data is divided into predetermined macro unit blocks.

Here, as shown in FIG. 6, each frame data (FIG. 6(A)) is divided into 5×2 in the vertical and horizontal directions of the display screen and divided into 10 block unit groups (6
Figure (B)).

Furthermore, each block unit group is divided vertically and horizontally into 3×11 units into 33 macro unit groups (FIG. 6(C)), and the transmitting device 1 transmits frame data in units of macro unit groups. are processed sequentially.

Incidentally, one macro unit group is configured to allocate image data for 8 pixels vertically and horizontally to one block, so that image data for a total of 6 blocks is allocated.

Furthermore, for the 6 blocks, the luminance signals Y, , Y, , Y, , for 2 x 2 blocks vertically and horizontally are applied to the four blocks.
Y, is allocated to the remaining two blocks, and color difference signals C corresponding to the luminance signals Y, , Y, , Y3, and Y, respectively, are assigned to the remaining two blocks.
,,C, are allocated.

In this manner, frame data divided into 15×22 macro unit blocks can be obtained via the blocking circuit 84.

The delay circuit 85 delays the frame data output from the blocking circuit 84 by five frame periods required for motion vector detection processing and outputs the delayed frame data.

Thus, in the motion vector detection circuit 6, the image data Dv (OUT) (FIG. 5(K)) is divided into macro unit blocks and output in synchronization with the detection of motion vectors.

The delay circuit 86 has a frame group index GOF(IN
) (FIG. 5(L)) is delayed by 5 frame periods, and as a result, the frame group index GOF whose timing coincides with the image data D, (OUT) output from the motion vector detection circuit 6 is delayed. (OLIT) (5th
Figure (M)) is output.

The backward predicted frame memory circuit 88, the previous predicted frame memory circuit 89, and the interframe memory circuit 90 each store frame data serving as a reference for motion vector detection.

That is, the post-prediction frame memory circuit 88 takes in the image data Dv when the intra-frame encoding processing control data P INTRA rises, and thereby stores the frame data for a period of one frame period via the post-prediction frame memory circuit 88. After the AO is output, it is possible to obtain image data DHV in which the period frame data A6 of the following 6 frame period is continuous, and the period frame data A12 of the subsequent 6 frame period is continuous (Fig. 5 (N )).

On the other hand, the pre-prediction frame memory circuit 89 takes in the frame data output from the post-prediction frame memory circuit 88 when the frame memory control data WAP rises.

As a result, after the frame data AO continues for the first 5 frame periods among the 6 frame periods in which the frame data A6 is output from the backward predictive frame memory circuit 88 via the previous predictive frame memory circuit 89. , it is possible to obtain image data DPV in which the period frame data A6 of the following 6 frame period is continuous, and the period frame data A12 of the subsequent 6 frame period is continuous (FIG. 5(0)).

On the other hand, the interframe memory circuit 90 takes in the image data DvN when the interframe encoding processing control data WB3 rises.

As a result, the fourth frame data B3, B9, and B15 are transmitted through the interframe memory circuit 90 to obtain image data D, . being done.

The selection circuits 92 and 93 each select image data I)sv
and DINT, receives image data DPV and DINT,
The contacts are switched based on switching control data SW1 and SW2.

As a result, the selection circuits 92 and 93 sequentially switch and output frame data AO, A6, B3, .

That is, when detecting motion vectors MV3N and MV3P of frame data B3, the variable read memory circuit 9
Frame data A6 and AO are outputted to ports 4 and 95, respectively.

On the other hand, in level 2 processing, frame data C1
and motion vectors MVIN, MVIP and MV2 of C2
When detecting N, MV2P, frame data B3 and AO are output to variable read memory circuits 94 and 95, respectively, and motion vector M of frame data C4 and C5 is detected.
When detecting V4N, MV4P and MV5N, MV5P, frame data A6 and B3 are output to variable read memory circuits 94 and 95, respectively.

By the way, when detecting a motion vector of frame data C1 in a range of, for example, 8 pixels on the top, bottom, left and right sides using frame data AO as a reference, in order to detect a motion vector of frame data C2 using frame data AO as a reference, it is necessary to It is necessary to detect motion vectors within a range of 16 pixels.

Similarly, in order to detect the motion vectors of the frame data C4 and C5 using the frame data A6 as a reference, it is necessary to detect the motion vectors in a range of 16 pixels and 8 pixels, respectively.

Therefore, in level 2 processing, when detecting a motion vector, it is necessary to detect the motion vector within a maximum range of 16 pixels on the top, bottom, left and right.

On the other hand, in order to detect the motion vector of the frame data B3 based on the frame data AO and A6, it is necessary to detect the motion vector in a range of 24 pixels on the top, bottom, left and right.

Therefore, in the motion vector detection circuit 6, when the frame data is divided into predetermined frame groups and the frame data in each frame group is interframe encoded and transmitted, the motion vector detection range is wide. become,
Therefore, there was a risk that the configuration would become complicated.

Therefore, in this embodiment, after first detecting the level 2 motion vector, the motion vector detection range of the frame data B3 is set with reference to the detection result, and the entire motion vector detection circuit 6 is adjusted accordingly. It is designed to simplify the configuration.

That is, as shown in FIGS. 7 and 8, motion vectors V, , Vt, V are sequentially calculated for each frame data C1 and C2 from frame data AO to frame data B3.
, and the sum vector V++Vt+V3 of the motion vectors V, ,Vo,■, is detected.

Furthermore, frame data B3 is centered at a position offset by the sum vector V + + V z + V s.
A motion vector detection range is set, and a motion vector MV3P is detected within the motion vector detection range.

In this way, the motion vector MV3P can be detected within a narrow motion vector detection range.

In the case of this embodiment, since motion vectors for forward prediction and backward prediction are detected in the level 2 motion vector detection process, the motion vector MVIP of frame data C1
and MVIN are detected, and the motion vectors MV1P, , M■
By setting the motion vector detection range centered on a position offset by IN, the motion vector MV3P can be detected within a narrow motion vector detection range.

For this reason, the selection circuit 96 first supplies the frame data C1, C2, C4, and C5 to be processed at level 2 to the subtraction circuits KN, ~KNtss, and KPe~KPzss.

On the other hand, in level l processing, the selection circuit 9
6 switches the contact and connects the ink frame memory circuit 90.
The blocking circuit 97 divides the frame data B3 once stored into macro unit blocks in the same manner as the blocking circuit 84, and then divides the frame data B3 into macro unit blocks into subtraction circuits KNo to KN2S.
s and KP, to KPzss, thereby sequentially detecting motion vectors for frame data C1, C2, C4, and C5, and then detecting a motion vector for frame data B3.

The selection circuits 92 and 93 switch their contacts in accordance with the motion vector detection order, and input the frame data C1, C2, C4, and C5 to the variable read memory circuits 94 and 95, respectively, at the timing when the frame data C1, C2, C4, and C5 are input to the motion vector detection circuit 6. Frame data B3 and AO1B3 and AO2A6
After sequentially outputting B3, A6 and B3, frame data A6 and AO of one subsequent frame period are outputted.

Subtraction circuit KNo ~ KNzss and KP0 ~ KP, %,
256×2 subtraction circuits are connected in parallel and sequentially input image data of luminance signals forming each macro unit block.

On the other hand, the variable read memory circuits 94 and 95 subtract circuits KN, . Output to KNtss and KP, ~KP,%.

That is, in the level 2 processing, the variable read memory circuits 94 and 95 convert the first image data of the first macro unit block into subtraction circuits KN, ~KN□, and KP, ~).
(When input to pzss, the image data in the range of 16 pixels on the top, bottom, left and right sides of the image data (i.e., the image data in the motion vector detection range) is processed by the subtraction circuit K.
Output to N, ~KN□5 and KP, ~KP□.

Similarly, the variable read memory circuits 94 and 95 are configured such that the second image data of the first macro unit block is subtracted by the subtraction circuit KN,
When input to ~KN□5, KP, and ~KPtss, image data in a range of 16 pixels on the top, bottom, left, and right around the image data of the cylinder 2 is extracted from the frame data of the predicted frame by a subtraction circuit KNo ~K N zss and KPo~
Output to KP*ss.

Thus, the variable read memory circuits 94 and 95 operate as subtraction circuits KN, ~KNtss and K in level 2 processing.
P0~KP□1. For the input image data, image data in the motion vector detection range is sequentially output.

As a result, in level 2 processing, the subtraction circuit K N
Obtain deviation data when moving the frame data of the predicted frame within the motion vector detection range for each image data of the frame data for which the motion vector is detected, via o~KN□ and K P o~KP□. be able to.

On the other hand, in level 1 processing, variable read memory circuits 94 and 95 store frame data C1, C2,
Subtraction circuits KN, ~KN based on the detection results of C4 and C5
For the image data input to zss and KPo to KPtss, the predicted motion vector MV is calculated from the image data.
Centering on the image data displaced by 3NY and MY3PY, image data in a range of 16 pixels in the upper, lower, left, and right directions is output to subtraction circuits KN0 to KNtss and KP to KP□.

As a result, in level 1 processing, the subtraction circuit K N
-~K N-5s and K P o ~K P tss
For each image data of the frame data B3, it is possible to obtain deviation data when the predicted frame is moved within the motion vector detection range displaced by the predicted motion vector MV3NYXMY3PY.

Absolute value summation circuits 100 and 101 receive subtraction data from subtraction circuits KN, ~KN□5 and KP, ~KPzss, respectively, and each subtraction circuit KN.

After detecting the absolute value sum of the subtraction data for each of ~KNxss, KP, and ~KP□, the absolute value sum is output for each macro unit block.

As a result, via the absolute value summation circuits 100 and 101,
In level 2 processing, for each macro unit block,
It is possible to obtain 256 pieces (that is, 16×16) of deviation data when the predicted frame is sequentially moved within the motion vector detection range centered on the macro unit block.

On the other hand, in level 1 processing, the predicted frame is sequentially moved for each macro unit block within a motion vector detection range that is displaced by the predicted motion vectors MV3NY and MY3PYO with respect to the macro unit block as a reference. 256 deviation data can be obtained.

The comparison circuits 102 and 103 receive the 256 deviation data output from the absolute value summation circuit 100 and lOl,
Among them, deviation data D0°8 and Do when the image data of the predicted frame is moved up, down, left and right by O pixels (that is, the predicted frame is not moved). , is output to comparison circuits 105 and 106.

Further, the comparison circuits 102 and 103 detect the minimum value from the remaining deviation data, and detect the error data ER (ER, and ER
, ), and detects the position information of the deviation data of the minimum value.

Thus, by switching the quantization step size of the requantization circuit 18 and controlling the weighting process of the multiplication circuit 14 based on the error data ER, the properties of the image can be reflected in the requantization process. Video signals can be transmitted while effectively avoiding image quality deterioration.

Furthermore, it is possible to detect positional information for moving the predicted frame so that the deviation data is minimized based on the deviation data of the minimum value, and thereby it is possible to sequentially detect motion vectors for each macro unit block.

Comparison circuits 105 and 106 output error data ER and E.
R, and deviation data D,. , and Do. .

It is designed to obtain comparative results.

At this time, as shown in FIG.
6 is error data ER and ER, and deviation data D0° and Do. , as expressed by the following equation, when converting into the error and deviation amount per IN element, the 0 vector is preferentially selected as the motion vector in a range where the error and deviation amount are small.

In other words, in a range where the error and deviation amounts are small, even if the comparison dies 15102 and 103 generate the deviation data ΔEN and ΔEP (Fig. 1) based on the motion vector, when the deviation data ΔEN and ΔEP are generated using a zero vector. Compared to this, the data amount of the deviation data ΔEN and ΔEP can be reduced to a certain extent, but on the contrary, the overall data amount increases by the amount that the detected motion vectors, which are significant information, are transmitted.

Therefore, in this embodiment, comparison circuits 105 and 10
By preferentially selecting the 0 vector as the motion vector in step 6, the video signal as a whole can be efficiently transmitted.

Thus, the comparison circuits 105 and 106 output switching signals to switch the contacts of the selection circuits 107 and 108,
The O vector data MY and the motion vectors output from the comparison circuits 102 and 103 are selected and output according to the priorities shown in FIG. 9, and the motion vectors MviN and MViP (see FIG. Q
) and (R)) can be obtained.

Motion vector memory circuits 110-113 and 114-1
17 is interframe encoding processing control data WCI, WC
2. According to WC4 and WC5, capture motion vectors MViN and MV i P, and thereby obtain motion vectors MVINS for backward prediction and forward prediction for frame data C1, C2, C4, and C5 to be processed at level 2, respectively.
MV2N.

MV4NSMV5N and MVIP, MV2P, MV4P
,, Import MV5P.

On the other hand, adder circuits 120 to 122 and 123 to 12
5, motion vector memory circuits 110 to 113 and 11;
Motion vectors stored in 4 to 117 MVIN, MV2
NSMV4N, MV5N and MVI P, MV2P, M
V4P,, MV5P received, motion vector MV I N
, MV I PSMV 2 N and MV2P, and the addition results of motion vectors MV4N, MV4 PSMV5N and MV5P(7) are output to 1/2 division circuits 127 and 128, respectively.

In other words, as described above, in this embodiment, after first detecting the level 2 motion vector, the detection range of the motion vector of frame data B3 is set in advance by referring to the detection result. The motion vector is detected within a range of 16 pixels on the left and right, and the overall configuration of the motion vector detection circuit 6 is simplified accordingly.

Therefore, adder circuits 120 to 125 and 1/2 divider circuit 1
27.128 calculates the predicted motion vectors MV3NY and MV as expressed by the following equations (3) (4) by obtaining the addition result of 1/2 for the motion vectors MvIN to MV5P.
After creating 3PY, the predicted motion vectors MV3NY and MV3PY are output to addition circuits 132 and 133 via selection circuits 130 and 131.

Here, the selection circuits 130 and 131 switch the contacts according to the switching control data BON, and select the frame data C1, C2, C4 to be processed at level 2,
For C5, data [)as and I)or of value O are selected and output, whereas for frame data B3 to be processed at level l, predicted motion vector MV3N
Selectively output Y and MV3PY.

- Addition circuits 132 and 133 are connected to selection circuits 130 and 1
31 (7) Output data MV 3 N Y, Dos and MV 3 PY, DIP to the vector generation circuit 9
Control data D output from 8. Add to.

As a result, for frame data C1, C2, C4, and C5, motion vectors are detected in the motion vector detection range centered on each macro unit block, whereas for frame data B3, motion vectors are detected from each macro unit block. , a motion vector is detected in a motion vector detection range displaced by the predicted motion vectors MV3NY and MV3PY.

Therefore, frame data A separated by multiple frames
Motion vectors between O and B3, B3 and A6 can be reliably detected within a narrow motion vector detection range, and thus motion vectors can be detected with a simple configuration.

Furthermore, the motion vectors for forward prediction and backward prediction of the frame data C1 and C2 are averaged to set a motion vector detection range of the forward prediction motion vector MV3P,
The motion vectors for forward prediction and backward prediction of frame data C4 and C5 are averaged, and the motion vector for backward prediction MV3 is calculated.
By setting N motion vector detection ranges, motion vectors can be detected reliably.

Addition circuits 135 and 136 add predicted motion vectors MV3NY and MV3PY to the motion vectors output from selection circuits 107 and 108 in level 1 processing, and output the resultant motion vectors MV3P and MV3.
Thus, with an overall simple configuration, the motion vector MV between far-separated frame data is
3N and MV3P can be detected.

After the counter circuit 138 is cleared by the interframe encoding processing control data WC5, the counter circuit 138 receives the frame pulse signal SFP.
The motion vector selection data MVSEL (FIG. 5(S)) is composed of a quinary counter circuit configured to sequentially count 0 to 4, and outputs motion vector selection data MVSEL (FIG. 5(S)) that sequentially cycles from value O to value 4.

The selection circuits 139 and 140 sequentially switch the contacts in accordance with the motion vector selection data MVSEL, thereby selecting the motion vector M output from the addition circuits 135 and 136.
V3N and MV3P, motion vector memory circuit 110-
The motion vectors MVIN-MV5P stored in 117 are sequentially selected and outputted to the run-length Huffman encoding circuit 34, and the motion vectors MvN and MVP (FIG. 5 (T) and (U)
)) can be obtained for each macro unit block.

(G2-3) Run-length Huffman encoding circuit As shown in FIG. 10, the run-length Huffman encoding circuit 34 is
Pre-predicted motion vector MV of frame data C1 and C4
A selection circuit selects the post-predicted motion vector MV2NSMV5N of IP, MV4P and frame data C2, C5 (that is, a motion vector detected using the adjacent frame data AO, B3, A6 as a reference frame, hereinafter referred to as a 1x vector). Give 150.

The addition circuit 151 calculates the motion vectors MVIN and MV4N of the post-prediction of frame data C1 and C4 and the motion vectors MV2P and MV5P of the pre-prediction of frame data C2 and C5.
(In other words, it is a motion vector of frame data that is two frames apart from the reference frame data AO, B3, and A6, hereinafter referred to as a double vector), and when the value is positive, it adds a value of 1 and outputs it. On the other hand, if the value is negative, the value -1 is subtracted and output.

On the other hand, the 1/2 divider circuit 152
, the remainder is removed from the 1/2 division result, and the result is output to the selection circuit 150.

That is, the addition circuit 151 and the 1/2 division circuit 152 are
Motion vectors MV I N, MV 4 N and MV2
P, MV5P are converted into motion vectors for one frame and output.

On the other hand, the addition circuit 153 receives motion vectors MV3P and MV3N of frame data B3 (that is, motion vectors of frame data separated by three frames from the reference frame data AO and A6, hereinafter referred to as triple vectors). , when the value is positive (t[2 is added and output), whereas when the value is negative (i-2 is subtracted and output).

The 1/3 division circuit 154 receives the output of the addition circuit 153, removes the remainder from the 1/3 division result, and sends it to the selection circuit 1.
Output to 50.

That is, the addition circuit 153 and the 1/3 division circuit 154 are
The motion vectors Mv3P and MV3N are converted into motion vectors for one frame and output.

In this way, the occurrence probabilities of the motion vector values input to the selection circuit 150 are set to equal values, thereby making it possible to easily optimize each motion vector.

That is, as shown in FIG. 11, in successive frames FM, Fl, F2, and F3, the motion vectors V, , V, , ■, based on frame FM are the same as frame FM.
, Fl, and F2.13, the following relationship holds true.

Therefore, the motion vector vX of frames spaced X frames apart during -boat fishing is calculated using the following formula (%) (7) As shown in Figure 12, this means that when the value of the motion vector is set to a, the appearance probability is calculated statistically. Expressing this, it can be seen that if the appearance probability φVl (a) of the motion vector v1 is multiplied by X in the horizontal axis direction, the probability φv,I (a) of the motion vector ■8 can be expressed.

Therefore, if we divide the motion vector detection circuit by X, remove the remainder, and express it as the value a, the probability of occurrence of the motion vector v
φVx (a) is the appearance probability φV of the motion vector V
l (a), and it can be seen that the division result of the motion vector v8 and the motion vector vI can be optimized using the same table.

Based on this principle, the run-length Huffman code differentiation processing circuit 34 provides the selection output of the selection circuit 150 to the read-only memory circuit 156, uses the selection output as an address, and sets the data DVI stored in the read-only memory circuit 156. Output.

Here, as shown in FIG. 13, the read-only memory circuit 156 outputs variable-length encoded data in which the code length gradually increases with input data having a value of 0 as the center. The motion vector converted into one frame is thereby optimally encoded.

In other words, when the value of the motion vector is statistically detected, the value O
The motion vector has the highest probability of occurrence, and the probability of occurrence decreases as the value of the motion vector increases.

Therefore, in this embodiment, the amount of data required for motion vector transmission is reduced as a whole by encoding the motion vector of value O into the shortest code table, thereby reducing the amount of data required for motion vector transmission. It is designed to transmit information efficiently.

Further, the read-only memory circuit 156 outputs the output data D
Code length data DLL representing the code length of VI is output together with data DVI.

The remainder output circuit 160 divides the output data of the adder circuit 153 by 4ti3, and then outputs the remainder data to the read-only memory circuit 162.

As shown in FIG. 14, read-only memory circuit 162
outputs residual data DV2 of value O with code length 1 for input data of value 0; and outputs residual data Dv2 with a value of 1.1.

Here, the input data to the read-only memory circuit 162 has a value of 0 because it is the remainder obtained by converting the triple vector added and subtracted by the addition circuit 153 into one frame.
has the highest probability of occurrence, and as the value increases, the probability of occurrence decreases.

Therefore, in this embodiment, the amount of data required for motion vector transmission is reduced as a whole by outputting residual data DV2 with the shortest code length for the input data with the highest probability of occurrence, 0. This makes it possible to efficiently transmit moving image signals.

Furthermore, the read-only memory circuit 162 stores surplus data D.
In synchronization with V2, code length data DLL2 representing the code length of the surplus data DV2 is output.

The selection circuit 164 switches its contacts in synchronization with the selection circuit 150, and selects and outputs the least significant bit of the output data output from the addition circuit 151 and the remainder data DV2.

That is, the selection circuit 164 stops the selective output operation for the 1x vector.

Further, the selection circuit 164 outputs the manually input data of the least significant bit for the double vector, and thereby selects and outputs a selection output of value 1 to the parallel-serial conversion circuit 166 when the value of the double vector is an even value. However, when the value of the double vector is an odd value or the value 0, a selection output of value O is output to the parallel-serial conversion circuit 166.

Further, the selection circuit 164 selectively outputs the residual data DV2 for the triple vector.

The selection circuit 168 selects input data DLLO of value O and value 1.
and DLL1 and code length data DLL2, and by changing the contacts in synchronization with the selection circuit 164, code length data DL2 representing the code length of the selected output data DJ output from the selection circuit 164 is output.

Adder circuit 170 outputs the addition result of code length data DLL and DL2 to parallel-serial converter circuit 166.

As shown in FIG. 15, the parallel-to-serial conversion circuit 16
6 is output data DV of the read-only memory circuit 156
Output data DJ of the selection circuit 164 and addition circuit 17 to I
After adding 0 addition data, it is converted to serial data and output.

As a result, via the parallel-serial conversion circuit 166,
Read-only memory circuit 156 for 1x vector
The output data DVI and the output data D output from
The code length data DL1 of VI is converted into serial data and output.

On the other hand, when the value of the double vector is an even value, the remainder bit b1 of the value O is added to the output data DVI output from the read-only memory circuit 156, and the code length data is added to the output data DVI output from the read-only memory circuit 156. After addition data obtained by adding the value 1 to DLI is added, it is converted to serial data and output.

Further, when the value of the double vector is an odd value or the value O, the remainder bit b1 of value 1 is added to the output data DVI, and after addition data obtained by adding the value 1 to the code length data DLI is added, the serial It is converted to data and output.

On the other hand, for the triple vector, the triple vector has the value O or above the value (3n+1) (n=o, 1.2...
), the output data DVI has a remainder pi of value O)b+
is added, and added data obtained by adding the value l to the code length data DL1 is added, and then converted into serial data and output.

Furthermore, the triple vector has the value ±(3n+2)(n=0.1
．． 2...), the output data DVI has the values 1 and 0, and the remainders b+ and s are added to it, and additional data obtained by adding the value 2 to the code length data DLI is added, While it is converted to serial data and output, the triple vector has a value of (3n+3) (n=o, 1, 2
-...), the value 1 and the remainder pi) b+ and b2 of the value 1 are added to the output data D■1, and additional data obtained by adding the value 2 to the code length data DLI is added to this. , converted to serial data and output.

In this way, on the transmission target side, the motion vector data subjected to the variable length encoding process in this way is used as the previous prediction reference index PID and the subsequent prediction reference index N I
D. Based on the temporary index TR, it can be determined whether the vector is a 1x vector, a 2x vector, or a 3x vector;
The original motion vector can be decoded based on the determination result.

In this way, the 1x vector, 2x vector, and 3x vector can be subjected to variable length encoding processing using one type of table stored in the read-only memory circuit 156, giving priority to those with a high probability of appearance. Motion vector optimization processing can be performed with a simple configuration.

Furthermore, by performing the encoding process in this manner, the motion vector can be transmitted while maintaining the detected accuracy, thus effectively avoiding image quality deterioration and efficiently transmitting the video signal.

(G2-4) Configuration of receiving device In FIG. 17, 200 indicates the receiving device as a whole, and playback data D obtained by playing back a compact disc.
, is received by the receiving circuit 201.

The receiving circuit 201 detects the beginning of each frame group based on the data added to the transmission data, and then outputs the detection result together with the image data DVPI.

As a result, as shown in FIG.
are frame data PAO1PB3, Pct, PC2 that have been sequentially subjected to intraframe encoding processing and interframe encoding processing.
. . . continuous image data Dv□ (FIG. 18(A)) can be obtained.

The rearrangement circuit 203 outputs the interframe encoded transmission frame data PB3, PctSPC2, etc. with a delay of 7 frame periods, thereby allowing the transmitting device l side to perform the intraframe encoding and processing. Interframe encoding processing order (i.e., same as decoding processing order)
Frame data PAO1PA6, PB3, PCI, P
Rearrange and output C2... (Figure 18 (B)
)).

The buffer circuit 204 once stores the image data Dv□8 output from the rearrangement circuit 203, and then outputs it to the subsequent separation circuit 206 at a predetermined transmission rate.

The separation circuit 206 determines the frame group index GOF based on the data added to the transmission data.

Pre-prediction reference index PID, post-prediction reference index NID, temporary index TR.

Prediction index P I NDEX, data DC (DC
M-Y, DCM-U, DCM-V), QUANT, and motion vector data MvD-P and MVD-N are reproduced and output to a predetermined circuit.

As a result, the control circuit 207 is configured to control the compact disc drive reproduction system, and as described above with reference to FIG. 18, reproduces data sequentially recorded on the compact disc to obtain image data Dv□8. being done.

Further, the separation circuit 206 removes the header from the image data Dv□, and then the run-length Huffman inverse encoding circuit 21
Output to 0.

The run-length Huffman inverse encoding circuit 210 performs the inverse processing of the run-length Huffman encoding circuit 30 (FIG. 3), thereby reproducing the input data of the run-length Huffman encoding circuit 30 on the receiving device 200 side. .

The inverse quantization circuit 211 receives the output data of the run-length Huffman inverse encoding circuit 210 and data Q representing the quantization step size that is added to the macro unit block and transmitted.
Upon receiving the UANT, the inverse quantization circuit 22 (FIG. 3) executes requantization processing that is inverse to that of the requantization circuit 18, and as a result, on the receiving device 200 side, the input data of the requantization circuit 18 is Reproduce.

The inverse dye calculation circuit 212 receives the output data of the inverse quantization circuit 211, and executes the inverse beam calculation process of the multiplication circuit 14 (FIG. 3) based on the data added to each macro unit block. Therefore, on the receiving device 200 side, the multiplier circuit 1
Reproduce the input data in step 4.

The discrete cosine inverse transform circuit 213 inversely transforms the output data of the inverse dye calculation circuit 212 and the discrete cosine transform circuit 12 (FIG. 3), thereby reproducing the input data of the discrete cosine transform circuit 12.

The addition circuit 218 adds the prediction data Dp□ output from the adaptive prediction circuit 214 to the output data of the discrete cosine inverse transform circuit 213,
Output to.

The run-length Huffman inverse encoding circuit 220 generates a pre-predicted motion vector MVP and a post-predicted motion vector MVP that has been subjected to variable-length encoding processing by the run-length Huffman encoding circuit 34 of the transmitting device 1;
The MVN is decoded and output to the adaptive prediction circuit 214.

The adaptive prediction circuit 214 receives the output data D of the addition circuit 218.
Based on fIN and motion vector MVPSMVN, etc.
The prediction data D□1 output from the adaptive prediction circuit 10 of the transmitter l is reproduced.

That is, the adaptive prediction circuit 214 outputs DC level data DC to the addition circuit 218 as prediction data DPRI for the frame data AO and A6 that have been subjected to the intra-frame encoding process.

Thereby, the frame data AOSA6 subjected to the intra-frame encoding process can be reproduced via the addition circuit 218.

Further, the adaptive prediction circuit 214 includes the adaptive prediction circuit 1 on the transmitting side.
0, it has a previous predictive frame memory circuit, a subsequent predictive frame memory circuit, and an interframe memory circuit, and stores reproduced frame data AO, A6 in the previous predictive frame memory circuit and the subsequent predictive frame memory circuit ( 1st
8 (C) and (D)), the predicted data D and □ of the frame data B3 are generated.

As a result, frame data B3 subjected to level 1 interframe encoding processing can be reproduced via the addition circuit 218.

Further, the adaptive prediction circuit 214 stores the reproduced frame data B3 in the interframe memory circuit (the 18th
(E)), the prediction data DPII of the frame data C1, C2, C4, C5 is generated, thus adding circuit
It is possible to reproduce frame data C1, C2, C4, and C5 that have been subjected to level 2 interframe coding processing.

Further, the adaptive prediction circuit 214 returns the reproduced frame data AO, , A6, B3, . . . to the original arrangement order and outputs them (FIG. 18(F)).

The receiving device 200 has an interpolation circuit (not shown), and is configured to interpolate and output the lines and frames thinned out on the transmitting device side 1 based on the reproduced frame data. The input video signal VDIN is reproduced.

In this way, it is possible to reproduce a video signal recorded on a compact disc by high-efficiency encoding processing.

(G3) Operation of the embodiment In the above configuration, after the input video signal VD is converted into a digital signal in the image data input section 2, the data amount is reduced to 1/4, and the frame data AO1C is sequentially converted into a digital signal.
1, C2, B3... Continuous video signals VD(
1(A)).

The video signal VD is processed by the rearrangement circuit 4 as frame data AO.
, CI, C2, B3... after being divided into a frame group of 6 frames, the encoding processing order AO, A
6, B3, C1, C2, C4, C5... (i.e., frame data AO1A to be intra-frame encoded)
6. Frame data B3 to be subjected to level 1 interframe encoding processing, frame data C1, C2, C4, and C5 to be subjected to level 2 interframe encoding processing), and then predetermined identification data GOFSP ID,N
It is output together with ID5TR.

Thus, the order of encoding processing is AO1A6, B3, CI,
After sorting into C2, C4, C5, C7, etc., predetermined identification data GOF, PID, NID, TR are added and output, resulting in subsequent intra-frame encoding processing and inter-frame encoding. The conversion process can be simplified.

The rearranged image data DVM is divided into macro unit blocks by the blocking circuit 84 of the motion vector detection circuit 6, and then divided into macro unit blocks by the adaptive prediction circuit 10 at a predetermined timing.
is output to.

Furthermore, among the rearranged image data DVN, frame data AO, B3, and A6 are stored in the previous prediction frame memory circuit 89, the interframe memory circuit 90, and the rear prediction frame memory circuit 88, respectively, and thereby the selection circuit 139 and 140, sequential frame data B
3. Motion vector MV3 of C1, C2,...
PSMV3N, MV IP, MVIN, MV2P, MV
2N... is detected.

On the other hand, for the image data DwH output to the adaptive prediction circuit 10, the average value of the image data of the luminance signal and color difference signal is obtained for each macro unit block, and the average value data is used as direct current data DC to the transmission data synthesis circuit. 32.

Furthermore, the image data DVH manually entered into the adaptive prediction circuit 10
is subjected to selective prediction processing based on frame data AO, A6, and B3 (consisting of frame data reproduced in two days of adding circuits), and post-prediction, pre-prediction, and interpolation prediction are performed for each macro unit block. Deviation data ΔFN, ΔFP
, ΔFNP (Fig. 1) are obtained.

As for the deviation data ΔFN, ΔFP, and ΔFNP, the one with the smallest amount of data is detected, and from this, the selected prediction result is detected for each macro unit block.

Post-predicted, pre-predicted, and interpolated predicted frame data FN, F
P and FNP are selectively outputted according to the prediction selection result, thereby creating prediction data DPI+, which is sent to the subtraction circuit 8.
is output to.

On the other hand, the selection prediction result is the identification data P[NDE
It is output as X to the transmission data synthesis circuit 32.

The predicted data D, □ are subtracted from the image data DVN in a subtraction circuit 8, thereby creating deviation data D2.

The deviation data D2 is obtained by the discrete cosine conversion circuit 1.
2, each macro unit block is transformed using the DCT method.

The output data of the discrete cosine conversion circuit 12 is
In the multiplication circuit 14, the weighting is processed according to the error data ER output from the motion vector detection circuit 6, and then in the requantization circuit 18, the error data ER and the output data amount of the discrete cosine transform circuit 12 are processed. , is requantized with a quantization step size corresponding to the input data amount of the buffer circuit 21.

Thus, the weighting process and the error data fER
, the amount of output data of the discrete cosine transform circuit 12, and the input data of the buffer circuit 21 by requantizing with a quantization step size corresponding to the amount of output data of the discrete cosine transform circuit 12 and the input data of the buffer circuit 21. iiB
! It is possible to transmit the ll image signal with high quality and each frame data with a predetermined amount of data.

The requantized image data is variable length encoded in a run length Huffman encoding circuit 30, then variable length encoded in a transmission data synthesis circuit 32 according to a predetermined format, and then converted into a predetermined recorded on a compact disc in this format.

On the other hand, the motion vector detected by the motion vector detection circuit 6 is output to the run-length Huffman encoding circuit 34.

Here, the motion vector is converted into a vector for one frame, and then adaptively encoded, and residual data and data representing the type of motion vector (i.e., the previous prediction reference index PID, the subsequent prediction reference index NID, and the temporary (which can be detected with index TR) is recorded on the compact disc.

Furthermore, the requantized image data is processed by an inverse quantization circuit 2.
2. Discrete cosine transform circuit 12 via inverse beam calculation circuit 24 and discrete cosine inverse transform circuit 26
After being inversely transformed into input data, the addition circuit 28 adds the predicted data D, □ output from the adaptive prediction circuit 10 to frame data D, which reproduces the input data of the subtraction circuit 8. is converted to

Thus, the frame data D is processed by the adaptive prediction circuit 10.
and are used as predicted frames for forward prediction and backward prediction, respectively.

As a result, 8N data D P II + is created for the Frame 1 data that is subsequently input to the subtraction circuit 8.
Transmission frame data DATA can be obtained sequentially.

On the other hand, in the receiving device 200, the reproduced data D□ obtained by reproducing the compact disc is transmitted to the receiving circuit 200.
01 and after the beginning of each frame group is detected,
Frame data PAO1PB3, pci, PO2, etc. are output to the rearrangement circuit 203 together with the detection results and subjected to sequential intra-frame encoding processing and inter-frame encoding processing.
The image data is sorted into consecutive image data DVPIN.

The rearranged frame data is sent to the buffer circuit 204.
The frame group index G is output to the separation circuit 206 via the frame data, and is added to the frame data and transmitted.
OF, the previous prediction reference index PID, the subsequent prediction reference index NID, etc. are reproduced.

The frame data output from the separation circuit 206 is inversely transformed via a run length Huffman inverse encoding circuit 210, an inverse quantization circuit 211, an inverse beam calculation circuit 212, and a discrete cosine inverse transform 111213, thereby performing discrete cosine transform. The human power data of circuit 12 is reproduced.

The output data of the discrete cosine inverse transform circuit 213 is added to the predetermined rule data DPI+ output from the adaptive prediction circuit 2I4 in an adder circuit 218, and the resulting added data D? IN is output to adaptive prediction circuit 214.

In the adaptive prediction circuit 214, regarding the intra-frame encoded frame data, the transmitted DC level data DC is predicted data D? It is output as ll,
As a result, frame data A is transmitted via the adder circuit 218.
Output data DT obtained by sequentially reproducing O, A6, and A12
You can get IN.

Out of the output data D T I N of the adder circuit 218, the frame data AO1A6 is processed in the adaptive prediction circuit 214 for the following frame data B3, CI, C2, C4...
... is used for decoding, and the decoded frame data AOSA6, B3, C1, C2, C4...
The selection prediction circuit 214 arranges and outputs the signals in the original order, thus making it possible to reproduce the highly efficient encoded and transmitted moving image signal.

(G4) Effects of the Example According to the above configuration, double vector MvIN, MV2P
,,MV4N, Mv5P, triple vector MV3N, MV
By converting 3P into a vector for one frame and performing variable length encoding processing with priority given to those with a high probability of appearance,
Encoding processing can be performed using a common table, and thus motion vector optimization processing can be performed with a simple configuration.

(G5) Other embodiments (1) In the above embodiment, sequential frame data is divided into units of 6 frames, and motion vectors detected in 2 frames and 3 frames apart are transmitted. Although the case has been described, the present invention is not limited to this.
It is widely applicable to transmitting motion vectors between frames separated by multiple frames.

(2) Further, in the above embodiment, the case where a video signal is recorded on a compact disc is described, but the present invention is not limited to this, and the present invention is applicable to the case where a video signal is recorded on various recording media such as a magnetic tape. can be widely applied when directly transmitting a message to a device.

Effects of the Invention As described above, according to the present invention, motion vectors between frames separated by a plurality of frames are converted into vectors for one frame, and the motion vectors are optimized and transmitted, resulting in a simple configuration. The motion vector can be optimized and transmitted.

[Brief explanation of the drawing]

FIG. 1 is a route diagram for explaining a video signal transmission system according to an embodiment of the present invention, FIG. 2 is a route diagram for explaining its operation, and FIG. 3 is a block diagram showing the overall configuration of a transmission device.
Figures 4 (1) and (2) are block diagrams showing the motion vector detection circuit, Figures 5 (1) and (2) are route maps explaining its operation, and Figure 6 is a diagram explaining frame data. Route map, Figures 7 and 8 are route maps for explaining the principle of motion vector detection, Figure 9 is a characteristic curve diagram for explaining priority detection of motion vectors, and Figure 10 is run-length Huffman encoding. 11 and 12 are block diagrams showing the circuit; FIGS. 11 and 12 are route diagrams for explaining motion vector encoding processing; FIGS. 13 and 14 are route diagrams for explaining the read-only memory circuit; FIG. 16 is a route map showing encoded motion vector data, FIG. 17 is a block diagram showing the receiving device, FIG. 18 is a route map explaining its operation, and FIGS. 19 and 20 are It is a route map for explaining problems. l...Transmitting device, 4.33.203...
・Reordering circuit, 6...Motion vector detection circuit,
10,214...adaptive prediction circuit, 18...
... Requantization circuit, 22.211 ... Reverse quantization circuit, 200 ... Receiving device.

Claims (1)

[Scope of Claims] A video signal transmission device that detects a motion vector from a predetermined reference frame, performs interframe encoding processing using the motion vector, and transmits a video signal, wherein a plurality of frames apart from the reference frame are provided. A video signal transmission device characterized in that a motion vector of a frame separated from the reference frame is converted into a motion vector of one frame from the reference frame to a frame separated by a plurality of frames, and the motion vector is optimized and transmitted.