JPH03129754A - Designing method for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To sharply reduce the number of designing processes and to realize a high density by a method wherein, when a specific lower-rank cell housed in a large-scale cell is replaced with another lower-rank cell formed separately, a designing pattern of a large-scale cell which has been already designed is utilized effectively. CONSTITUTION:Another lower-rank cell 103 which is connected electrically to a RAM 110 is unfolded in advance. After the lower-rank cell 103 has been unfolded, information on a RAM 102 before its replacement is stored in advance; after that, a pattern of the RAN 102 is removed from a layout pattern; a higher- rank cell pattern which forms an external shape of a large-scale cell is obtained. Then, a size of the RAM 110 to be replaced and positions of individual terminals are detected. Stored information on a RAM 101 before its replacement is exchanged for information on the RAM 110 after its replacement; the higher-rank cell pattern is compacted automatically. The RAM 110 is arranged in the automatically compacted higherrank cell 102; a new large-scale cell 20' can be obtained.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for designing a semiconductor integrated circuit device that aims to reduce the size of a layout pattern, and in particular to a semiconductor integrated circuit device to which a hierarchical design consisting of an upper cell and a lower cell is applied. The present invention relates to a design method for reducing the layout pattern of an integrated circuit device.

[Prior art] When designing an LSI, it is not easy to do the detailed design of the entire LSI at once, so the so-called layered design handles the functions and logic of the LSI hierarchically and proceeds with the design layer by layer. is commonly used.

One of the aspects of such layered design is the bottom-up design technique, which starts from designing the basic blocks (lower functional blocks) of the LSI, combines them, and sequentially designs higher functional blocks, and vice versa. Starting from the design of higher-level functional blocks, the more detailed parts (lower-level functional blocks)
A top-down design technique is known in which the design progresses from step to step.

The above two design techniques are used for microprocessors and calculators.
It is suitable for the so-called general type LSI layout technique, which is advantageous for designing LSIs such as SIs that have a wide variety of logic functions mounted on one chip.

This general type LSI layout technique realizes a wide variety of logic functions in rectangular areas with different shapes, and in order to realize the placement of various cells, the logic design of the circuit is performed top-down for each layer. The specific layout design is done from the bottom up for each layer.

Incidentally, the above-mentioned layout design is automatically performed using so-called CAD, and this automatic layout design determines an LSI layout pattern that minimizes the chip area.

On the other hand, a compaction technique for automatically further compacting the minimum LSI layout pattern is well known. Such compaction techniques usually perform automatic compaction based on symbolic layout (a method of laying out transistors, wiring, etc. as symbols), so even if automatic compaction is performed after automatic layout to minimize the chip area. It has not been possible to achieve a high degree of integration equivalent to mask design at the individual layout level by skilled workers.

In order to solve this problem, a CAD method for mask layout/compaction that enables compaction at the mask layout level and takes electrical characteristics into consideration was published in Nikkei Microdevice December 1987 issue, pages 120-128.
It became publicly known by Shin. According to the compaction CAD method mentioned above, rectangular figures such as the length of bus wiring and the diffusion layer (
The area of polygons) is also subject to automatic compaction,
Therefore, it is possible to compact down to individual mass layers such as ion-implanted layers and well-forming layers, and compared to the conventional compaction technique (technique using symbolic layout), the compaction is much superior. This is suitable for reducing the chip area.

[Problems to be Solved by the Invention] Incidentally, in recent manufacturing technology for semiconductor integrated circuit devices, it is difficult to design only a group of cell parts (lower cells) such as a bipolar transistor part, ROM part, RAM part, etc. in a semiconductor integrated circuit. A development method is adopted in which a person creates a separate document. The lower cells created separately in this way are provided with just enough input/output terminals to correspond to those of the previous lower cells, but regarding the horizontal and/or vertical size of the cell, Improvements such as reducing them and making them even more compact are being made.

Therefore, even if a semiconductor integrated circuit device is created by adopting the above-mentioned automatic layout technique and automatic compaction technique, if the unique lower cell of the functional block is developed separately and its external dimensions change, the automatic The entire design process, including layout and automatic compaction, must be redone. As described above, it is impractical to redesign the entire semiconductor integrated circuit device every time a new functional block is developed.

The present invention has been made in view of the above circumstances, and it is possible to select a specific lower cell stored in a large-scale cell from among functional blocks constituting a large-scale cell designed using an automatic layout technique and an automatic compaction technique. When replacing the lower cell with another separately created lower cell, effectively utilize the design pattern of the large-scale cell (other than the lower cell) that has already been designed,
It is an object of the present invention to provide a method for designing a semiconductor integrated circuit device that achieves high density while significantly reducing the number of design steps.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, in the present invention, a semiconductor integrated circuit device consisting of an upper cell and a replaceable lower cell incorporated in the upper cell is designed for each functional block cell corresponding to the upper cell and the lower cell, and In a method for designing a semiconductor integrated circuit device in which the arrangement is determined by automatic layout and compaction is applied to a design pattern based on the determined arrangement of functional block cells, when replacing the lower-order cells, the designed The pattern of the lower cell to be replaced and removed is extracted from the design pattern of the semiconductor integrated circuit device, the input/output terminal positions and the outer shape pattern of the lower cell to be inserted due to replacement are detected in advance, and the terminal position of the extracted lower cell pattern is detected. The input/output terminal position of the upper cell side corresponding to matches the input/output terminal position of the lower cell detected in advance, and the area after lower cell extraction of the upper cell matches the outer shape of the lower cell detected in advance. After the lower cell pattern has been extracted, compaction is applied to the design pattern of the upper cell as shown in FIG.
The lower cell pattern is inserted into the upper cell pattern that has been subjected to the compaction.

[Operation] According to the above-mentioned means, by the compaction technique,
The input/output terminal position of the upper cell side matches the input/output terminal position of the lower cell to be inserted, and the area after lower cell extraction of the upper cell matches the outer shape of the lower cell to be inserted. Therefore, it becomes possible to effectively utilize design patterns other than the extracted lower cell among design patterns of already designed integrated circuit devices.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic plan view for explaining the principle of the method for designing a semiconductor integrated circuit device according to the present invention, in which reference numeral A indicates an upper cell, reference numeral B.1. Both B and B indicate lower cells. Here, upper cell A forms the outer frame of lower cells B, B, and lower cell (lower cell to be replaced and removed) B
, , B (FIG. 1(C)) and corresponding input/output terminals (FIG. 1(B)). The block diagram shown in Figure 1(a) is designed to minimize the chip layout area by performing automatic layout and automatic compaction based on various data of three functional blocks: lower cells B, B, and upper cell A. A semiconductor integrated circuit device (large-scale cell) 10 is shown.

Now, suppose that the functional blocks of the lower cells B, B, which are incorporated in the upper cell A of this semiconductor integrated circuit device IO, are separately designed, and a new lower cell (replacement/insertion) as shown in FIG. 1(d) is created. lower cell) B, 'B,'
Consider the case where we obtain (smaller than lower cell B,, B,).

Here, the new lower cell Bl'lB,' is the lower cell B,
, B, is a rectangular cell similar to
The output terminals correspond exactly to those of the original lower cells B, B, (Fig. 1(C)).

(d)).

The replacement of the lower cell B11B with B,+,B% in the semiconductor integrated circuit device 10 is performed according to the following steps.

■First, cell B of the design pattern shown in Figure 1(a)
, ,B, is extracted (erases) (Fig. 1(b)). After the deletion, the information left in the upper cell △ is the input/output terminal position of the upper cell A that represents the connection relationship of the lower cells B, B, with the upper cell A, and the lower cell B.
,, B, is the shape of the frame on the upper cell A side that represents the outer shape of B.

■Next, the saved design information of the upper cell A, that is, the information representing the input/output terminal positions and the shape of the frame on the upper cell A side, is transferred to the newly designed lower cell BI'lB1.
Automatic compaction is performed again on the upper cell A by replacing it with new information representing the input/output terminal positions and its external shape.

As a result of the above-mentioned automatic compaction, the upper cell A shown in FIG. 1(b) is changed to the shape of the outer frame of the new lower cell Bl'lBj' and its person/output terminal position, as shown in FIG. 1(e). (upper cell A').

■A new large-scale cell lO' is created by inserting a new lower cell B,', B,' (Fig. 1(d)) into the upper cell A' obtained in step (2) above and replacing the lower cells. (Fig. 1(f)).

Next, B of the lower cell replaced in step ① above.
A specific example of a method of displaying information on l'+B* will be described.

Among the information on the lower cell (rectangular cell) B, 'B,', the information required when compacting the upper cell A to the upper cell A' is the outline of the lower cell Bl'lB,' to be replaced as described above. , namely, the length in the vertical and horizontal directions and the position of the person/output terminal. As shown in FIG. 2(a), this information is expressed, for example, in coordinates (x, y) with the origin (X, ) at any one of the four corners of the lower cell. At this time, the size of the lower cell can be expressed by the coordinates (x+p y,) of point Z1 in FIG. On the other hand, the input/output terminal positions of each lower cell are similarly expressed using x and y as parameters. Specifically, for example, terminal position 2. shown in FIG. 2(a). ．．
2. ．． 2. are respectively (o, y,) + (X@l O)
It is expressed as t(Xl+3'4).

Therefore, all information regarding the outer shape of the lower cell Bl'lB1' can be expressed by the two parameters x and y as described above, and such information is used in step (3) described above.
Automatic compaction is performed based on this information.

FIG. 2(b) shows an example of information replacement, in which only the horizontal length of the information representing the outer frame of the lower cell is converted from xj to xk (the vertical direction is not converted) and The automatic compaction is performed again when the coordinates of the terminal position Zj satisfy the condition (XQ, O)→(xm, O).

The large-scale cell lO1 obtained through steps ① to ① above is reduced by automatic compaction using the above-mentioned CAD method for compaction, which also targets the area of polygon data, taking into consideration the internal shape of the lower cell Bl'lBt'. A fine compaction at the mask level is achieved.

FIG. 3 is a diagram showing an example of a large-scale cell in which lower-order cells are actually replaced by the method described above. Code 1 in the diagram
01 is the lower cell (RAM) before replacement, 102 is the RA
It is an upper cell that dominates the outer frame of Ml0I, and 103 is the above-mentioned R
Other lower cells connected to AMI Ol are shown.

The large-scale cell 20 shown in FIG. 3(a) is a layout pattern obtained by connecting cells made up of these three functional blocks using automatic layout and automatic compaction.

Here, let us consider a case where the RAM 101, which is a lower cell, is actually replaced with a newly designed replacement RAM 110 (FIG. 3(b)).

In this case, first, other lower cells 103 electrically connected to RAMll0 are developed in advance.

After developing the other lower cell 103, first store the information before replacement in the RAM 102, and then remove (extract) the pattern in the RAM 102 from the layout pattern to obtain the upper cell pattern forming the outer shape of the large-scale cell. Figure 3 (C)
).

Next, the size (vertical and horizontal length) of the RAM 102 to be replaced and the position of each terminal are detected.

The above-mentioned stored information of RAM10I before replacement and the above-mentioned information of RAM110 after replacement are exchanged, and the upper cell pattern is automatically compacted.

Upper cell 102 after automatic compaction (Fig. 3(d)
) and create a new large-scale cell 20' (
Figure 3(e)) is obtained.

Further R is added to the large-scale cell 20' obtained in this way.
Automatic compaction is performed taking into account the internal shape of AMll0 to obtain a final, minimized large-scale cell.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

That is, in this embodiment, the RAM section is assumed to be the lower cell to be replaced, but the invention is not limited to this, and it is also possible to replace, for example, the ROM section and the bipolar transistor section in the same way.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in the present invention, a semiconductor integrated circuit device consisting of an upper cell and a replaceable lower cell incorporated in the upper cell is designed for each functional block cell corresponding to the upper cell and the lower cell, and the layout of these functional block cells is determined. In a method for designing a semiconductor integrated circuit device, in which the design pattern is determined by an automatic layout and compaction is performed on a design pattern based on the arrangement of the determined function pro and tuxel, when replacing the lower cell, the design pattern described above is The pattern of the lower cell to be replaced and removed is extracted from the design pattern of the semiconductor integrated circuit device, the input/output terminal positions and the outer shape pattern of the lower cell to be inserted due to replacement are detected in advance, and the terminal position of the extracted lower cell pattern is detected. The input/output terminal position of the upper cell side corresponding to matches the input/output terminal position of the lower cell detected in advance, and the area after lower cell extraction of the upper cell matches the outer shape of the lower cell detected in advance. After the lower cell pattern has been extracted, compaction is applied to the design pattern of the upper cell as shown in FIG.
Since the lower cell pattern is inserted into the upper cell pattern that has been subjected to the compaction, when replacing a specific lower cell stored in a large cell in a functional block with another separately created lower cell, It is possible to effectively utilize the design pattern of the large-scale cell (other than the lower-order cells) that has already been designed, thereby significantly reducing the number of design steps and further increasing the density.

A schematic plan view for explaining the principle of the measuring method, Figure 2 (a
) is an explanatory diagram showing a specific example of how to display information on lower cells necessary for compaction of upper cells, and Figure 2 (b) is an explanatory diagram showing an example of information replacement. FIG. 2 is a schematic plan view showing an example carried out.

A, 102... Upper cell (before compaction),
A', 102' ... Upper cell (after compaction), B,, B, ... Lower cell (replaced and removed), Bl'TBs' ... Lower cell (replaced and inserted) Cell, 10.10', 20.20'...Large-scale cell, 101 (before replacement) RAM, 110...
RAM (after replacement).

Figure 1 (f) No. figure (d) (e)

Claims (1)

[Claims] 1. A semiconductor integrated circuit device consisting of an upper cell and a replaceable lower cell incorporated in the upper cell is designed for each functional block cell corresponding to the upper cell and lower cell, and the arrangement of these functional block cells is automatically laid out. In a method for designing a semiconductor integrated circuit device in which compaction is performed on a design pattern based on the determined arrangement of functional block cells, when replacing the lower cell, the designed semiconductor integrated circuit Extracts the pattern of the lower cell to be replaced and removed from the device design pattern, detects in advance the input/output terminal positions and external shape pattern of the lower cell to be inserted by replacement, and corresponds to the terminal position of the extracted lower cell pattern. The input/output terminal position of the upper cell side matches the previously detected input/output terminal position of the lower cell, and the area after lower cell extraction of the upper cell matches the outer shape of the lower cell detected in advance. A semiconductor integrated circuit device characterized in that the design pattern of the upper cell after the extraction of the lower cell pattern is compacted, and the lower cell pattern is inserted into the compacted upper cell pattern. design method.