JPH03125980A - Trouble simulation system - Google Patents

Abstract

PURPOSE:To achieve a higher speed in treatment of a troubled simulation (SM) by judging validity of a trouble yet to be detected from a logic value obtained by analyzing an input signal with a fixed language length and condition of a trouble to eliminate a waste simulation (SM) step. CONSTITUTION:A logic gate G for assuming a trouble is divided into partial sets with the number thereof reduced by two from a bit W of the length of one language and connected with a carry. Then, troubles are inserted sequentially and a code of the W bit is analyzed at each input line to determine a logic value. The carry is passed to the subsequent logic G when a trouble is being inserted presently. The logic G receiving the carry judges a trouble yet to be detected which is possibly transmitted to an output of the logic G from a normal value of the logical value and a trouble detecting condition and if a trouble is determined to be effective, the insertion thereof is reported to an output value generating section 4 by the subsequent trouble alteration clock and a normal value of the output is determined from a normal value of all input signals. If a trouble is determined to be invalid, the carry is passed to the subsequent logic G. Then, as a result of a trouble SM, when a trouble is detected from a trouble detection signal being inserted, a detecting condition managing section 2 eliminates the trouble from a set of troubles yet to be detected.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 10) Problem to be solved by the invention (Figure 10) Means for solving the problem (Figure 1) Effect ( Fig. 1) Example (Fig. 2 to Fig. 10) Effects of the invention [Summary] Regarding the test pattern used in the process of inspecting the operation of an LSI chip, how much detection rate does the test pattern have? Regarding the fault simulation method to be investigated, for the purpose of speeding up the processing of the fault simulation and making it easier to change the circuit for the fault simulation, input for each input line regarding the logic gate included in the target circuit of the fault simulation is required. An input value analysis unit that analyzes an input signal with a fixed word length to which a fault has been assigned and obtains a logical value, and a detection unit that maintains the fault detection status using fault detection signals and deletes detected faults from the set of undetected faults. A status management unit determines the validity of the undetected fault from the logic value of the input signal and the fault detection status, and generates and reports a carry representing the own failure status based on the notified carry and the determination result. , and a validity determination/fault insertion unit that inserts a fault using a fault change clock, and an output value generation unit that generates an output signal of the logic gate based on the input signal and the fault insertion status.

(Industrial Application Field) The present invention relates to a failure simulation method for investigating the detection rate of a test pattern used in a process for inspecting the operation of an LSI chip. Input patterns are sequentially input into the target circuit for fault simulation, a single stuck-at fault is inserted into the target circuit, the output value of the target circuit is inspected, and when a fault is detected, a fault detection signal and a fault change clock are issued. , relates to a fault simulation method that simulates fault testing of a target circuit by sequentially updating input patterns.

When manufacturing an LSI, a test process is required to determine whether the chip has been manufactured as designed.

Currently, the creation of input patterns (test patterns) to check whether the chip operates correctly is increasingly automated, but depending on the circuit, it is not possible to obtain a high detection rate with just that, and some patterns are created manually. There are many situations where this is the case.

The detection rate of the created test pattern can be confirmed by fault simulation. As circuits have become larger in size in recent years, there has been an increasing demand for systems that can perform fault simulations on larger circuits at higher speeds.

(Prior art) Conventionally, when performing failure simulation, Figure 10 (a)
As shown in the figure, the circuit 42 to be simulated
A pattern to be inputted to the input pattern is prepared in advance and sequentially applied to the target circuit 42 by an input pattern generating section 41 that generates an input pattern. The fault insertion unit 43 sequentially inserts faults into the target circuit according to the assumed fault model. The output value inspection unit 44 observes the output of the target circuit 42 and confirms that the pattern generated by the input pattern generation unit 41 is detected by the fault insertion unit 43.
Check whether the inserted fault has been detected. Control unit 4
5 judges the result of the output value inspection section 44 and controls the replacement of the input pattern to the input pattern generation section 41;
Controls replacement of a fault in the fault insertion unit 43.

Here, regarding the target circuit 42, there has conventionally been a fault insertion method as shown in FIG. 1O(b).

In this method, a fault insertion module VC (Value Converter) is inserted into a signal line that assumes a fault in the target circuit.
51, 52, 53, and 54) were embedded and connected with a carry to form a VC chain 55, and failures were successively replaced.

(Problems to be Solved by the Invention) With the recent increase in the scale of target circuits, there is an increasing demand for a system that can execute failure simulation for large-scale circuits within practical time.

By the way, when automatically generating a test pattern, a fault simulation is performed to detect equivalent faults for the obtained pattern. This test generation algorithm is also realized by software and operated on large-scale computers, but there is a strong desire for a high-speed system that can handle large-scale target circuits.

Here, in order to speed up the processing and apply it to a large-scale target circuit, each part shown in FIG. 10(a) is constructed as a circuit,
A method has been devised to quickly simulate the operation of the entire circuit using a machine dedicated to logic simulation (Japanese Patent Application Laid-Open No. 1983-1999-1).
(See Publication No. 225972). In this method, the 10th
There was a fault insertion method shown in Figure (b), but the number of faults assumed in the target circuit is generally about three times the number of logic gates.
In this fault insertion method, it was necessary to additionally set VCs corresponding to the number of faults in the target circuit.

Further, when a VC actually inserts a fault, each VC inserts only faults that are likely to propagate based on the fault detection status for which it is responsible and the normal value of the signal line into which the fault is inserted.

These localities only hold on one signal line at most, and in reality, even if they are valid on the input signal line of a logic gate, they may insert useless faults that do not even propagate to the output of that gate. There are cases.

In order to solve the above problems, the present invention makes it possible to judge the effectiveness of fault injection at the logic gate level, speeds up fault simulation processing by eliminating unnecessary simulation steps, and improves fault simulation. The purpose of the circuit conversion processing for this was to provide a failure simulation method that only involved module replacement processing.

[Means to solve the problem]

In order to solve the above technical problems, the present invention, as shown in FIG. In the fault simulation method, when a fault is detected during inspection, a fault detection signal and a fault change clock are issued, and the input pattern is sequentially updated to simulate the fault test of the target circuit. , an input value analysis section 1 that analyzes an input signal of a fixed word length to which a fault is assigned to each input line and obtains a logical value; and an input value analysis section 1 that obtains a logical value by analyzing an input signal of a fixed word length to which a fault is input for each input line; The detection status management unit 2 deletes the undetected failures from the set of undetected failures, determines the validity of the undetected failures based on the logic value of the input signal and the detection status of the failure, and based on the notified carry and the determination result, detects the undetected failures. a validity determination/fault insertion unit 3 that generates and notifies a carry representing a fault situation and inserts a fault using a fault change clock; and an output value that generates an output signal of the logic gate based on the input signal and the fault insertion state. It has a generation section 4.

(Operation) The operation of the failure simulation method according to the present invention will be explained with reference to FIG. First, if one word length is W bits, for example, divide the logic gate that assumes a fault into (w-2) subsets, connect the logic gates belonging to each subset with carries, and sequentially insert faults. .

The input value analysis unit 1 analyzes the sign of the W bit to which a fault is assigned, which is input for each input line, and obtains a logical value. The logic gate that is currently inserting a fault raises a carry, and the logic gate that will insert the fault next is sought. The logic gate that receives or receives a carry is determined by the validity determination unit 3 to determine whether the logic gate is undetected or not, which may be propagated to the output of the logic gate, based on the normal value and failure detection status related to the logic value obtained by the input value analysis unit 1. Determine whether there is a failure. That is, when the result of a logical operation using a normal value (normal value of the output) is different from the result of an operation assuming a fault, it is determined that the fault is valid. Takes a carry when a valid fault exists, otherwise passes the carry to the next logic gate. At the next fault change clock, the fault insertion section 3 of the logic gate in question notifies the output value generation section 4 that a fault will be inserted.

It also launches a carry and passes it to the next logic gate. The output value generation unit 4 determines the normal value of the output from the normal values of all input signals, and sets a flag for fault assignment to insert a fault. Flags for other failures in the output are set by calculating the normal value of the input and the fault value (obtained from the normal value and the flag), and set to 1 if different from the normal value of the output, and 0 otherwise.

As a result of the fault simulation, after determining whether a fault has been detected through output value inspection, a fault change clock is issued, and the detection status management unit 2 detects a fault when a fault is detected by the fault detection signal currently being inserted. Drop (delete detected faults from the set of undetected faults). The fault insertion unit 3 notifies the output value generation unit 4 that fault insertion will be stopped, and the output value generation unit 4 sets the fault insertion flag to 0.

〔Example〕

Next, examples of the present invention will be described.

First, the configuration diagrams according to the embodiment shown in FIGS. 4 to 7 will be explained.

The logic gates assumed to be faulty in the target circuit are G1 and G.
It is 2. The output value inspection unit 25 observes the output of the target circuit and determines whether the pattern generated by the input pattern generation unit 15 is G
Check whether the inserted fault of G2 is detected.

Based on the detection result, the control unit 35 issues a detection signal and a failure change clock, and the input pattern generation unit 15
Controls the replacement of input patterns for . The input pattern generating section 15 sequentially generates large cover turns and applies them to the target circuit.

By the way, according to the present invention, in the case of one word length W bits (w-2
) fault assignment is now possible. For example, one word length is 4
The fault assignment method for bits is shown in Figure 3.

Next, in the input value analysis section 21, for example, in the fault assignment shown in FIG.

Since the detection signal is given in 2 bits (Dtct), the detection status management section 22 has a 2-bit (SA) register corresponding to the failure on each input/output signal line of the logic gate, and records the detection status of the failure. hold. The specifications of the detection signal and detection situation are shown in FIG. 5(b).

Carry consists of 2 bits (Ca, C1). Further, the validity determination/fault insertion section 23 has 2 bits (Ef, Df) as an internal state, and the specifications of these signals are shown in FIG. 5(C).

The validity determining unit 23 determines undetected faults that may be transmitted to the output depending on the function of the logic gate. Figure 5 (d
) is 2-man power AND, Figure 6 (e) is 2-man power 0R1 (f)
The conditions for determining the effectiveness of NOT are shown in 2-manpower XOR1(g). In the figure, A and B represent input signal lines, and 01 represents an output signal line. In addition, . indicates that the fault will propagate to the output of the logic gate, O indicates that there is a possibility that the fault will propagate if the value of the input with logic value X is set to O or 1, and the fault output value is Let it be Y. In the diagram (*1) and (*2), when the fault O is inserted, the fault output value becomes X, and when the fault is inserted, the fault output value becomes 1 or 0, so the output changes depending on the fault detection status. change.

By the way, the AND gate (d) has a stuck-at-0 fault at A, B, and Ot, the OR gate (e) has a stuck-at-1 fault at A, B, and Ot, and the NOT gate (g) has a stuck-at-0 fault at A and O.
Since the stuck-at-1 fault at t, the stuck-at-1 fault at A, and the stuck-at O fault at Ot are equivalent faults, the detection status management unit 2
2, the registers corresponding to these faults can be shared. Further, the validity determination unit 23 can also perform the determination all at once.

Furthermore, as shown in FIG. 6(h), the validity determining unit 23 determines that the carry is valid when the carry input is 01=1 and the failure indicated by O or · is not detected for each input. It is determined that a failure exists and Ef=1. Failure insertion part 23
As shown in FIG. 6(i), when a fault change clock is issued, if a valid fault exists (Ef=1), a fault is inserted and the insertion is stopped at the primary clock. As shown in FIG. 7(j), the carry output is set to CI=1 by the logic gate into which a fault is currently inserted, and 01 by the logic gate having the next valid undetected fault. Also, when there are no undetected faults in the logic gates before it, Ca=1
shall be.

As shown in FIG. 7(k), the detection status management unit 22 updates the value of the register corresponding to the inserted fault in response to the detection signal when the fault change clock is issued. Otherwise, the previous state is maintained.

The output value generation unit 24 obtains an output value from the input value and the fault insertion status. The fault value to be inserted into the logic gate is determined from FIGS. 5(d) to 6(g) according to the function of the gate, and a flag is set at the bit position where the fault is inserted. For other failure values, input failure values are determined from the input normal values and flag inputs, and output values are calculated based on the input failure values. If the result is different from the normal output value, a flag is set for the output signal.

For logic gates that require three or more manpower, modules are generated in the same manner by the expansion shown in FIGS. 4 to 7.

Next, the fault allocation method according to the present invention will be explained.

Here, fault assignment means that when one word length is W bits, one normal circuit and (w-2) faulty circuits are represented by a code of W bits. In other words, the logical value (normal value) of a normal circuit is expressed with a 2-bit sign, and the difference between the logical value of a faulty circuit and the logical value of a normal circuit is expressed using a 1-bit sign, only indicating whether it is different from the normal value. Therefore, in the case of one word length W bits, (w-2) fault assignments can be made. FIG. 2(b) shows the modulus of fault assignment to codes when the length of one word is W bits. 2 for the logic value (normal value) of a normal circuit
Assign bits to represent the three values Oll and X. Only one bit is assigned as a flag to a fault inserted in parallel, and it is set to 1 if the logic value (failure value) of the faulty circuit is different from the normal value, and O if it is the same. As a result, it is now possible to assign twice as many faults to one word as in the conventional method shown in FIG. 2(a).

Here, the method for assigning faults to codes in the case where one word length is 4 bits as shown in FIG. 3 will be explained.

In Figure 3, [symbol] is an external signal input to the logic gate,
[Logical value] is a value obtained by analyzing the sign by the input value analysis section.

In this case, two faults can be inserted in parallel. When the normal value is O or 1, and when the normal value is X and the influence of the failure is not propagated, each code corresponds one-to-one with the code in the conventional system (■ to ■). When the normal value is X and one of the fault values is not X, or when the normal value is 0 or 1 and one of the fault values is X, the fault detection status is unknown (■ to ■). In Figure 3(a), the normal value is
When the fault value is not X, the fault assignment that determines the fault shows the modulus. In this method, when the normal value is 0 or 1 and the fault value is X, the normal value can be determined, but information regarding which fault influence may propagate is lost (Φ to ■). Furthermore, when at least one of the fault values is X, the distinction between other faults in which fault values different from normal values are propagated is lost (■[phase]).

■■). FIG. 3(b) shows a coding method (■ to ■) for determining a failure when the normal value is O or 1 and the failure value is X. With this encoding method, when the normal value is X and the faulty value is not
). Although some information is lost in both methods shown in FIGS. 3(a) and 3(b), the meaning will not be misunderstood.

Next, we will calculate the processing time for failure simulation using a specific example and compare it with the conventional example. The results of the fault simulation according to the embodiment of the present invention shown in FIG. 4(a) are shown in FIG.
Figure 8 (b) shows the results of the conventional method in Figure 10 (b).
Shown in a). For simplicity, only one failure is inserted at a time.

In the figure, Fc1k represents a failure change clock, and Pc1k represents an input pattern change clock. In the output values, D represents normal value=1 and failure value=0, and Db represents normal value=O1 failure value=1. Each VC injects a fault when Df=1. When 5aO11 is 1, it means that it has been detected. In the figure, * means the value O. For easy understanding, failures during insertion are indicated by @ in the column 5aO11 in the figure. In FIG. 9(b), in order to match the number of failures with FIG. 10(b), failures are assumed only on the input sides of logic gates G1 and G2. That is, for a failure on the output side, the register value of the detection status management unit is initially set to detected.

The input pattern is (S, A, B) = (0, O, O
), (0,0,1),... (1°1.1) is applied.

In the conventional method shown in FIG. 8(a), first, Pc1k is issued at time 1 and the first pattern (0, O, O) is input. From time 2, Fc1k is issued and each VC sequentially inserts a valid fault. With this input pattern, as a result of four fault insertions,
Only a stuck-at-1 fault in VC54 is detected. Fc at time 5
Since the last VC inserted a fault at 1k, Pc
Issue 1k and input the next pattern (0, 0, 1).

Putter: / (0,1,0) The normal input value of vC53 is 1, but a stuck-at-0 fault has been detected, VC5
The normal input value of 4 is 0, but the stuck-at-1 fault has already been detected, so no fault is inserted into these two VCs. The same process is repeated and all failures are detected at time 27, so the process ends. On the other hand, in the method according to the present invention FIG. 9(b),
It is G2 that inserts a fault by Fc1k issued at time 2. This is because the input of G1 is (0,0) and the failure on the input side is not valid according to Figure 5(d).
This is because G1 passes carry C1. In the next pattern, the input of G2 becomes (1°1), and at time 4, a stuck-at-0 fault at input C and a stuck-at-0 fault at input d can be detected simultaneously. Thereafter, the same process is repeated, and at time 16, all failures are detected and the process ends. In this way, by using the method according to the present invention, it is possible to complete processing with a smaller number of clocks.

〔Effect of the invention〕

As explained above, in the present invention, by making it possible to judge the effectiveness of fault insertion at the logic gate level and having the function of inserting only faults that affect the output, unnecessary simulation steps can be eliminated. It has become possible to perform fault simulations on large-scale circuits at high speed.

In addition, by providing a function to insert faults into the circuit's logic gate itself, circuit changes for fault simulation can be performed simply by replacing modules.
The overall number of modules can now be reduced.

[Brief explanation of the drawing]

Figure 1 is a principle block diagram of the present invention, Figures 2 and 3 are explanatory diagrams of an embodiment, Figures 4 to 7 are configuration diagrams of an embodiment, and Figures 8 and 9 are simulations. As a result, FIG. 10 is a block diagram of the conventional example. 1.21. ...Input value analysis section 2.22. ...Detection status management section 3.23. ...Efficacy determination/fault insertion section 4.24.・
...Output value generation section 15...Input pattern generation section 25...Output value inspection section 35...Control section
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Claims (1)

[Claims] Input patterns are sequentially input to a target circuit for fault simulation, a single stuck-at fault is inserted into the target circuit, and the output value of the target circuit is inspected. When a fault is detected, a fault detection signal and In a fault simulation method that issues a fault change clock and sequentially updates the input pattern to simulate fault inspection of the target circuit, a fixed word that assigns a fault to be input to each input line regarding the logic gate included in the target circuit is used. an input value analysis unit (1) that analyzes a long input signal and obtains a logical value, and a detection status management unit that maintains the failure detection status based on the failure detection signal and deletes the detected failure from the set of undetected failures. (2) Determine the validity of the undetected fault from the logical value of the input signal and the fault detection status, and generate and notify a carry representing the self-failure status based on the notified carry and the determination result. , and includes a validity determination/fault insertion unit (3) that inserts a fault using a fault change clock, and an output value generation unit (4) that generates an output signal of the logic gate based on the input signal and the fault insertion status. A failure simulation method featuring: