JPH0312326B2 - - Google Patents
Info
- Publication number
- JPH0312326B2 JPH0312326B2 JP58005851A JP585183A JPH0312326B2 JP H0312326 B2 JPH0312326 B2 JP H0312326B2 JP 58005851 A JP58005851 A JP 58005851A JP 585183 A JP585183 A JP 585183A JP H0312326 B2 JPH0312326 B2 JP H0312326B2
- Authority
- JP
- Japan
- Prior art keywords
- clock
- self
- information processing
- signal
- supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010365 information processing Effects 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 2
- 230000010355 oscillation Effects 0.000 description 7
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Description
【発明の詳細な説明】
本発明は、情報処理装置におけるクロツク供給
制御方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock supply control method in an information processing device.
従来のクロツク供給方式の二重化装置の例を第
１図に示す。 An example of a conventional clock supply type duplexing device is shown in FIG.
第１図において、両情報処理装置＃０，＃１の
クロツク供給回路は全く同一の回路構成であり、
１，２１はクロツク供給源を決定するセツト、リ
セツト端子のみを有するフリツプフロツプ（以下
「クロツクセルフFF」と略す。）、２，３，２２，
２３は論理積ゲート、４，５，６，２４，２５，
２６は論理和ゲート、７，２７はクロツク発振
源、８，２８は外部より前記クロツクセルフFF
１，２１をセツトする信号、９，２９は図には表
わされていない周知の緊急制御回路よりクロツク
セルフFF１，２１をセツトする信号、１０，３
０は外部よりクロツクセルフFF１，２１をリセ
ツトする信号、１１，３１は前記緊急制御回路よ
りクロツクセルフFF１，２１をリセツトする信
号、１２，３２は論理和ゲート６，２６の出力よ
りクロツクセルフFF１，２１をリセツトする信
号、１３，３３は自装装置用クロツク供給信号、
１４，３４は他装置へクロツクを供給する交叉信
号、１５，３５は入力信号の否定を表わす記号で
ある。 In FIG. 1, the clock supply circuits of both information processing devices #0 and #1 have exactly the same circuit configuration.
1, 21 are flip-flops having only set and reset terminals for determining the clock supply source (hereinafter abbreviated as "clock self FF"); 2, 3, 22;
23 is an AND gate, 4, 5, 6, 24, 25,
26 is an OR gate, 7 and 27 are clock oscillation sources, and 8 and 28 are externally connected clock self FFs.
9 and 29 are signals for setting the clock self FF1 and FF21 from a well-known emergency control circuit not shown in the figure.
0 is a signal for resetting clock self FF1, 21 from the outside, 11, 31 is a signal for resetting clock self FF1, 21 from the emergency control circuit, 12, 32 is a signal for resetting clock self FF1, 21 from the output of OR gates 6, 26. signals, 13 and 33 are clock supply signals for self-equipped devices,
14 and 34 are cross signals for supplying clocks to other devices, and 15 and 35 are symbols representing negation of input signals.
第１図において、通常は例えば第１クロツクセ
ルフFF１の出力が“１”のとき第２のクロツク
セルフFF２１の出力が“０”であり、情報処理
装置＃０内のクロツク発生源７のクロツクが各ゲ
ートを経て、各情報処理装置＃０，＃１の自装置
用クロツク供給信号１３，３３として供給され
る。第１のクロツクセルフFF１の出力が“０”
であり第２のクロツクセルフFF２１の出力が
“１”であるときは、情報処理装置＃１内のクロ
ツク発生源２７のクロツクが供給される。 In FIG. 1, normally, for example, when the output of the first clock self FF1 is "1", the output of the second clock self FF21 is "0", and the clock of the clock generation source 7 in the information processing device #0 is clocked at each gate. The signal is then supplied to each information processing device #0, #1 as its own clock supply signal 13, 33. The output of the first clock self FF1 is “0”
When the output of the second clock self FF21 is "1", the clock from the clock generation source 27 in the information processing device #1 is supplied.
ところが、各情報処理装置＃０，＃１のクロツ
ク供給用電源を投入する場合、使用している集積
回路の特性によりクロツクセルフFF１，２１が
電源投入時にセツトする場合とセツトしない場合
がある。 However, when turning on the clock supply power to each information processing device #0, #1, the clock self FF1, 21 may or may not be set when the power is turned on, depending on the characteristics of the integrated circuit used.
第１，第２クロツクセルフFF１，２１が共に
セツトする場合は、情報処理装置＃０へのクロツ
ク供給は、第１のクロツクセルフFF１の出力が
“１”であるため、クロツク発振源７のクロツク
は論理積ゲート２のゲート条件を満足し、論理和
ゲート４を経由して、自装置用クロツク供給信号
１３として供給される。一方、情報処理装置＃１
へのクロツク供給は、第２のクロツクセルフFF
２１の出力が“１”であるため、クロツク発振源
２７のクロツクは論理積ゲート２２のゲート条件
を満足して、論理和ゲート２４を経由して自装置
用クロツク供給信号３３として供給される。この
ようなことから、各情報処理装置＃０，＃１で
は、各々自装置のクロツクを使用して動作するこ
とになり、各装置間のクロツクの相間関係が保証
されない。いるれか一つの装置のクロツクで動作
する条件に違反するので、外部よりどちらかのク
ロツクセルフFFをリセツトする必要ある。 When both the first and second clock self FF1 and FF21 are set, the clock from the clock oscillation source 7 is a logic clock because the output of the first clock self FF1 is "1" to supply the clock to the information processing device #0. The signal satisfies the gate conditions of the product gate 2 and is supplied as the own device clock supply signal 13 via the OR gate 4. On the other hand, information processing device #1
The clock supply to the second clock self FF
Since the output of the clock oscillation source 21 is "1", the clock of the clock oscillation source 27 satisfies the gate condition of the AND gate 22 and is supplied via the OR gate 24 as the clock supply signal 33 for the own device. For this reason, each of the information processing devices #0 and #1 operates using its own clock, and the correlation of the clocks between the devices is not guaranteed. Since this violates the condition of operating on the clock of only one device, it is necessary to reset either clock self FF externally.
第１，第２のクロツクセルフFF１，２１が共
にセツトされていない場合は、各情報処理装置
＃０，＃１間で互の相手装置のクロツクを使用し
動作するため、前述の第１，第２のクロツクセル
フFF１，２１が共にセツトする場合と同様の不
都合が発生する。 If both the first and second clock self FF1 and FF21 are not set, each information processing device #0 and #1 operate using the clock of the other device, so the first and second clock self described above The same problem occurs when the clock self FF1 and FF21 are both set.
本発明は、このような欠点を解決するために、
電源投入にクロツク供給源を唯一つに決定するよ
うにしたものである。すなわち二重化されたクロ
ツク供給源を持ち、いずれかのクロツクにより動
作させる情報処理装置のクロツク供給制御方式に
おいて、クロツク供給源を決定するクロツクセル
フFFを両系の情報処理装置に有し、自系の電源
回路で作成され電源出力安定後に発生する信号
と、他系のクロツクセルフFFの出力信号の論理
信号とを実質的に論理積し、その論理積の出力信
号を両系のクロツクセルフFFの入力信号として
加えることにより、クロツク供給源を唯一つに初
期設定することを特徴とするクロツク供給制御方
式である。 In order to solve these drawbacks, the present invention has the following features:
Only one clock supply source is determined when power is turned on. In other words, in a clock supply control method for an information processing device that has dual clock supply sources and is operated by one of the clocks, both information processing devices have a clock self FF that determines the clock supply source, and the information processing device of both systems has a clock self FF that determines the clock supply source, and the power supply of the own system is used. The signal created by the circuit and generated after the power supply output stabilizes is effectively ANDed with the logic signal of the output signal of the clock self FF of the other system, and the output signal of the AND is added as the input signal of the clock self FF of both systems. This is a clock supply control method characterized by initially setting only one clock supply source.
第２図は本発明を二重化情報処理装置へ適用し
た場合の回路例であり、第３図及び第４図は第２
図の動作を示すタイムチヤートである。第２図に
おいて、５２，８２は論理積ゲート、６１，９１
は電源回路で作成され電源出力安定後発生する信
号、６２，９２はクロツク供給出力決定信号の交
叉信号、６８，９８は入力信号の否定を表わす符
号である。その他の符号は、第１図のものと同様
のものである。 FIG. 2 shows an example of a circuit when the present invention is applied to a redundant information processing device, and FIGS.
It is a time chart showing the operation of the figure. In FIG. 2, 52, 82 are AND gates, 61, 91
is a signal created by the power supply circuit and generated after the power supply output is stabilized, 62 and 92 are cross signals of the clock supply output determination signal, and 68 and 98 are symbols representing negation of the input signal. Other symbols are the same as those in FIG.
第２図，第３図によつて、０側情報処理装置
＃０から先にクロツク供給用電源を投入した場合
に第１クロツクセルフFF１がその集積回路の特
性によりセツトし、次に１側情報処理装置＃１の
クロツク供給用電源を投入する場合について説明
する。時刻t0に０側情報処理装置＃０のクロツク
供給用電源を投入すると、その後時刻t1に第１の
クロツクセルフFF１がセツトする。この信号９
２は論理積ゲート２の一方の入力となり、また１
側情報処理装置＃１の論理積ゲート８２のクロツ
ク供給出力決定信号９２の“１”が反転して
“０”で入力する。時刻t0，t1の後の時刻t2に１側
情報処理装置＃１のクロツク供給用電源を投入す
ると、すでに論理積ゲート８２の一方の入力はク
ロツク供給出力決定信号９２が反転された“０”
になつており、時刻t2の後の時刻t3に１側情報処
理装置＃１のクロツク供給用電源回路で作成され
電源出力安定後発生する信号９１が前記論理積ゲ
ート８２の一方の入力との論理積をとることによ
り出力“０”となる。したがつて、論理和ゲート
２５を経由しては、第２のクロツクセルフFF２
１をセツトすることができない。時刻t3では、０
側及び１側情報処理装置＃０，＃１へのクロツク
供給は、０側のクロツク発振源７からされる。 2 and 3, when the clock supply power is turned on first from the 0-side information processing device #0, the first clock self FF1 is set according to the characteristics of the integrated circuit, and then the 1-side information processing device #0 is turned on. The case of turning on the clock supply power of device #1 will be explained. When the clock supply power of the 0-side information processing device # 0 is turned on at time t0, the first clock self FF1 is set at time t1 . This signal 9
2 becomes one input of AND gate 2, and 1
The "1" of the clock supply output determination signal 92 of the AND gate 82 of the side information processing device #1 is inverted and input as "0". When the clock supply power of the first-side information processing device #1 is turned on at time t 2 after time t 0 and t 1 , one input of the AND gate 82 has already detected that the clock supply output determination signal 92 has been inverted. 0"
At time t3 after time t2 , the signal 91 generated by the clock supply power circuit of the first information processing device #1 and generated after the power supply output stabilizes is connected to one input of the AND gate 82. The output is "0" by taking the logical product. Therefore, the second clock self FF2 passes through the OR gate 25.
Cannot set to 1. At time t 3 , 0
Clock is supplied to the side and first side information processing devices #0 and #1 from the clock oscillation source 7 on the zero side.
次に、第２図，第４図によつて、０側情報処理
装置＃０から先にクロツク供給用電源を投入した
ときに、第１のクロツクセルフFF１がその集積
回路の特性によりセツトしない場合について説明
する。時刻t0に０側のクロツク供給用電源を投入
しても信号９２は“０”となつており、その後時
刻t2に１側情報処理装置＃１のクロツク供給用電
源を投入した場合、すでに論理積ゲート８２のク
ロツク供給出力決定信号９２の“０”が反転して
“１”で入力しているため、時刻t2の後の時刻t3
にクロツク供給用電源回路で作成され電源出力安
定後発生する信号９１が前記論理積ゲート８２の
他方の入力に加えられると、論理和ゲート２５を
経由して第２のクロツクセルフFF２１をセツト
する。このセツトの信号は０側の論理積ゲート５
２のゲート条件を成立させないめ、第１のクロツ
クセルフFF１は依然リセツト状態を維持し続け
る。従つて、時刻t3では、０側及び１側情報処理
装置＃０，＃１へのクロツク供給は１側のクロツ
ク発振源２７からされる。 Next, as shown in FIGS. 2 and 4, when the clock supply power is turned on from the 0-side information processing device #0 first, the first clock self FF1 is not set due to the characteristics of its integrated circuit. explain. Even if the power supply for clock supply on the 0 side is turned on at time t 0 , the signal 92 remains "0", and when the power supply for clock supply on the 1 side information processing device #1 is turned on at time t 2 , the signal 92 is already "0". Since "0" of the clock supply output determination signal 92 of the AND gate 82 is inverted and inputted as "1", the clock supply output determination signal 92 of the AND gate 82 is input as "1", so that at time t 3 after time t 2
When the signal 91 generated by the clock supply power supply circuit and generated after the power supply output is stabilized is applied to the other input of the AND gate 82, the second clock self FF 21 is set via the OR gate 25. This set of signals is connected to the AND gate 5 on the 0 side.
In order not to satisfy the second gate condition, the first clock cell FF1 continues to maintain the reset state. Therefore, at time t3 , the clock oscillation source 27 on the 1 side supplies the clock to the 0 side and 1 side information processing devices #0 and #1.
以上説明したように本発明によれば、クロツク
セルフFFに用いている電子回路の電源投入時の
特性によらず、各情報処理装置へ供給されるクロ
ツク源が必ず唯一つに決定されるので、外部より
初期設定をしなくともよく、電源投入時より情報
処理装置が安定して動作する利点がある。 As explained above, according to the present invention, regardless of the power-on characteristics of the electronic circuit used in the clock self-FF, only one clock source is always determined to be supplied to each information processing device. There is an advantage that there is no need to perform initial settings, and the information processing device operates stably from the moment the power is turned on.
第１図は従来のクロツク供給方式の回路例、第
２図は本発明を説明するめの回路例、第３図，第
４図は第２のタイムチヤートの例である。１，２
１……クロツクセルフFF、２，３，２２，２３，
５２，８２……論理積ゲート、４，５，６，２
４，２５，２６……論理和ゲート、７，２７……
クロツク発振源、６１，９１……クロツク供給用
電源の出力安定後に発生する信号、６２，９２…
…クロツク供給出力決定信号。
FIG. 1 shows an example of a circuit using a conventional clock supply system, FIG. 2 shows an example of a circuit for explaining the present invention, and FIGS. 3 and 4 show examples of a second time chart. 1,2
1...Clock self FF, 2, 3, 22, 23,
52, 82...AND gate, 4, 5, 6, 2
4, 25, 26...OR gate, 7, 27...
Clock oscillation source, 61, 91... Signal generated after the output of the clock supply power supply stabilizes, 62, 92...
...Clock supply output determination signal.
Claims (1)
かのクロツクにより動作させる情報処理装置のク
ロツク供給制御方式において、 クロツク供給源を決定するクロツクセルフFF
を両系の情報処理装置に有し、 自系の電源回路で作成され電源出力安定後に発
生する信号と、他系のクロツクセルフFFの出力
信号の論理信号とを実質的に論理積し、 その論理積の出力信号を両系のクロツクセルフ
FFの入力信号として加えることにより、クロツ
ク供給源を唯一つに初期設定することを特徴とす
るクロツク供給制御方式。[Scope of Claims] 1. In a clock supply control method for an information processing device that has dual clock supply sources and is operated by one of the clocks, a clock self-FF that determines the clock supply source.
is included in the information processing devices of both systems, and the signal created by the power supply circuit of the own system and generated after the power supply output stabilizes is effectively ANDed with the logic signal of the output signal of the clock self FF of the other system, and the logic is calculated. The output signal of the product is applied to the clock self of both systems.
A clock supply control method characterized by initially setting the clock supply source to only one by adding it as an input signal to the FF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP585183A JPS59132023A (en) | 1983-01-19 | 1983-01-19 | Clock supply control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP585183A JPS59132023A (en) | 1983-01-19 | 1983-01-19 | Clock supply control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59132023A JPS59132023A (en) | 1984-07-30 |
| JPH0312326B2 true JPH0312326B2 (en) | 1991-02-20 |
Family
ID=11622492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP585183A Granted JPS59132023A (en) | 1983-01-19 | 1983-01-19 | Clock supply control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59132023A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008190762A (en) * | 2007-02-02 | 2008-08-21 | Daikin Ind Ltd | Case for heat exchanging device, and heat exchanging device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5171647A (en) * | 1974-12-18 | 1976-06-21 | Hitachi Ltd | KUROTSUKUSENTA KUHOSHIKI |
-
1983
- 1983-01-19 JP JP585183A patent/JPS59132023A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5171647A (en) * | 1974-12-18 | 1976-06-21 | Hitachi Ltd | KUROTSUKUSENTA KUHOSHIKI |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59132023A (en) | 1984-07-30 |
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