JPH03123118A - Programmable switch circuit - Google Patents

Abstract

PURPOSE:To quickly define the intermittent state of a switch even immediately after a power source is turned on, without increasing the power sonsumption by connecting a PMOS transistor in series to an NMOS transistor. CONSTITUTION:The circuit is provided with a PMOS transistor P1 of a floating gate type having a floating gate FG held in common with an NMOS transistor N1 and N2, and also, its control gate is connected to a power source Vcc as a high potential side. Accordingly, a period when the transistor P1 and N1 are both turned on is limited to an extremely short time such as the charge is injected to the floating gate FG, etc., a through-current can be nearly disregarded. In such a way, an output terminal Q can be charged quickly even immediately after the power source is turned on, without increasing the power consumption. As a result, an unstable state of a switch means immediately after the power source is turned on can be eliminated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a programmable switch circuit used in various logic circuits, and in particular, the present invention relates to a programmable switch circuit used in various logic circuits, and in particular, the present invention relates to a programmable switch circuit used in various logic circuits. , relates to a programmable switch circuit that quickly determines the on/off state of a switch.

[Conventional technology]

For example, conventional programmable switch circuits include:
There is something like the one shown in Figure 3.

This means that the output terminal Q of the memory circuit M is connected to the gate of N
This is a switch circuit that connects or disconnects wirings 1 and 2 by a transfer gate 1-NT consisting of a channel MOS transistor (hereinafter referred to as an NMOS transistor), and has a high potential (logical value "L") at the output terminal Q. is output, the transfer gate NT is turned on and the wirings 1 and 2 are connected, and when the output terminal Q is outputted with a low potential (logical value "0"), the transfer gate NT is turned on. , is turned off, and the wirings 1 and 2 are disconnected.

The memory circuit M is composed of a non-volatile memory section 3 and a charge injection section 4, and the non-volatile memory section 3 is connected to a power supply V
An electric resistance R and a floating gate type NMOS transistor N1 are connected in series in this order between CC and ground, and the control gate of the NMOS transistor N1 is connected to a power source (2). , is configured by connecting to.

Furthermore, the floating gate FG of NMO3I-Randisuk N is shared with the floating gate of floating gate type NMOS transistor N2 constituting the charge injection section 4, and NMO3) Ranjisku N2 is connected between bit line B and ground. and its control gate is connected to the word line W.

Now, assuming that no charge is injected into the floating gate FG, the threshold voltage of the NMOS transistor NI maintains its normal value (about 2V), so the power supply Vc
By c (approximately 5 .mu.), NMO3) is turned on, and conduction is established between the output terminal Q and the ground, and the potential of the output terminal Q becomes a low potential.

Therefore, transfer gate N is turned off, so that wirings 1 and 2 are disconnected.

Furthermore, when a suitable high voltage is applied to the bit line B and the word line W and the negative charge generated in the NMOS transistor N2 is injected into the floating gate FC, the threshold voltage of the NMOS transistor N sharing the floating gate FG will be increased. rises. Then, the threshold voltage is the power supply ■
. Floating gate FG until voltage group C becomes 2
If charge is injected into the NMOS transistor N1, the NMOS transistor N1 is always turned off.

Then, the output terminal Q is disconnected from the ground and is charged by the power supply VCC connected through the electric resistance R to have a high potential, so the transfer gate NT is turned on and the wirings 1 and 2 are connected. becomes.

Note that the charge injected into the floating game (FC) is
It can be erased by irradiating it with ultraviolet light, and NMO3I-
The threshold voltage of transistor N1 can be reset to the initial value.

In this way, by setting the floating gate FC in a state in which charges are not injected (non-writing state) or in a state in which charges are injected (writing state), the output terminal Q becomes a low potential or a high potential, so that the memory The circuit M can store 1 bit of data.

Furthermore, the charge injected into the floating gate FC is transferred to the power supply ■. Since the data is stored regardless of whether power is supplied or not, the nonvolatile storage unit 3 stores the data even when the power is turned on again.

Therefore, by defining the conduction state between wires 1 and 2 using such a programmable switch circuit, it is possible to easily realize a logic circuit having a desired logic function. ), etc.

[Problem to be solved by the invention]

However, such conventional programmable switch circuits have the following unresolved problems.

That is, since the power supply VCC and the NMOS transistor N are connected by an electric resistance R, when the NMOS transistor N is turned on, the electric resistance R and the NMOS transistor N are connected.
A through current flows between the power supply VCC and ground via the S transistor N1.

This through current continues to flow when the NMO3I-transistor N is on, that is, when the power supply Cc is supplied and no charge is injected into the floating gate FC, which has a large effect on power consumption. I end up giving.

Conventionally, the resistance value of the electrical resistance R was set to a large value (several 10 to several 10
(approximately 0 GΩ) to prevent a large through current from flowing.

However, by increasing the resistance value of the electrical resistance R, power consumption can be reduced;
When the power supply VCC is turned on again with charge being injected into the output terminal Q and a high potential is expected to be output from the output terminal Q,
The drawback is that it takes a long time to charge the battery.

Therefore, immediately after the power is turned on, the state of the transfer gate NT, that is, the conduction state of wires 1 and 2, is not determined, so the state of the logic circuit defined by the connection state of these wires 1 and 2 becomes unstable. Put it away.

This invention was made by focusing on the unresolved problems of the conventional technology, and is a programmable technology that quickly determines the on/off state of the switch even immediately after power is turned on, without increasing power consumption. The purpose is to provide switch circuits.

[Means to solve the problem]

In order to achieve the above object, the programmable switch circuit of the present invention has floating gate type P channel MO3I-
Transistor and floating gate type N-channel MO
a switch means which is connected via an S transistor, and which connects the control gates of the two transistors to a high potential side or a low potential side, and which is turned on and off according to the potential of a connection point between the two transistors; charge injection means for injecting charge into the floating gate of the device.

[Effect]

Since a floating gate type P-channel MOS transistor (hereinafter referred to as a PMOS transistor) and a floating gate type NMOS transistor are connected in series, no charge is injected into the floating gates of both transistors. If their control gates are connected to the high potential side, P
The MOS transistor is turned off and the NMO3I-transistor is turned on. As a result, the potential on the side to which the NMOS transistor is connected is supplied to the switch means via the connection point. On the other hand, if the control gate is connected to the low potential side, the PMOS transistor is turned on and the NMOS transistor is turned off, so the switching means is supplied with the potential of the side to which the PMOS transistor is connected via the connection point. Ru.

Then, if charge is injected into the floating gate,
Since the threshold voltages of the PMOS and NMOS transistors change, an operation opposite to that described above can be obtained.

Therefore, when both the PMOS transistor and the NMOS transistor are turned on, it is limited to a very short time such as when injecting charge into the floating gate, so the through current can be almost ignored, and power consumption can be kept low. .

Therefore, there is no need to use a high load resistor as in the conventional case, so it does not take much time to charge the output terminal when the power is turned on.

〔Example〕 Embodiments of the present invention will be described below based on the drawings.

1 and 2 are diagrams showing an embodiment of the present invention, and FIG. 1 is a circuit diagram showing the configuration of the embodiment.

Note that the same parts and the like as in FIG. 3 explained in the above-mentioned conventional technique are given the same reference numerals, and the redundant explanation thereof will be omitted.

That is, in the configuration of this embodiment, an NMOS transistor N and a floating gate type PMOS transistor P having a floating gate FC shared with N2 are provided in place of the electrical resistor R in FIG. 3, and the control gate thereof is It is the same as the conventional programmable switch circuit described above except that it is connected to the power supply VCC as the high potential side.

Now, assume that no charge is injected into the floating gate FC (before writing), and in that state, the NMO
The threshold voltage of the S transistor N1 is expressed as A, (the amount of deviation from the ground voltage as the low potential side), and the threshold voltage of the PMOS transistor P is expressed as -VTP (the amount of deviation from the voltage of the power source). ) (see Figure 2).

In this case, since the control gates of the PMOS transistor P1 and the NMOS transistor N are connected to the power supply VCC, the PMOS transistor P is turned off and the NMOS transistor N1 is turned on.

Therefore, since the output terminal Q is disconnected from the power supply VCC and connected to the ground, its potential becomes a low potential, and the transfer gate Nt as a switching means is turned off, and the wirings 1 and 2 are disconnected.

Next, when a negative charge is injected into the floating gate 1-FC by the charge injection unit 4 as a charge injection means, the PMO
3) The threshold voltage of Ranjisk P decreases to -VTP
+ΔVTP, and the threshold voltage of the NMOS transistor N increases to +ΔVTN.

Note that the changes in threshold voltage ΔV7p and ΔVTN are as follows:
This value is determined by the size of the transistors P and N, and by adjusting the thickness of the insulating layer as appropriate, Δ
It is also possible to set VT, -Δ■A.

Then, the negative charge is injected until the threshold value after injecting the charge (after writing) is -■A, +Δ■7F〉0 and VTN+ΔVyH#V(((), as shown in FIG. inject.

Then, the PMO3I-transistor P1 goes into depletion mode and turns on, and the NMOS transistor N1 turns off, so the output terminal Q is disconnected from the ground and the power supply ■. Since it is connected to C, it is charged and becomes a high potential, and the transfer gate NT is turned on.
Wirings 1 and 2 are in a connected state.

In this way, in this embodiment, under normal operating conditions,
PMOS transistor P1 and NMOS transistor N
1 are not turned on at the same time, no large through current flows between the power supply VCC and ground.

Therefore, power consumption can be kept low, and
Power ■. Since there is no need to provide a high load resistor between , and ground, it does not take a long time to charge the output terminal Q even when the power is turned on.

Therefore, the unstable state of the l transfer gate bare immediately after power is turned on can be eliminated, and stable operation of the logic circuit can be obtained.

In the above embodiment, the control gates of the PMOS transistor PI and the NMOS transistor N are connected to the power supply (2) as the high potential side. Although the case has been described in which it is connected to C, the case is not limited to this, and it may be connected to ground as the low potential side. however,
In this case, the charges injected into the floating gate FC may be positive charges, and the NMOS transistor N may be turned on and the PMOS transistor P+ may be turned off by programming.
The threshold voltage -VTF of the OS transistor P is set to a value near the ground voltage, and the threshold voltage (A) of the NMOS transistor N1 is set to a value below the ground voltage. By setting the threshold voltage to a value sufficiently higher than the ground voltage, and setting the threshold voltage of the NMO3I transistor N to a value higher than the ground voltage, the floating gate FG is set by programming.
By injecting negative charge into the transistors N+ and P+, transistors N+ and P+ may be turned off and on, respectively.

Further, in the above embodiment, the PMO3I-transistor P1 is connected to the power supply VCC side as the high potential side, and the NMO
Although the case has been described in which the S transistor N1 is connected to the ground side, which is the low potential side, these relationships can also be reversed.

〔Effect of the invention〕

As explained above, according to the programmable switch circuit of the present invention, a large through current does not flow between the high potential side and the low potential side, and a high load resistor is inserted between the high potential side and the low potential side. Since this is no longer necessary, the output terminal can be quickly charged even immediately after the power is turned on without increasing power consumption, and as a result, the unstable state of the switching means immediately after the power is turned on can be eliminated. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of changes in threshold voltage before and after writing in a PMOS transistor and an NMO3I-transistor, and FIG. 3 is a circuit diagram showing a conventional FIG. 2 is a circuit diagram illustrating the technology.

Claims (1)

[Claims] (1) The high potential side and the low potential side are connected via a floating gate type P-channel MOS transistor and a floating gate type N-channel MOS transistor connected in series, and the control gates of both transistors are set to a high level. A switch means connected to a potential side or a low potential side and further includes a switch means that is turned on and off according to a potential of a connection point between both the transistors, and a charge injection means that injects charge into the floating gates of both the transistors. A programmable switch circuit featuring: