JPH03121638A - Monitoring timer circuit - Google Patents

Abstract

PURPOSE:To decrease number of required gates by preparing an LSI terminal input number only for a code bit number equal to number of discrete monitoring time of a monitoring timer when monitor timer exclusive terminals are prepared for the LSI. CONSTITUTION:The circuit consists of a monitoring counter 6 starting and counting a clock pulse from the start point of time, stopping the count when a signal being a monitor object comes and reset thereby, a code register 5 set with a predetermined set time in a form of a code and latching the time, a decode circuit 11 receiving a code output from the code register 6, decoding it and outputting the result as an individual signal, and a comparator circuit comparing a count output of the counter 6 with an individual signal from the decode circuit 11 and outputting an overflow signal when they are coincident. Then the counter output is extracted from bit locations of the counter 6 corresponding to the 4 discrete monitor time desired to be set. Thus, the required gate number is less and the cost is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to data transmission and reception on a common bus when switching equipment, information processing equipment, etc. transmit and receive data (bus communication) via a common bus. The present invention relates to a monitoring timer circuit that contributes to confirming the normality of a bus protocol by monitoring whether the timer has arrived within a predetermined period of time.

[Conventional technology]

FIG. 2 is a conceptual diagram of bus communication.

In the same figure, each device A-N connected to the common bus BUS
Communication is performed between any pair of the two via the common bus BUS. Each device can adopt a transmitting operation mode as a transmitting side, and can also adopt a receiving operation mode as a receiving side. The common bus BUS communicates only with the device pair 1&l (in the example of the figure, communication from A to D) at the same time,
At other different times, communication is possible between any other pair of devices (eg, from D to C). This is bus communication.

Communication between devices on such a common bus (which may also be simply called a bus) is performed by exchanging a series of bus control signals between the transmitting side and the receiving side. For example, a "bus start signal" that instructs the start of signal transfer on the bus is sent from the transmitting side,
When data transfer is actually performed on the bus and the receiving side receives or accepts the data, the receiving side notifies the transmitting side that the data has been received by using an ``acknowledge (or also referred to as data transfer complete) signal.''

Such a bus control signal and data transfer procedure (how to use) is generally called a bus protocol.

FIG. 3 is a time chart showing an example of the relationship of signal exchange between the transmitting side and the receiving side in such a bus protocol.

In the figure, prior to data transfer, the sending side sends out a bus start signal and then sends out the data. When the receiving side receives data subsequent to receiving the bus start signal, it transmits an acknowledge signal indicating this to the transmitting side. On the transmitting side, after sending the bus start signal,
A monitoring timer circuit (not shown) is activated, and the receiving side monitors whether or not an acknowledge signal is sent within a predetermined time set in the timer, and if an acknowledge signal is not sent, the protocol It is determined that this is an abnormality and countermeasures are taken.

For this reason, the present invention relates to a monitoring timer circuit used in bus communication, etc., and such a monitoring timer circuit generally has a monitoring time value that can be variably set by initial setting. Bus control LS
It is realized as an internal circuit of I.

FIG. 4 is a circuit diagram showing an example of the configuration of a conventional monitoring timer circuit. This example is a configuration example of a monitoring timer circuit implemented using 32 bits within an LSI.

Although the LSI terminal to which the monitoring time value of the monitoring timer circuit in the LSI is input is serialized, for the sake of simplicity, the explanation will be made assuming that the input is from a parallel terminal.

It is shown in Figure 4, ■ is LSI, (2-0) ~ (2-3
1) is the monitoring time value input terminal of the monitoring timer, ■0 to 131
is its input signal, 3 is the first AND gate, (3-0)
~(3-31) is the output of the AND gate, 4 is the set input of the first AND gate, 5 is the holding register 32b (b means bit) for holding the monitoring time input value, (5 -1) is the output of the holding register 5, 6 is the addition counter of 32b, (6-1) is the output of 32b of counter 6, 7 is the comparison circuit of 32b, (7-1) is the comparison result output,
8 is the second AND gate, (8-1) is the monitoring start input,
(8-2) is the output of the second AND gate 8, and 9 is the reset input.

The monitoring time value is set using the LSI input terminals (2-0) to (2-31) for setting the monitoring time value in bits of the monitoring timer.
This is achieved by importing in binary value from . A two-selection type switch may be connected to the terminal to select pull-up (high level) or ground (low level) so that each terminal input has the required binary value, or It may also be realized so that it is connected to a bus signal line and input in the form of a bus data signal.

These inputs are set in the holding register 5 when the set input 4 of the first AND gate 3 becomes "1".
Although the operating clocks of the holding register 5, counter 6, and comparison circuit 7 are not shown in this figure, in reality, setting, count amplifier, and comparison are performed respectively in synchronization with the clocks.

On the other hand, the counter 6 indicates that the monitoring start input (8-1) is “Io
When the comparison result output (7-1) becomes "0° (that is, no match), the output of the second AND gate (8-2)
becomes 1 and starts counting up. The monitoring start input (8-1) is input when the signal to be actually monitored (e.g., bus control signal "pass start, etc.") satisfies the conditions (e.g., when the signal changes from "0" to "Io" and is sent. )
The comparison result output (7-1) becomes "1" when the output of the holding register 5 and the output (6-1) of the counter 6 match. °, and when there is a mismatch, it is assumed to be “0”.

While the count amplifier operation of the counter 6 (increase by 1 every clock) is performed, the holding register output (5-1) and the counter output (6-1) are output to the comparison circuit 7 at the clock cycle.
The comparison result is output as a comparison result output (7-1).

Therefore, when the comparison result becomes "1", the AND gate output (8-2) becomes 0', and the counter 6 stops counting up. That is, the counter 6 inputs the set time value held in the holding register 5. If the monitoring target signal arrives before the count ends, the counter 6 should stop counting at that point, so after the counter 6 finishes counting the set time value, the output (7 −
The fact that 1) becomes "l" means that the signal to be monitored has not arrived, resulting in a monitoring time overflow.

Note that the comparison result output (7-1) can also be used for other controls within the LSI. When a monitored signal arrives, the counter 6 assumes that the monitored signal satisfies the termination condition and starts monitoring. Since the starting force is set to 0°, the second AND gate output (8-2) becomes "0" and the counting stops. The counter 6 is cleared to "O" by a reset manual 9 after the monitoring operation is completed and before new monitoring is started.

As explained above, such a monitoring timer can realize any monitoring time according to the input value set in the holding register, but in order to make the monitoring time value of the monitoring timer variable, It is necessary to set the monitoring time value data equal to the bit length of . When incorporating into an actual system, connect a DIP switch, etc. to the end of the LSI terminal for setting value input, and select the input value for each terminal [pull-up (high level), ground (low level)] by operating the switch. If you do this, you can easily change the monitoring time value,
Furthermore, the contents of the holding register can be set autonomously by hardware when the power is turned on.

Please refer to FIG. 5, which shows an operation time chart for the above explanation.

In this example, the contents of the holding register are set by LSI terminal input, but the contents may be written via the original Hassle interface. However, in the latter case, it is necessary to heteronomously set the contents of the holding register from a CPU or the like connected to the same bus after the power is turned on.

[Problem to be solved by the invention]

The conventional monitoring timer circuit as described above has a large number of bits for setting the monitoring time, such as 32 bits, so it has the advantage of being able to set an arbitrarily variable value as the monitoring time, but it is difficult to configure the circuit. The problem is that the number of gates required increases and the cost also increases.

SUMMARY OF THE INVENTION An object of the present invention is to overcome the problems in the prior art and to provide a monitoring timer circuit that requires fewer gates and is inexpensive.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a monitoring timer that monitors whether a signal to be monitored arrives within a predetermined time from the start time and outputs an overflow signal to that effect if the signal does not arrive. The circuit includes a counter that starts counting clock pulses from the start point and stops counting and is reset when a signal to be monitored arrives, and a code register that sets and holds the predetermined set time in code format. and a decoding circuit that receives and decodes the code output from the code register and outputs it as an individual signal, and compares the count output of the counter with the individual signal from the decoding circuit, and if they match, outputs the overflow signal. a comparison circuit,
We have realized a monitoring timer circuit consisting of:

[Effect]

In the conventional technology, a monitoring time value having a number of bits equal to the bit length of the monitoring timer is set from an LSI manual terminal, but in this case, any binary value can be set within the range of the number of bits. However, there is generally no need for the monitoring time to be completely continuously variable. If you can set discrete values within a certain range, most requests can be met.

Therefore, in the present invention, we focused on this point and focused on n terminal input (n<
The bit length of the watchdog timer) is input as a code instead of a binary value, and this is decoded within the LSI and developed into 2n states, where one output bit is "1" and the other output bits are "O". Each of these decoded outputs is configured to be compared with the output of 2n arbitrary bit positions of the counter constituting the monitoring timer, and the counter (assuming an additive type ) is activated in synchronization with the start of monitoring of the monitored signal, performs a comparison every time it is counted up, and outputs the decoded output bit “
When it is detected that the bit output of the monitoring timer corresponding to 1' becomes Il+, it is determined that the monitoring time has overflowed, and the counter is stopped. Note that the counter stops counting at any time if the monitoring condition is canceled due to the arrival of a monitoring target signal or the like before the monitoring time overflows.

Normally, n=2 to 3 (4 to 8 states) is considered to be sufficient.

As a result, in the present invention, when an LSI is provided with a terminal dedicated to the watchdog timer, the number of inputs to the LSI terminal is only the number of code bits equal to the number of discrete watchdog time values of the watchdog timer. The decoding circuit and the comparison circuit with the counter output can also be small-scale, and the gate required is much smaller than the conventional method, which requires an input value holding register with the number of bits equal to the number of bits of the monitoring timer and a comparison circuit of the same size. The number can be reduced.

On the other hand, when the present invention is implemented by inputting setting values via an LSI bus interface, the number of required gates can be similarly reduced.

〔Example〕

An embodiment in which four monitoring time values can be selected according to the present invention will be described with reference to FIG.

In Figure 1, 1 is an LSI, (2-0) to (2-1)
is the LSI terminal input for inputting the monitoring time code of the monitoring timer, 10 and 11 are the input signals thereof, 3 is the first AND gate, (3-0) and (3-1) are the outputs of the AND gate,
4 is the set input of the first AND gate 3, 5 is the holding register of 2b, (5-0), (5-1) is the holding register 5
, 6 is a counter, (6-1) to (6-4) are outputs of predetermined different bit positions of counter 6, 9 is a reset input, 11 is a decoding circuit, (11-0
) to (11-3) are decode outputs, 2 is the third AND gate, (12-0) to (12-3) are each output of the third AND gate 12, 13 is an OR gate, (13-1 ) is the output of the OR gate.

The input signals IO and TI are 2-bit code signals, which are passed through the first AND gate 3 and output (3-0) from the gate when the set force 4 is at "1 degree."

(3-1) and is set in the holding register 5. The outputs (5-0) and (5-1) of the holding register 5 are supplied to the decoding circuit 11, and the four decoding circuit outputs (11
-0) to (11-3). The outputs are input to the third AND gates 12 in one-to-one correspondence with the outputs (6-1) to (6-4) of the counter 6, respectively. These AND gate outputs are input to the OR gate 13, and the OR gate output (13-1) becomes the input to the second AND gate 8, and the output can also be used for other controls within the LSI.

The functions of the holding register 5, counter 6, and second AND gate 8 are as already explained in the conventional circuit example shown in FIG.

The decode outputs (11-0) to (11-3) are associated with the code input pattern, and any one output is
°, and the other outputs are decoded to be 0°.The counter output should be drawn from the bit position of the counter 6 corresponding to the four discrete monitoring times you want to set.For example, 30 seconds, 1 second, 100 milliseconds, the bit positions corresponding to 1 millisecond. These times are easily calculated from the product of the operating clock period of counter 6 and the binary bit value of counter 6. However, the time values are not necessarily current. It does not exactly match the time value mentioned above, and there is little need for it to match.

For example, if the decode output (11-0) is "l" and the counter output (6-1) corresponds to the output of bit 28 of counter 6, then if the counter clock cycle is 100 nanoseconds, 28 bits are When the count-up reaches 1°, the monitoring time overflows, but the time is
2"X100 nanoseconds ns';2.68X10" nanoseconds-
26.8 seconds. At this time, the third AND gate outputs (121) to (12-3) become "0" because the decoding output is "0°," but the third AND gate output (12-3) becomes "0".
0) becomes "1°," and the output (13-1) of the OR gate also becomes "1", which serves to stop the counter 6.

As mentioned in the explanation of the prior art in FIG.
is separately controlled so that the monitoring start time becomes '0' when the monitoring end condition of the monitored signal is satisfied, and the counter 6 is counted up at the clock cycle. Further, the operation time chart is the same as that shown in FIG. 5 except that the decoded signal of the holding register 5 is the object of comparison.

From the above explanation, with the two-person code signal of IO, 11,
It is clear that four time monitoring values can be selected and determined from any fixed bit position of the counter.

It is clear from a comparison with FIG. 4 that this embodiment can also be set from the bus interface (only the input means is different).

In the embodiments of the present invention, the bus interface control LSI has been described, but the monitoring timer circuit according to the present invention
The signals to be monitored are not particularly limited, and the present invention can be applied to any kind of monitoring in which a monitoring start condition occurs at an arbitrary time and a monitoring end condition occurs at an arbitrary time after a certain period of time.

Further, as long as the input means is a code input and the conditions are satisfied, any method may be used.

〔Effect of the invention〕

As explained above, according to the monitoring timer circuit of the present invention,
Compared to the conventional variable monitoring time type monitoring timer, the number of gates necessary for configuring the initial setting means including the holding register and comparison circuit essential to the monitoring timer can be reduced to 115 or less.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a conceptual diagram of bus communication, and Fig. 3 is an example of the relationship of signal exchange between the sending side and the receiving side in the bus protocol. FIG. 4 is a circuit diagram showing a configuration example of a conventional monitoring timer circuit, and FIG. 5 is a time chart showing the operation of the monitoring timer circuit of FIG. 4. Explanation of symbols 1... LSI, (2-0) to (2-31)... Monitoring time value input terminal of monitoring timer, 3... AND gate,
5... Holding register, 6... Addition counter, 7...
・Comparison circuit, (8-1)...Monitoring start input, 10...
・Decode circuit, 12...OR gate

Claims (1)

[Claims] 1) In a monitoring timer circuit that monitors whether a signal to be monitored arrives within a predetermined time from a start point and outputs an overflow signal to that effect if the signal does not arrive. a counter that starts counting clock pulses from the start point and stops counting and is reset when a signal to be monitored arrives, and a code register that holds the predetermined set time set in a code format; a decoding circuit that receives and decodes the code output from the code register and outputs it as an individual signal; and a comparison circuit that compares the count output of the counter and the individual signal from the decoding circuit and outputs the overflow signal if they match. A monitoring timer circuit comprising: