JPH03120920A - Optical reception circuit - Google Patents

Optical reception circuit

Info

Publication number
JPH03120920A
JPH03120920A JP1257665A JP25766589A JPH03120920A JP H03120920 A JPH03120920 A JP H03120920A JP 1257665 A JP1257665 A JP 1257665A JP 25766589 A JP25766589 A JP 25766589A JP H03120920 A JPH03120920 A JP H03120920A
Authority
JP
Japan
Prior art keywords
voltage
circuit
signal
avalanche photodiode
bias voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1257665A
Other languages
Japanese (ja)
Inventor
Kenta Noda
健太 野田
Ichiro Ikushima
生島 一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1257665A priority Critical patent/JPH03120920A/en
Publication of JPH03120920A publication Critical patent/JPH03120920A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To prevent the band deterioration in an avalanche photodiode with simple constitution by providing a voltage holding circuit holding an output voltage of a voltage control circuit to be a prescribed value or over. CONSTITUTION:When an input level of an optical signal is increasing, a bias voltage gets lower, band deterioration takes place in a reception signal of an avalanche photodiode 1 but the reduction of a bias voltage to be a prescribed level or below is blocked by a voltage holding circuit 8. That is, a prescribed voltage signal resulting from dividing an output voltage of a high voltage generating circuit 7 with resistors 8b, 8c is obtained at a connection midpoint of the resistors 8b, 8c and even when a collector level of a transistor(TR) 6a in a voltage control circuit 6 is decreased, a level at a cathode side point (b) of diodes 8a, 8d (that is, a bias voltage) is not lowered than the divided voltage signal. Thus, a bias voltage of the avalanche photodiode 1 is not lowered than the voltage division signal resulting from dividing an output voltage of the high voltage generating circuit 7 with the resistors 8b, 8c and the band deterioration in the reception signal is blocked.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はアバランシェ2オドダイオードを用いた光信号
の受信回路に関する〇 〔従来の技術〕 光通信システムに適用されるアバランシェフォトダイオ
ードを用いた光信号の受信回路として、特開昭63−2
15126号公報に記載されているように、第2図に示
す如き回路が従来知られていた。この第2図において、
1はアバランシェフォトダイオードを示し、このアバラ
ンシェフォトダイオード1の出力信号を前置増幅回路2
及び可変利得増幅回路5を介してピーク値検出回路4に
供給し、このピーク値検出回路4の検出信号を誤差増幅
回路5の一方の入力端子に供給する・この場合、可変利
得増幅回路3は、前置増幅回路2からの(2号を等化増
幅すると共に、出力電圧が一定となるように利得が変化
するものである。そして、基準電圧信号入力端子5aに
得られる基準電圧信号を、誤差増幅回路5の他方の入力
端子に供給する・そして、誤差増幅回路5が出力する誤
差信号を、’l圧制御回路6に供給するにの電圧制御回
路6には、高圧発生回路7から高圧信号が供給され、こ
の高圧信号の電圧値を電圧制御回路6で誤差信号に基づ
いて制御し、制御された高圧信号をアバランシェフォト
ダイオード1にバイアス電圧として供給している。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an optical signal receiving circuit using an avalanche 2-odd diode. As a signal receiving circuit, JP-A-63-2
As described in Japanese Patent No. 15126, a circuit as shown in FIG. 2 has been known in the past. In this figure 2,
1 indicates an avalanche photodiode, and the output signal of this avalanche photodiode 1 is sent to a preamplifier circuit 2.
and is supplied to the peak value detection circuit 4 via the variable gain amplifier circuit 5, and the detection signal of this peak value detection circuit 4 is supplied to one input terminal of the error amplifier circuit 5. In this case, the variable gain amplifier circuit 3 , No. 2 from the preamplifier circuit 2 is equalized and amplified, and the gain is changed so that the output voltage is constant.Then, the reference voltage signal obtained at the reference voltage signal input terminal 5a is The voltage control circuit 6 is supplied with the high voltage from the high voltage generation circuit 7 to supply the error signal output from the error amplification circuit 5 to the other input terminal of the error amplification circuit 5 and to the voltage control circuit 6. A signal is supplied, the voltage value of this high voltage signal is controlled by a voltage control circuit 6 based on an error signal, and the controlled high voltage signal is supplied to the avalanche photodiode 1 as a bias voltage.

〔発明が解決しようとするvjA題〕[vjA problem that the invention attempts to solve]

この第2図の回路構成では、アバランシェフォトダイオ
ード1への光信号の入力レベルが高いときには、電圧制
御回路6がアバランシェフォトダイオード1のバイアス
電圧を下げるように働く。
In the circuit configuration shown in FIG. 2, when the input level of the optical signal to the avalanche photodiode 1 is high, the voltage control circuit 6 works to lower the bias voltage of the avalanche photodiode 1.

このようにバイアス電圧が低下すると、アバランシェフ
ォトダイオード1の出力信号に帯域劣化を生じる問題が
あった。この帯域劣化を防ぐためKは、例えば誤差増幅
回路の出力信号と基準電圧信号とを比較し、比較結果に
応じて高圧発生回路を制御する比較判定回路を設けるこ
とが提案されているが、このように比較判定回路を設け
ると回路構成が複雑化する問題があった。
When the bias voltage decreases in this way, there is a problem in that the output signal of the avalanche photodiode 1 suffers from band deterioration. In order to prevent this band deterioration, it has been proposed that K be provided with a comparison/judgment circuit that, for example, compares the output signal of the error amplifier circuit with a reference voltage signal and controls the high voltage generation circuit according to the comparison result. When a comparison/determination circuit is provided in this way, there is a problem in that the circuit configuration becomes complicated.

本発明の目的は、簡単な構成でアバランシェフォトダイ
オードの帯域劣化を防止することにある。
An object of the present invention is to prevent band deterioration of an avalanche photodiode with a simple configuration.

〔課題を解決するための手段〕 上記目的を達成するために、本発明の光受信回路は、バ
イアス電圧を制御する電圧制御回路の出力電圧を一定以
上に保持する電圧保持回路を設けたものである。
[Means for Solving the Problems] In order to achieve the above object, the optical receiving circuit of the present invention is provided with a voltage holding circuit that holds the output voltage of the voltage control circuit that controls the bias voltage above a certain level. be.

〔作用〕[Effect]

この構成によると、アバランシェフォトダイオードへの
光信号の入力レベルが高いときに、電圧制御回路が出力
電圧を低下させても、電圧保持回路によりバイアスミ圧
が一定値以上に保持され、アバランシェフォトダイオー
ドの帯域劣化が阻止される。
According to this configuration, even if the voltage control circuit lowers the output voltage when the input level of the optical signal to the avalanche photodiode is high, the voltage holding circuit maintains the bias voltage above a certain value, and the avalanche photodiode Bandwidth degradation is prevented.

〔実施例〕〔Example〕

以下、本発明の光受信回路の一実施例を、第1図を参照
して説明する。この第1図において、第2図に対応する
部分には同一符号を付し、その詳細説明は省略する。
An embodiment of the optical receiving circuit of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

本例においては、前置増幅回路2及び可変利得回路3を
介したアバランシェフォトダイオード1の出力信号を、
ピーク値検出回路4でピーク値検出する。そして、誤差
増幅回路5で基準電圧信号入力端子5aK得られる基準
電圧とピーク値検出出力との誤差検出をし、誤差信号を
電圧制御回路6に供給する。この場合、誤差信号を、電
圧制御回路6を構成するNPN型トランジスタ6aのペ
−−X IIC供給供給。そして、このトランジスタ6
aのエミッタを、抵抗器6bを介して接地する◎また、
高圧発生回路7の出力電圧を、抵抗器6cを介してトラ
ンジスタ6sLのコレクタに供給する。
In this example, the output signal of the avalanche photodiode 1 via the preamplifier circuit 2 and variable gain circuit 3 is
A peak value detection circuit 4 detects the peak value. Then, the error amplifier circuit 5 detects an error between the reference voltage obtained from the reference voltage signal input terminal 5aK and the peak value detection output, and supplies the error signal to the voltage control circuit 6. In this case, the error signal is supplied to the P-X IIC of the NPN transistor 6a constituting the voltage control circuit 6. And this transistor 6
The emitter of a is grounded via the resistor 6b. Also,
The output voltage of the high voltage generation circuit 7 is supplied to the collector of the transistor 6sL via the resistor 6c.

そして本例においては、電圧保持回路8を設けるようk
する・即ち、トランジスタ6 a O2レクタを、電圧
保持回路8を構成するダイオード8aのアノードに接続
し、このダイオード8aのカソードをアバランシェフォ
トダイオード1に接続する・また、高圧発生回路7の出
力側を、電圧保持回路8を構成する抵抗器8b及び8c
の直列回路を介して接地し、さらに両抵抗器8b及び8
cの接続中点をダイオード8dのアノードに接続し。
In this example, the voltage holding circuit 8 is provided.
In other words, the transistor 6a O2 collector is connected to the anode of the diode 8a that constitutes the voltage holding circuit 8, and the cathode of this diode 8a is connected to the avalanche photodiode 1.In addition, the output side of the high voltage generation circuit 7 is , resistors 8b and 8c forming the voltage holding circuit 8
grounded through a series circuit of 8b and 8b.
Connect the middle point of connection c to the anode of diode 8d.

このダイオード8dのカソードをアバランシェフォトダ
イオード1に接続する。
The cathode of this diode 8d is connected to the avalanche photodiode 1.

この構成の受信回路の動作について以下説明すると、例
えばアラパンシェアオドダイオード1に高いレベルの光
信号が入力したとする@このときには、ピーク値検出回
路4の出力電圧が上が)、誤差増幅回路5の誤差出力電
圧も上昇する。この誤差出力電圧の上昇により、電圧制
御回路6内のトランジスタ6aにペース電流が流れ、ア
バランシェフォトダイオード1のバイアス電圧であるト
ランジスタ6aのコレクタ電位が低下する。このコレク
タ電位(即ちバイアス電圧)の低下によ)、アバランシ
ェフォトダイオード1の増倍率が下がシ、可変利得増幅
回路5の出力が一定に保たれる。
The operation of the receiving circuit with this configuration will be explained below. For example, if a high-level optical signal is input to the Alapan shear odd diode 1 (at this time, the output voltage of the peak value detection circuit 4 increases), the error amplifier circuit The error output voltage of No. 5 also increases. Due to this increase in the error output voltage, a pace current flows through the transistor 6a in the voltage control circuit 6, and the collector potential of the transistor 6a, which is the bias voltage of the avalanche photodiode 1, decreases. Due to this decrease in the collector potential (ie, bias voltage), the multiplication factor of the avalanche photodiode 1 decreases, and the output of the variable gain amplifier circuit 5 is kept constant.

このようにして光信号の入力レベルが高くなりて行<ト
、バイアス電圧が低くなって行き、アバランシェフォト
ダイオード1の受am号た帯域劣化が発生するが1本例
にシいては電圧保持回路8により、バイアス電圧が一定
値以下に低下するのが阻止される・即ち、抵抗器8′b
及び8cの接続中点a点には、高圧発生回路7の出力電
圧を抵抗器8b及び8aで分圧した一定の電圧信号が得
られ、トランジスタ6のコレクタ電位が低下しても、ダ
イオード8a及び8dのカソード側)点の電位(即ちバ
イアス電圧)がこの分圧信号よ)も低下することはない
・従って、アバランシェフォトダイオード1のバイアス
電圧は、抵抗器8b及び8Cで分圧した分圧信号よシ低
下することはなく、受信信号の帯域劣化が阻止される・
表お、ダイオード8aは、光入力レベルが高いときtc
、分圧信号がトランジスタ6aのコレクタ側に流れるの
を阻止するために設けたもので、またダイオード8dは
、光入力レベルが低いときにトランジスタ6aのコレク
タ電流が抵抗器8c@に流れるのを阻止するために設け
たものである。
In this way, as the input level of the optical signal increases, the bias voltage decreases, causing band deterioration of the avalanche photodiode 1. In this example, the voltage holding circuit 8 prevents the bias voltage from dropping below a certain value, i.e. resistor 8'b
A constant voltage signal obtained by dividing the output voltage of the high voltage generation circuit 7 by the resistors 8b and 8a is obtained at the connection midpoint a of the high voltage generating circuit 7 and 8c. The potential (that is, the bias voltage) at the point on the cathode side of 8d (that is, the bias voltage) also does not drop due to this divided voltage signal. Therefore, the bias voltage of the avalanche photodiode 1 is equal to the divided voltage signal divided by the resistors 8b and 8C. The band quality of the received signal is not degraded, and the band deterioration of the received signal is prevented.
In the table, when the optical input level is high, the diode 8a
, is provided to prevent the divided voltage signal from flowing to the collector side of the transistor 6a, and the diode 8d prevents the collector current of the transistor 6a from flowing to the resistor 8c@ when the optical input level is low. It was established for the purpose of

〔発明の効果〕〔Effect of the invention〕

本発明の光受信回路によると、一定電圧の信号を出力す
る電圧保持回路を設けただけの簡単な回路構成で、アバ
ランシェフォトダイオードのバイアス電圧低下による受
信信号の帯域劣化を阻止することができ、受信回路のダ
イナミックレンジを広げることができる。
According to the optical receiving circuit of the present invention, with a simple circuit configuration that only includes a voltage holding circuit that outputs a constant voltage signal, it is possible to prevent band deterioration of the received signal due to a drop in the bias voltage of the avalanche photodiode. The dynamic range of the receiving circuit can be expanded.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の光受信回路の一実施例を示す構成図、
第2図は従来の光受信回路の一例を示す構成図である◎
FIG. 1 is a configuration diagram showing an embodiment of the optical receiving circuit of the present invention;
Figure 2 is a configuration diagram showing an example of a conventional optical receiver circuit◎

Claims (1)

【特許請求の範囲】[Claims] 1、光入力信号を電気信号に変換するアバランシェフォ
トダイオードと、該アバランシエフォトダイオードから
の電流信号を電圧信号に変換する等化増幅回路と、該等
化増幅回路の出力レベルを検出する検出回路と、前記ア
バランシェフォトダイオードにバイアス電圧を供給する
高圧発生回路と、前記検出回路の検出信号により前記高
圧発生回路が発生させるバイアス電圧を制御する電圧制
御回路とを備える光受信回路において、前記電圧制御回
路の出力電圧を一定以上に保持する電圧保持回路を設け
たことを特徴とする光受信回路。
1. An avalanche photodiode that converts an optical input signal into an electrical signal, an equalization amplifier circuit that converts a current signal from the avalanche photodiode into a voltage signal, and a detection circuit that detects the output level of the equalization amplifier circuit. and a high voltage generation circuit that supplies a bias voltage to the avalanche photodiode, and a voltage control circuit that controls the bias voltage generated by the high voltage generation circuit based on a detection signal of the detection circuit, wherein the voltage control circuit includes: An optical receiving circuit characterized by being provided with a voltage holding circuit that holds the output voltage of the circuit above a certain level.
JP1257665A 1989-10-04 1989-10-04 Optical reception circuit Pending JPH03120920A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1257665A JPH03120920A (en) 1989-10-04 1989-10-04 Optical reception circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1257665A JPH03120920A (en) 1989-10-04 1989-10-04 Optical reception circuit

Publications (1)

Publication Number Publication Date
JPH03120920A true JPH03120920A (en) 1991-05-23

Family

ID=17309403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1257665A Pending JPH03120920A (en) 1989-10-04 1989-10-04 Optical reception circuit

Country Status (1)

Country Link
JP (1) JPH03120920A (en)

Similar Documents

Publication Publication Date Title
JP2503837B2 (en) Digital optical receiver circuit and preamplifier circuit in digital optical receiver circuit
US5539779A (en) Automatic offset control circuit for digital receiver
US5038055A (en) Peak level detecting device and method
US6072366A (en) Receiver capable of outputting a high quality signal without regard to an input signal level
US4564818A (en) Transimpedance amplifier having an improved gain/bandwidth product
US5844445A (en) Feedback type pre-amplifier
US7755433B2 (en) Preamplifier and optical receiving device including the same
AU672839B2 (en) Circuit for converting unipolar input to bipolar output
US4446443A (en) Amplifier having reduced power dissipation and improved slew rate
US4492926A (en) Amplitude modulation detector
US4983905A (en) Constant voltage source circuit
KR100327173B1 (en) Voltage Control Attenuator for Speakerphone
US4137552A (en) Automatic beam current limiter with independently determined threshold level and dynamic control range
US4607234A (en) Gain-controlled amplifier arrangement
JPS61109376A (en) Clamp circuit
US5295161A (en) Fiber optic amplifier with active elements feedback circuit
US6891405B2 (en) Variable gain amplifier
US20060028279A1 (en) Automatic gain control feedback amplifier
EP0498197B1 (en) Circuit for DC control of a compressor
JPH03120920A (en) Optical reception circuit
US5157347A (en) Switching bridge amplifier
US4812908A (en) Automatic gain control circuit having a control loop including a current threshold circuit
US20240283419A1 (en) Transimpedance gain control
JP2513435B2 (en) Optical receiver circuit
JP2000349571A (en) Preamplifier circuit