JPH03117963U - - Google Patents

Info

Publication number
JPH03117963U
JPH03117963U JP2696390U JP2696390U JPH03117963U JP H03117963 U JPH03117963 U JP H03117963U JP 2696390 U JP2696390 U JP 2696390U JP 2696390 U JP2696390 U JP 2696390U JP H03117963 U JPH03117963 U JP H03117963U
Authority
JP
Japan
Prior art keywords
status signal
logic circuit
signal
2mpcm
receiving end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2696390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2696390U priority Critical patent/JPH03117963U/ja
Publication of JPH03117963U publication Critical patent/JPH03117963U/ja
Pending legal-status Critical Current

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  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Interface Circuits In Exchanges (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは本考案の実施例のブロツク図で
ある。 1……中継局、2……PCM端局、3……信号
変換回路、4……リレーコイル(RL)、5……
オアゲート、S1〜S3……接点。
1a and 1b are block diagrams of an embodiment of the present invention. 1...Relay station, 2...PCM terminal station, 3...Signal conversion circuit, 4...Relay coil (RL), 5...
OR gate, S1-S3...contact.

Claims (1)

【実用新案登録請求の範囲】 1 2MPCM端局装置の2つのステータス信号
送信端と変換機の1つのステータス信号受信端と
の間に接続され、2つの前記ステータス信号送信
端から送信される両信号を論理演算処理して発生
した1つの信号を前記ステータス信号受信端へ与
える論理回路を備えている2MPCM端局装置用
信号変換回路。 2 前記論理回路は、前記両信号の一方と他方の
否定との論理和信号を発生する請求項1記載の2
MPCM端局装置用信号変換回路。
[Claims for Utility Model Registration] 1. Both signals connected between two status signal transmitting ends of a 2MPCM terminal device and one status signal receiving end of a converter, and transmitted from the two status signal transmitting ends. A signal conversion circuit for a 2MPCM terminal device, comprising a logic circuit for applying a signal generated by processing a logical operation to the status signal receiving end. 2. The logic circuit according to claim 1, wherein the logic circuit generates a logical sum signal of one of the two signals and the negation of the other.
Signal conversion circuit for MPCM terminal equipment.
JP2696390U 1990-03-16 1990-03-16 Pending JPH03117963U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2696390U JPH03117963U (en) 1990-03-16 1990-03-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2696390U JPH03117963U (en) 1990-03-16 1990-03-16

Publications (1)

Publication Number Publication Date
JPH03117963U true JPH03117963U (en) 1991-12-05

Family

ID=31529838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2696390U Pending JPH03117963U (en) 1990-03-16 1990-03-16

Country Status (1)

Country Link
JP (1) JPH03117963U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60186163A (en) * 1984-03-05 1985-09-21 Fujitsu Ltd Signal converting circuit
JPS6325549A (en) * 1986-07-17 1988-02-03 Daicel Chem Ind Ltd Analysis of alkali metallic salt of bisphenol
JPS6325549U (en) * 1986-07-31 1988-02-19

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60186163A (en) * 1984-03-05 1985-09-21 Fujitsu Ltd Signal converting circuit
JPS6325549A (en) * 1986-07-17 1988-02-03 Daicel Chem Ind Ltd Analysis of alkali metallic salt of bisphenol
JPS6325549U (en) * 1986-07-31 1988-02-19

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