JPH03117216A - A/d converter - Google Patents

A/d converter

Info

Publication number
JPH03117216A
JPH03117216A JP25589689A JP25589689A JPH03117216A JP H03117216 A JPH03117216 A JP H03117216A JP 25589689 A JP25589689 A JP 25589689A JP 25589689 A JP25589689 A JP 25589689A JP H03117216 A JPH03117216 A JP H03117216A
Authority
JP
Japan
Prior art keywords
signal
converter
conversion
msb
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25589689A
Other languages
Japanese (ja)
Inventor
Masakatsu Kinoshita
雅勝 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba Audio Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Audio Video Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP25589689A priority Critical patent/JPH03117216A/en
Publication of JPH03117216A publication Critical patent/JPH03117216A/en
Pending legal-status Critical Current

Links

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To improve the characteristic after conversion even when no analog signal input exists by generating a signal with a prescribed amplitude and a frequency at the outside of the band of A/D conversion by an A/D converter means and inputting the signal to the A/D converter means. CONSTITUTION:When an analog signal is inputted to an A/D converter 1 and the signal has a large positive DC offset, an MSB data outputted from an MSB extraction circuit 2 takes a negatively consecutive prescribed value. Then MSB data pass through an integration circuit 3 and is inputted to the converter 1 to cancel the DC offset. When no analog signal is inputted to the converter 1 and the DC offset reaches a small value, then the MSB data from the circuit 2 is a signal having a frequency of 48kHz by a signal generated from a signal generating circuit 4. Since the signal is sufficiently attenuated by the circuit 3 and eliminated by a digital filter 8, then the signal is not included in an output signal. Thus, even when no analog signal is inputted, the characteristic after conversion is improved.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) この発明は、DAT等のディジタルオーディオ装置等に
用いられるA/D変換装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an A/D conversion device used in a digital audio device such as a DAT.

(従来の技術) A/D変換器によりディジタル信号に変換されるアナロ
グ信号にその前段に配置される入力バッファ等によるD
Cオフセットが含まれていない場合であっても、変換に
係る各パラメータの誤差等により変換後のディジタル信
号にDCオフセットが含まれる。
(Prior art) An analog signal that is converted into a digital signal by an A/D converter is processed by an input buffer or the like placed before it.
Even if a C offset is not included, a DC offset is included in the converted digital signal due to errors in each parameter related to the conversion.

このため、従来から例えばMSBサーボによりこのよう
なりCオフセットを除去している。
For this reason, conventionally, for example, MSB servo is used to remove such a C offset.

MSBサーボとは、第3図(a)に示すように、2−S
コンブリメントのデータのMSBが信号の正負を表しか
つ音楽信号等のアナログ信号には本来的にD/C成分が
含まれていないことから、第3図(b)に示すように、
A/D変換器により変換されたディジタル信号からMS
Bデータを抽出して積分する。そして、この積分値が”
1(正)”か“0(負)”の一方に片寄らずに中間の値
をとるよう、この積分値をA/D変換器により変換され
るアナログ信号に帰還する。
The MSB servo is a 2-S servo, as shown in Figure 3(a).
The MSB of conbriment data represents the positive or negative of the signal, and since analog signals such as music signals inherently do not contain D/C components, as shown in FIG. 3(b),
MS from the digital signal converted by the A/D converter
Extract and integrate B data. And this integral value is ”
This integrated value is fed back to the analog signal converted by the A/D converter so that it takes an intermediate value without being biased toward either "1 (positive)" or "0 (negative)".

ところが、上記A/D変換器にアナログ信号が入力され
ていない場合、第4図(a)に示すような入力側に残留
するノイズやこのA/D変換器自体が発生するノイズ等
により、第4図(b)に示すように、MSBデータがこ
れらノイズに応じた内容となる。即ち、MSBデータを
抽出するための回路が、広いスペクトルを持つノイズア
ンプとなる。そして、このようなMSBデータがA/D
変換器の入力側に回り込み、A/D変換器のS/N比を
劣化させるという問題を生じる。
However, if no analog signal is input to the A/D converter, noise remaining on the input side as shown in Figure 4(a) or noise generated by the A/D converter itself may cause the As shown in FIG. 4(b), the MSB data has contents corresponding to these noises. That is, the circuit for extracting MSB data becomes a noise amplifier with a wide spectrum. Then, such MSB data is sent to the A/D
A problem arises in that the signal goes around to the input side of the converter and deteriorates the S/N ratio of the A/D converter.

(発明が解決しようとする課題) このように従来のMSBサーボによりDCオフセットを
除去する手段を備えたA/D変換装置では、A/D変換
器にアナログ信号が入力されていない場合、入力側に残
留するノイズやこのA/D変換器自体が発生するノイズ
等により、MSBデータがこれらノイズに応じた内容と
なって、A/D変換器の入力端に回り込み、A/D変換
器のS/N比を劣化させるという問題を生じる。
(Problems to be Solved by the Invention) As described above, in an A/D converter equipped with a means for removing DC offset using the conventional MSB servo, when an analog signal is not input to the A/D converter, the input side Due to the noise remaining in the A/D converter and the noise generated by the A/D converter itself, the MSB data becomes a content corresponding to these noises, wraps around to the input terminal of the A/D converter, and the S of the A/D converter This causes a problem of deteriorating the /N ratio.

そこで、この発明は、アナログ信号の入力のない場合で
あっても変換後の特性が良好なA/D変換装置を提供す
ることを目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an A/D converter with good characteristics after conversion even when no analog signal is input.

[発明の構成] (課題を解決するための手段) この発明は、入力されたアナログ信号をディジタル信号
に変換するA/D変換手段と、このA/D変換手段によ
り変換されたディジタル信号からMSBデータを抽出す
るMSB抽出手段と、このMSB抽出手段により抽出さ
れたMSBデータを積分し、この積分結果を前記A/D
変換手段の入力側に帰還する積分手段と、前記A/D変
換手段によるA/D変換の帯域外の周波数でかつ所定の
振幅の信号を発生し、この信号を前記A/D変換手段の
入力側に入力する信号発生手段とを具備するものである
[Structure of the Invention] (Means for Solving the Problems) The present invention includes an A/D conversion means for converting an input analog signal into a digital signal, and an MSB from the digital signal converted by the A/D conversion means. MSB extracting means for extracting data, integrating the MSB data extracted by the MSB extracting means, and transmitting the integration result to the A/D
an integrating means which is fed back to the input side of the converting means, and a signal having a frequency outside the band of A/D conversion by the A/D converting means and having a predetermined amplitude is generated, and this signal is input to the input side of the A/D converting means. and a signal generating means input to the side.

(作 用) この発明では、A/D変換手段によるA/D変換の帯域
外の周波数でかつ所定の振幅の信号を発生し、この信号
をA/D変換手段の入力側に入力しているので、アナロ
グ信号の入力のない場合であっても変換後の特性が良好
なものとなる。
(Function) In this invention, a signal having a frequency outside the A/D conversion band and a predetermined amplitude is generated by the A/D conversion means, and this signal is input to the input side of the A/D conversion means. Therefore, even when no analog signal is input, the characteristics after conversion are good.

(実施例) 次に、この発明の一実施例を説明する。(Example) Next, one embodiment of the present invention will be described.

第1図はこの実施例のA/D変換装置の構成を示す図で
ある。
FIG. 1 is a diagram showing the configuration of an A/D converter according to this embodiment.

同図において、1は入力されたアナログ信号を98Kl
lzの変換レートでディジタル信号に変換するA/D変
換器、2はA/D変換器1により変換されたディジタル
信号からMSBデータを抽出するMSB抽出回路である
In the same figure, 1 converts the input analog signal to 98Kl.
An A/D converter 2 converts the digital signal into a digital signal at a conversion rate of 1z, and 2 is an MSB extraction circuit that extracts MSB data from the digital signal converted by the A/D converter 1.

また、3はMSB抽出回路2により抽出されたMSBデ
ータを積分する積分回路、4はA/D変換器1によるA
/D変換の帯域外の周波数例えば48KHzでかつ所定
の振幅例えば1mV   の方形p″″p 波の信号を発生する信号発生回路である。この信号発生
回路4は、上記信号を発生するため、信号発生源5と−
60〜−80dB程度のアッテネータ6とを備える。
Further, 3 is an integration circuit that integrates the MSB data extracted by the MSB extraction circuit 2, and 4 is an A/D converter 1.
This is a signal generating circuit that generates a square p''p wave signal at a frequency outside the /D conversion band, for example, 48 KHz and a predetermined amplitude, for example, 1 mV. This signal generation circuit 4 is connected to a signal generation source 5 in order to generate the above-mentioned signal.
An attenuator 6 of about 60 to -80 dB is provided.

そして、7は積分回路3による積分結果及び信号発生回
路4からの信号をA/D変換器1の入力側に重畳する加
算器、8はA/D変換器1により変換されたディジタル
信号から例えば20Kllz以上の信号を除去するディ
ジタルフィルタである。
7 is an adder that superimposes the integration result by the integrating circuit 3 and the signal from the signal generating circuit 4 on the input side of the A/D converter 1; This is a digital filter that removes signals of 20 Kllz or more.

次に、このように構成されたA/D変換装置の動作を第
2図に基づき説明する。
Next, the operation of the A/D converter configured as described above will be explained based on FIG. 2.

第2図(a)■に示すように、A/D変換器1にアナロ
グ信号が入力されていて、その信号に大きな正のDCオ
フセットがあれば、MSB抽出回路2から出力されるM
SBデータは、第2図(b)■に示すように、負側で連
続する一定の値をとる。
As shown in FIG. 2(a), if an analog signal is input to the A/D converter 1 and the signal has a large positive DC offset, the MSB extraction circuit 2 outputs an
As shown in FIG. 2(b), the SB data takes a continuous constant value on the negative side.

そして、このMSBデータは、積分回路3を通りA/D
変換器1の入力側に入力され、上記DCオフセットをキ
ャンセルするよう働く。尚、アナログ信号に大きな負の
DCオフセットがある場合も(第2図(a)■)、同様
である(第2図(b)■)。
Then, this MSB data passes through the integrating circuit 3 and is sent to the A/D
It is input to the input side of the converter 1 and serves to cancel the above DC offset. Incidentally, the same applies when the analog signal has a large negative DC offset (Fig. 2(a) -) (Fig. 2(b) -).

次に、例えば第2図(a)■に示すように、A/D変換
器1にアナログ信号が入力されなくなり、DCオフセッ
トが微小(例えば500μV程度以下)になると、MS
B抽出回路2から出力されるMSBデータは、信号発生
回路4から発生される信号により、第2図(b)■に示
すように、48Kllzの周波数の信号となる。
Next, as shown in FIG. 2(a), for example, when the analog signal is no longer input to the A/D converter 1 and the DC offset becomes minute (for example, about 500 μV or less), the MS
The MSB data outputted from the B extraction circuit 2 becomes a signal with a frequency of 48 Kllz, as shown in FIG.

この周波数の信号は、積分回路3により充分アッテネー
トすることができかつディジタルフィルタ8により除去
することができるので、出力信号中には含まれない。
Since the signal at this frequency can be sufficiently attenuated by the integrating circuit 3 and removed by the digital filter 8, it is not included in the output signal.

従って、この実施例のA/D変換装置によれば、アナロ
グ信号の入力のない場合であっても変換後の特性は良好
なものとなる。
Therefore, according to the A/D converter of this embodiment, the characteristics after conversion are good even when no analog signal is input.

[発明の効果] 以上説明したように、この発明によれば、A/D変換手
段によるA/D変換の帯域外の周波数でかつ所定の振幅
の信号を発生し、この信号をA/D変換手段の入力側に
入力しているので、アナログ信号の入力のない場合であ
っても変換後の特性が良好なものとなる。
[Effects of the Invention] As explained above, according to the present invention, a signal having a frequency outside the A/D conversion band and a predetermined amplitude is generated by the A/D conversion means, and this signal is converted into an A/D conversion signal. Since it is input to the input side of the means, the characteristics after conversion are good even when no analog signal is input.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例に係るA/D変換装置の構
成を示す図、第2図はこの装置の動作を説明するための
図、第3図及び第4図従来例を説明するための図である
。 1・・・A/D変換器、2・・・MSB抽出回路、3・
・積分回路、4・・・信号発生口、5・・・信号発生源
、6・・・アッテネータ、7・・・加算器、8・・・デ
ィジタルフィルタ。
FIG. 1 is a diagram showing the configuration of an A/D conversion device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of this device, and FIGS. 3 and 4 are diagrams for explaining a conventional example. This is a diagram for 1... A/D converter, 2... MSB extraction circuit, 3...
・Integrator circuit, 4... Signal generation port, 5... Signal generation source, 6... Attenuator, 7... Adder, 8... Digital filter.

Claims (1)

【特許請求の範囲】 入力されたアナログ信号をディジタル信号に変換するA
/D変換手段と、 このA/D変換手段により変換されたディジタル信号か
らMSBデータを抽出するMSB抽出手段と、 このMSB抽出手段により抽出されたMSBデータを積
分し、この積分結果を前記A/D変換手段の入力側に帰
還する積分手段と、 前記A/D変換手段によるA/D変換の帯域外の周波数
でかつ所定の振幅の信号を発生し、この信号を前記A/
D変換手段の入力側に入力する信号発生手段と を具備することを特徴とするA/D変換装置。
[Claims] A for converting an input analog signal into a digital signal
MSB extracting means extracting MSB data from the digital signal converted by the A/D converting means; integrating the MSB data extracted by the MSB extracting means; an integrating means that feeds back to the input side of the D converting means; and generating a signal having a frequency outside the band of A/D conversion by the A/D converting means and having a predetermined amplitude, and transmitting this signal to the A/D converting means.
An A/D conversion device comprising: signal generation means input to the input side of the D conversion means.
JP25589689A 1989-09-29 1989-09-29 A/d converter Pending JPH03117216A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25589689A JPH03117216A (en) 1989-09-29 1989-09-29 A/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25589689A JPH03117216A (en) 1989-09-29 1989-09-29 A/d converter

Publications (1)

Publication Number Publication Date
JPH03117216A true JPH03117216A (en) 1991-05-20

Family

ID=17285075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25589689A Pending JPH03117216A (en) 1989-09-29 1989-09-29 A/d converter

Country Status (1)

Country Link
JP (1) JPH03117216A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07177187A (en) * 1993-12-21 1995-07-14 Nec Corp Demodulator
US8992756B2 (en) 2006-11-06 2015-03-31 C. Uyemura & Co., Ltd. Direct plating method and solution for palladium conductor layer formation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07177187A (en) * 1993-12-21 1995-07-14 Nec Corp Demodulator
US8992756B2 (en) 2006-11-06 2015-03-31 C. Uyemura & Co., Ltd. Direct plating method and solution for palladium conductor layer formation

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