JPH03116357A - Parallel processing system - Google Patents

Abstract

PURPOSE:To efficiently perform the information processing which requires communication processing of a mesh or torus pattern by mapping a model of the mesh or torus pattern on respective processors of a parallel computer. CONSTITUTION:With respect to a mesh pattern 3 and a torus pattern 8 having nXn nodes, n processors 1 ((n) is the square root of the number of nodes) and a universal communication coupling network 2 are used to generate n/2 loops or X-shaped patterns including 2n nodes without overlapping. Every two processors are selected from n processors without overlapping and are assigned to n/2 loops or X-shaped patterns, and two assigned processors are alternately assigned to successive nodes in each loop or X-shaped pattern. Thus, the informa tion processing requiring the communication processing of the mesh or torus pattern is efficiently performed.

Description

[Detailed Description of the Invention] [Summary] Parallel processing method on a parallel computer for information processing that requires mesh or torus pattern communication processing On a parallel computer equipped with a connection network capable of processing all-to-all communication, The purpose of this invention is to provide a method for efficiently performing information processing that requires mesh or torus pattern communication processing.

For mesh patterns and torus patterns with nxn nodes, use n processors of the square root of the number of nodes and an all-to-all communication network.

Create n/2 loops or X-shaped patterns each containing 2n nodes without overlap for each mesh pattern and torus pattern, and divide these n/2
For each loop or X-shaped pattern, two processors selected from n processors without duplication are assigned, and in each loop or X-shaped pattern, the two processors assigned 2 are sequentially assigned. It was configured to be assigned alternately to nodes.

(Industrial Application Field) The present invention relates to a parallel processing method on a parallel computer for information processing that requires mesh or torus pattern communication processing.

[Prior Art] In simulations of physical phenomena, such as fluid analysis, models with mesh or torus patterns often appear. Since the processing of such problems often requires a large amount of computational processing, there is a desire for faster processing using parallel computers.

Conventionally, systems in which processors are connected in a mesh or torus topology have been proposed as parallel computers for processing problems having mesh pattern or torus pattern models.

Figures 7(a) and (bH) show examples of mesh-like and torus-like connected networks each having 8x80 nodes. Each node alternates between computation and communication with neighboring nodes. repeat.

FIG. 8(a) is an example of a real problem of fluid analysis, and each region divided into meshes is associated with each node of the calculation model of FIG. 8(b). Processing at each node is executed while processors connected to the connection network exchange boundary information via links with processors processing adjacent nodes.

A torus or mesh-like connection network requires a relatively small amount of hardware to implement and is easy to use.

Since it has the same topology as the model to be simulated, the model can be naturally mapped onto a parallel computer.

However, such a mesh-coupled parallel computer system
For problems with models of other patterns.

Difficult to apply successfully. A mesh or torus-like connection network requires less hardware to implement, but... j! Efficiency tends to drop when trying to process coarse message patterns. Therefore, it can be used as a connection network for general-purpose parallel computer systems.

A more complex connection network such as a hypercubic type is often adopted.

Therefore, there is a need for a method for processing a mesh or torus pattern model on a parallel computer having a highly complex connection network such as a hypercube type.

FIG. 9 shows a conventional example of a parallel computer having a hypercubic all-to-all communication network. In this example, eight processors P
Eo to PE are each enabled to perform direct communication processing with any other party via the all-to-all communication network. There are various methods of communication coupling, such as a method of coupling at the time of one communication request, a method of allocating a fixed timing to one communication partner so that communication can be performed sequentially, and a method of providing a dedicated bus.

[Invention tries to solve! ! ! ! [Problem] By the way, if the number of nodes in a mesh or torus pattern is much larger than the number of processors that can be used for parallel processing, it is possible to divide all nodes and allocate multiple nodes to each processor.5 Parallel processing by each processor multiple times Need to repeat. However, at this time, it is desirable to have as many opportunities as possible to communicate between processors processing adjacent nodes, and to average these opportunities among the processors.

An object of the present invention is to provide a method for efficiently performing information processing that requires mesh or torus pattern communication processing on a parallel computer equipped with a connection network capable of processing all-to-all communication.

[Means to solve Section H]

The present invention devises a mapping method that allocates nodes to each processor when communication processing between nodes connected in a mesh or torus pattern is performed by parallel processing using multiple processors. This is to ensure that the process is carried out efficiently.

FIG. 1 is a diagram explaining the principle of the present invention, and FIG. 1(a) shows the invention in the case of a mesh pattern, and FIG. 1(b) shows the invention in the case of a torus pattern in an exemplary manner. It is something that

In the mesh pattern case shown in FIG.
A processor group consisting of E, 2 is a processor PE. or an all-to-all communication connection network that connects PEt in an all-to-all manner; 3 has 8x8 nodes to be processed, and each node is connected to its upper, lower, left, and right adjacent nodes in a mesh pattern; 4, 5, 6;
．． 7 indicates a loop, and AA' and BB' indicate diagonal lines.

Loops 4 and 7 are loops set along diagonals AA' and 88', respectively, and include 16 (8×2) nodes. Also loops 5 and 6.

These loops are set so that nodes do not overlap outside loops 4 and 7, respectively, and similarly include 16 nodes.

In the diagram, two processors PE0 to PEt are assigned to each of the loops 4, 5, and 6゜7 created in this way.
PEa and PEs are assigned to loop 6, and PE and PE are assigned to loop 7.

Once two processors are assigned to each loop, the two processors are alternately assigned to successive nodes on the loop.

FIG. 2(a) is an example of a mesh pattern node in which processors are assigned in this way, and the numbers O to 7 in the nodes are the numbers indicated by the subscripts of Bromo-Tsa PE to PE. Next, in the invention for the torus pattern of FIG. 1(b), the processor group 1 (PE, ~PE,) and the all-to-all communication network 2 of FIG. 1(a) are shown. However, this is omitted for the sake of convenience, and the same as shown in FIG. 1(a) is applied as is.

In FIG. 1(b), 8 has 8×8 nodes, and each node is connected to adjacent nodes on the upper, lower, left, and right sides, and
This is a torus pattern in which the upper and lower ends and the left and right ends are respectively connected. Further, 9, 10° and 11.12 are X-shaped patterns set parallel to diagonals AA' and B-8', respectively, and each X-shaped pattern 9 includes 16 nodes that do not overlap. .10, 11.12, 8
Two processors are assigned from the processors PEG or PE, and in each X-shaped pattern, five
The two assigned processors are alternately assigned to successive nodes on the X-shaped pattern.

FIG. 2(b) shows an example of a torus pattern of nodes to which processors are assigned in this manner.

Note that in FIGS. 1(a) and 1(b), a mesh pattern and a torus pattern with eight processors and 8×8 nodes are used as examples;
1 for a mesh pattern and a torus pattern with n nodes; 20 nodes each for each mesh pattern and torus pattern using n processors and an all-to-all communication network with the square root of the number of nodes; Create n / 2 loops or X-shaped patterns that include without overlap, and for these n / 2 loops or , and furthermore, the two processors to which one is assigned within each loop or X-shaped pattern may be alternately assigned to successive nodes.

[Effect]

In the invention for the mensch pattern of FIG. 1(a), any one loop intersects orthogonally with any other loop at four points. Since each loop is associated with two separate 7'o sensors, each processor has the opportunity to process adjacent nodes four times with every other processor, i.e., to perform communication coupling between nodes. It will be worth it. A similar thing occurs between the X-shaped patterns shown in FIG. 1(b).

By mapping the mesh pattern or torus pattern model to each processor of the parallel computer in this way, it is possible to average the amount of communication to other processors in each processor.

For example, in FIG. 2(a), the number of links to be processed by processor 1 is four, including those leading to processor O, those leading to processor 2, and those leading to subsequent processors. .

Therefore, it can be said that the amount of communication to other processors than the processor 1 is averaged. A similar situation holds true for all processors.

Therefore, mesh or torus pattern communication processing can be performed efficiently by all-to-all communication.

(Embodiment) FIG. 3 shows the configuration of a parallel computer according to two embodiments of the present invention.

In the figure, 1 is a processor group consisting of PEs, and 2 is an all-to-all communication network connecting all pairs of PRs to PEs. Also 13.

This is a phase control unit that controls the connection between nodes in the all-to-all communication connection "fI42."

The phase control unit 13 has a plurality of phases S. In a certain phase S, a node ■ (V=O~?)
(!:, VeS (V and 5171EOR).

Note that the nodes here refer to the nodes in the all-to-all communication connection wA2, that is, the processors PE, ~PE.

With this control function, when S is swept from 0 to "number of nodes = 1', the partner nodes ■■S with which any node ■ can communicate in each phase S are as shown in the linear table, and any node V is When S=0 to 7 complete one cycle, all nodes can be used as communication partners. That is, all-to-all communication is realized.

Own node Communication partner node (V([)S)V S
=O, top, 2.3. Sat, 5.6.70 0.
1,2,3.4,56,71 1.0,3,2,
5,4,7,62 2.3,0,1,6,7,4
,53 3.2.1.0,7,6,5,44
4 5.6,7,0.1,2,35 5.4
．． 7.6,1,0.3,26 6.7,4.5.
2.3,0,17 7.6.5,4.3.2,1
．． By the way, good results can be obtained if the order of sweeping the phases S is not in the ascending order as in the previous table but in the order of the 5-inverted Gray code.

Figure 4 shows the structure of a one-inversion Gray code, in which only one bit changes between adjacent binary codes (the focus distance is "pi"), and the tree structure of the binary code is inverted at each level. (have symmetry).

Using an inverted Gray code with this structure, phase S
The sequence is advanced as 0.1, 3, 2.6, 7°54, and each loop of the mesh pattern and each X-shaped pattern of the torus pattern explained in Fig. 1 (a) and (b) is By assigning processors to each in the order of this inverted Gray code, we can obtain the results shown in Fig. 8(a), (
A mapping result as shown in b) can be obtained.

When mapping is performed based on the inverted Gray code in this way, the four points around each node in the calculation model become four consecutive numbers in the inverted Gray code (Figure 8 (a),
(see (b)). This is extremely advantageous when each processor performs communication processing for two surrounding nodes in a pipeline immediately after performing calculation processing for the node.

FIG. 6 shows the processing sequence of the processor PE.

This example targets a calculation model of a torus pattern shown in FIG. 5(b).

Assume that the processing node assigned to the processor PE1 with processor number 1 has coordinates on the torus expressed as (vertical coordinates, horizontal coordinates).

(1,6), (2,4), (3,8), (42), (5
,2),,(6,8),(7,4).

(8, 6). In order to process each node, it is necessary to communicate with the processors assigned to the nodes around each node.6 For example, considering node (1, 6), writing to the nodes around it is necessary. It can be seen from the processor number 9 that processing this node requires communication with the processor number 1, 0.3.2. In FIG.

It should be noted that, as shown by the input/output arrows to each processing node in successive phases, calculation processing and communication processing are executed in a pipeline manner, so that the overhead of communication does not appear. A similar situation has been achieved in other processors.

〔Effect of the invention〕

As explained above, according to the present invention, information processing that requires mesh or torus pattern communication processing can be efficiently performed on a parallel computer equipped with a connection network capable of processing all-to-all communication. This greatly contributes to improving the availability of parallel processing of the pattern.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of a mapping example according to the present invention, Fig. 3 is a configuration diagram of a parallel computer according to an embodiment of the present invention, and Fig. 4 is an inversion diagram used in an embodiment of the present invention. FIG. 5 is an explanatory diagram of the gray code, and FIG. 5 is an explanatory diagram of the mapping result according to the embodiment of the present invention. FIG. 6 is an explanatory diagram of the processing sequence of the processor PE+ according to the embodiment of the present invention, FIG. 7 is an explanatory diagram of mesh-like and torus-like connection networks, and FIG. 8 is an explanatory diagram of a processing example of a problem with a mesh pattern. FIG. 9 is a block diagram of a conventional example of a parallel computer having an all-to-all communication network. In Figure 1, 1: Processor group (PE, ~PE. 2: All-to-all communication connection network 3: Mesh pattern 4-7: Loop 8 Nidorus pattern 9-12: X-shaped pattern

Claims (2)

[Claims] (1) Information processing that requires communication processing in a mesh pattern with n×n nodes is carried out in a parallel computer consisting of multiple processors and equipped with a connection network that allows all-to-all communication between each processor. When performing the process, using n processors, a loop passing through 2n nodes of the mesh pattern along each of two orthogonal diagonals of the n×n mesh pattern is sequentially moved away from the diagonal and the same nodes are overlapped. Create n/2 processors without selecting them, assign two processors selected from the n processors to each of the n/2 loops created, and then assign two processors selected from the n processors to each of the n/2 loops created. 2n nodes on the loop are sequentially and alternately assigned to each processor, and each of the n processors processes the assigned n nodes in parallel n times. A parallel processing method characterized by (2) Information processing that requires communication processing in a torus pattern with n×n nodes is carried out in a parallel computer consisting of multiple processors and equipped with a connection network that allows all-to-all communication between each processor. When performing this, n processors are used to select an X-shaped pattern that passes through 2n nodes of the torus pattern in parallel to each of the two orthogonal diagonals of the n×n torus pattern, repeatedly selecting the same nodes. n/2 processors are created without The 2n nodes on the X-shaped pattern are sequentially and alternately assigned to the processors, and each processor is assigned n nodes, and each of the n processors processes the assigned n nodes in parallel. A parallel processing method characterized by processing n times.