JPH03115923A - Signal interpolating circuit and displacement measuring instrument equipped with the same - Google Patents

Abstract

PURPOSE:To make misoperation detection accurate by providing a dividing means which divides an original signal and generates plural pulses with specified number and detecting the malfunction of a dividing means according to the variation of the generated pulses. CONSTITUTION:Signals (a) and (b) from input terminals 1 and 2 are inputted to comparators 4 - 7 to obtain binarization signals (f) and (g), and (h) and (i), which are inputted to a direction discriminating circuits 8; and the signal (f) corresponding to the original signal (a) is delayed D by a delay circuit 10. Further, counter 9 counts signals (j) and (k) being divided signals from the circuit 8 and outputs counting data (m) to a decision circuit 12 to generate a pulse (n) with specific time width in response to the leading edge of the delay signal from the circuit 10. Then the pulse (n) is used as the reset signal of the counter 9 and the circuit 12 decides whether or not the data (m) is coincident with the specific number of division.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a signal interpolation circuit used in a displacement measuring device such as an incremental rotary encoder or a linear encoder.

[Prior Art] Traditionally, in magnetic or optical incremental rotary encoders and linear encoders, two signals having different phases obtained from two sensors have been used.
The amount of displacement and direction of movement of the movable scale are detected using two sine wave signals (two-phase sine wave signals). and,
For example, in a rotary encoder, in order to further increase the resolution of detection of the rotation angle of the rotation scale, a signal interpolation circuit is used to generate multiple sine wave signals having phase differences from the above two-phase sine wave signal. It is known to form multiple split pulse signals based on these sinusoidal signals.

FIG. 9 is a block diagram showing an example of the signal interpolation circuit. In the figure, 1 and 2 are input terminals, for example,
Sine wave signals output from two sensors of a rotary encoder and having mutually different phases are input. For example, with respect to a signal a input to input terminal 1, a signal having a phase difference of 90 degrees from signal a is input to input terminal 2. In addition, the signal a is input to the inverting circuit 3, and the signals a and 1
A signal C having a phase difference of 80 degrees is obtained. These three sinusoidal signals a.

b and c are appropriately weighted by resistance or the like and added to interpolate a sine wave signal at an arbitrary angle (phase angle).

In the figure, the resistance values of the resistors R are all set to the same value, and signals d and e having a phase difference of 45 degrees and 136 degrees with respect to the signal a are obtained. These signals a, d, b, e are each
Corresponding comparator 4. 5. 6. 7 into rectangular wave signals (binarized signals) f, g, h, i, and a direction discrimination circuit 8 outputs the signals in the form of a pulse train. This pulse train is generally called an up-down pulse, and is divided into an up pulse j or a down pulse k depending on the phase relationship between the signals a and b (which one is leading). In this way, the original signal a (b)
Since the angle is divided into multiple parts, the resolution of angle detection can be further improved. FIG. 10 shows an example of waveforms f to f in FIG. 9. In this case, a pulse signal j (k during reverse rotation) is obtained by dividing the -period of the rectangular wave signal f (or h) corresponding to the input signal a (or b) into eight. These up/down pulses j and k are counted to detect the angle.

However, when the rotation speed of the rotation scale changes and rotates at high speed, the frequency of the sine wave signal input to input terminals 1 and 2 increases, and the signal interpolation circuit cannot follow the high frequency signal and malfunctions. was found to occur.

U Overview of the Invention] A first object of the present invention is to provide a signal interpolation circuit that can accurately detect the above-mentioned malfunction.

A second object of the present invention is to provide a displacement measuring device equipped with a signal interpolation circuit that can accurately detect the above-mentioned malfunction.

In order to achieve the first object, the signal interpolation circuit of the present invention includes a dividing means for dividing an original signal to generate a predetermined number of pulses, and a dividing means for dividing an original signal to generate a predetermined number of pulses. It has a detection means for detecting a malfunction of the dividing means based on fluctuations in the pulse, such as the period of the pulse, and by adopting such a configuration, it is possible to prevent malfunction in the circuit due to an increase in the frequency of the original signal. What has happened can be accurately detected.

Therefore, for example, it is possible to prevent the continuous input of erroneous signals to a signal processing system provided at a later stage of the circuit.

Further, in order to achieve the second object, the displacement measuring device of the present invention includes a scale reading means for reading the scale formed on the movable scale and outputting a signal according to the displacement of the scale; and a dividing means for dividing the signal into a plurality of pulses having a predetermined number of pulses,
The displacement of the scale is measured by counting the pulses from the dividing means, and further, the malfunction of the dividing means is detected based on the pulse fluctuation, such as the number of pulses or the period of the plurality of pulses. It has a detecting means for detecting. With this configuration, even if the displacement of the movable scale becomes faster and the frequency of the signal from the reading means becomes higher, it is possible to accurately detect a malfunction in the apparatus. Therefore, for example, by outputting a predetermined alarm signal based on the detection result by the detection means and stopping the operation of the device, it is possible to prevent the device from continuing to make inaccurate displacement measurements.

Some features and specific embodiments of the present invention will be made clear in each embodiment described below.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a signal interpolation circuit according to the present invention. In FIG. 1, the same members as those shown in FIG. 9 are given the same reference numerals as in FIG.

Therefore, explanations of these members will be omitted and other members will be explained. A counter 9 is configured to count up/down pulses (divided pulses) j and k, which are divided signals output from the direction discrimination circuit 8, and output count data m. 10 is the original signal a before division
a delay circuit that gives a slight delay to the signal f corresponding to l;
1 is a pulse generating circuit such as a monostable multi-by-break, which generates a pulse n of a predetermined time width in response to a rising edge of a signal f delayed by D from a delay circuit 10. This pulse n is used as a reset signal for the counter 9. 12 is a discrimination circuit that determines whether the count data m of the counter 9 matches the division number N predetermined by this circuit, and only when they match, the output p becomes H (high level, logic 1). is configured to be.

The operation of the circuit shown in FIG. 1 will be described with reference to waveform examples of each signal shown in FIG. Note that the circuit shown in FIG. 1 divides the -period of the input signal (original signal) into eight, similar to the circuit shown in FIG. 9. The count data m is reset at {circle around (2)} (at the rising edge of the signal f) in FIG. 2, and the counter 9 counts up every rising edge of the signal j. Therefore, if there is no malfunction in the circuits up to the direction discrimination circuit 8, the count data m will be 8 (1, 0, 0, 0 from the upper bit in binary) at the next time the signal f rises. . At this time, the discrimination circuit 12 determines that the count data m is the number of divisions N
(N8), and the output p therefrom becomes H. At time point (2), when a short time has elapsed from time point (2), the counter 9 is reset by the signal n, and at the same time, the output p of the discrimination circuit 12 also becomes L (low level, logic 0). In this example, the signal p becomes H immediately after the rising edge of the signal f, thereby confirming that eight divisions are reliably performed.

By utilizing this discrimination circuit 12, various types of processing can be performed.

Next, FIG. 3 shows a case where the frequency of the sine wave signal (phase angle 00.90°) input to input terminals 1 and 2 becomes high and the divided pulses from the direction discrimination circuit 8 cannot be separated from each other. Let me explain using an example. The count data m is reset at 3 (at the rising edge of the signal f) in FIG. 3, and the counter 9 counts up every rising edge of the signal j. In the example shown in Figure 3, the fifth and sixth
The th pulse is combined into one pulse, and the 5th and 6th pulses cannot be separated, so at the next time the signal f rises, the count data m is 7 (0 from the upper bit).・1・1・l). At this time, in the discrimination circuit 12, the count data m does not match the division number N (N=8), so the output p therefrom remains at L.

In this way, by checking whether the signal p is H or not immediately after the rising edge of the signal f (time point 2), it can be determined whether the division is being performed correctly in this circuit.

In the above embodiment, an example was shown in which the delay of the signal f by the delay circuit 10 was relatively short, but basically, the counter It suffices if the settings are set so that the reset operation in step 9 is completed.

In the above embodiment, in order to detect a malfunction of the dividing means (1 to 8), the counter 9 counts the number of divided pulses within a period corresponding to one cycle of the signal f. , without being limited to one period of the signal before division.
Any period can be set as long as it is an integral multiple of the resolution (1/4 period) obtained by the signal f and signal h (ie, signal a and signal b).

Further, the means for determining whether the count value m matches the division number N and the form of the signal indicating the determination result are not limited to the determination circuit 12 or the signal p of the above embodiment.

Furthermore, the circuit of the above embodiment is particularly effectively used in a displacement measuring device such as a rotary encoder or a linear encoder for detecting the amount of movement or the speed of movement of a moving object.

As described above, the circuit is configured to count the number of divided pulses generated within a specific period, determine whether the input signal is divided correctly by the dividing means (1 to 8), and output the result. With this configuration, for example, in a displacement measuring device, it is possible to generate a signal that can accurately issue a warning when the scale displacement becomes high speed while confirming whether the predetermined division is being performed reliably. I can do it.

FIG. 4 is a block diagram showing another embodiment of the signal interpolation circuit according to the present invention. In FIG. 4, the same members as those shown in FIG. 9 are given the same reference numerals as in FIG. 9. Therefore, explanations of these members will be omitted and other members will be explained. A counter 9 is configured to count up-down pulses (divided pulses) Lk, which are divided signals output from the direction discrimination circuit 8, and output count data m. 13 and 14 are pulse generation circuits such as retriggerable monostable multi-bibreak circuits, which generate divided pulses 3. Generate up/down pulses u, v with a wider pulse width than k. 90 is a counter, and pulse generation circuit 13. 14, and outputs counting data q. 10 is a delay circuit that gives a slight delay to the signal f corresponding to the original signal a before division; 11 is a pulse generation circuit such as a monostable multi-bibreak;
A pulse r having a predetermined time width is generated in response to a rising edge of a signal from the delay circuit 10 that is delayed by a signal f fJ<D. This pulse r is used as a reset signal for the counter 90. Reference numeral 15 denotes a discrimination circuit that judges whether the count data q of the counter 12 matches the division number N predetermined in this circuit. Only when they match, the output S becomes H (high level, logic 1). ).

The operation of the circuit shown in FIG. 4 will be explained with reference to the waveform examples of each signal shown in FIG. Incidentally, the circuit shown in FIG. 5 also divides the -period of the input signal (original signal) by 8 and 1, similar to the circuit shown in FIG. 9. The count data q is reset at ◯ (at the rising edge of the signal f) in FIG. 5, and the counter 90 counts up every rising edge of the signal U.

Therefore, if there is no malfunction in the circuits up to the direction discrimination circuit 8, the count data q will be 8 (I, 0, 0, 0 from the upper bit in binary) at the next time when the signal f rises.
becomes. At this time, the determination circuit 15 determines that the data q matches the division number N (N=8), and the output S therefrom becomes H. At time point (2), after a short period of time has elapsed from time point (2), the counter 90 is reset by the signal r, and at the same time, the output S of the discrimination circuit 15 also becomes L (low level, logic O). In this example, the signal S becomes H immediately after the rising edge of the signal f, thereby confirming that eight divisions are reliably performed.

By utilizing this discrimination circuit 15, various types of processing can be performed.

Next, when the frequency of the sine wave signal (phase angle 0°, 90°) input to the input terminal 1.2 becomes high (so that the divided pulses from the direction discrimination circuit 8 cannot be separated from each other (slightly before) This will be explained using FIG. 6 as an example.The count data q is reset at ■ (at the rising edge of the signal f) in FIG. The pulse arrangement period fluctuates from the 3rd to the 6th pulse, and the 3rd and 4th pulses, and the 5th and 6th pulses cannot be separated (marked with a mark).
Therefore, at the next time when the signal f rises, the count data q
becomes 6 (0.1ψ1.O from the upper bit). At this time, in the discrimination circuit I5, the data q is divided into the number of divisions N (N=8
) does not match, so the output S remains at L.

In this way, the signal S immediately after the rising edge of the signal f becomes H.
By checking whether the pulses U and V generated in response to the pulses j and k are correctly separated, it can be determined whether the pulses U and V generated in response to the pulses j and k are separated correctly. As shown in Fig. 6, even if pulse U (or V) starts to become inseparable, the pulse width of divided pulse j is narrower than this, so
Although the periodic fluctuation of the pulses has occurred, it is still possible to separate the pulses, and a correct count value can be obtained from the output m of the counter 9. Therefore, it is possible to know more reliably and earlier than the embodiments shown in FIGS. 1 to 3 whether or not the division is being performed correctly in this circuit, or whether it is being performed correctly.

In the above embodiment, an example was shown in which the delay of the signal f by the delay circuit 10 is relatively short, but basically, the up-down pulse U (or V) is emitted before the next pulse signal V rises. It is sufficient that the setting is made so that the reset operation of the counter 90 is completed.

In the above embodiment, in order to detect a malfunction of the dividing means (1 to 8), the counter 9 counts the number of divided pulses (u, v) within a period corresponding to one cycle of the signal f. , this counting period is not limited to one cycle of the signal before division, but is a period that is an integral multiple of the resolution (1/4 cycle) obtained from the signal f and signal h (i.e., signal a and signal b). That's fine.

Further, the means for determining whether the count value q matches the division number N and the form of the signal indicating the determination result are not limited to the above method.

Next, a further embodiment of the present invention will be described with reference to FIG. In the figure, up to counters 9 and 90 are the same as in the embodiment shown in FIG. In this embodiment, counters 9 and 90
The comparator 16 compares the counting results m and q, determines whether they are equal or not, and outputs the result as a signal S. With this configuration, for example, if the scale displacement is slow and the input signal frequency is low, the counting result m
, q are always equal, but as the displacement of the scale becomes faster and the frequency of the input signal becomes higher, the interval between up and down pulses becomes narrower, the signal U (or V) cannot be separated, and the counting results m and q become different. It's coming. Therefore, it can be determined whether a malfunction is occurring in the circuit or whether a malfunction has occurred in the circuit.

Note that the circuits of each of the above embodiments can also be effectively used in a displacement measuring device, such as a rotary encoder or a linear encoder, for detecting the moving amount and moving speed of a moving object.

As described above, based on the divided pulse, up-down pulses having a wider pulse width than the divided pulse are generated, and by detecting whether these up-down pulses can be separated, the input signal is divided by the dividing means (1 to 8). Since we have configured a circuit to determine whether the division has been performed correctly and output the result, for example, you can check whether the specified division has been performed in the displacement measuring device while adjusting the scale. It is possible to generate a signal that can accurately warn when the displacement becomes high speed.

FIGS. 8(A) and 8(B) show schematic diagrams of a displacement measuring device equipped with a signal interpolation circuit of the present invention. This embodiment shows an example in which an optical displacement measuring device is used to measure the position of a wafer stage of an exposure apparatus for semiconductor manufacturing.

In the figure, 100 is a scale reading means, 101 is a semiconductor laser, 102 is a collimator lens, and 30 is an optical scale having a diffraction grating with a grating pitch d, which is attached to a wafer stage 300, and is in the direction of arrow X shown in the figure. is moving with speed V. The stage 30 is the drive device 5
Driven by 00. 109 is a polarizing beam splitter, 1151 and 152 are each an X wavelength plate, 111. 112
is a reflecting mirror, 106 is a beam splitter - 1171, 17
Polarizing plates 2 are arranged so that their polarizing axes are orthogonal to each other, and the polarizing axes of the A wavelength plates 151 and 152 form an angle of 45 degrees. 181,1
Reference numerals 82 each represent a light receiving element, which photoelectrically converts interference.

Reference numeral 110 denotes a stick-shaped lens of a refractive index distribution type with flat ends on both ends that images light incident from one end surface on the other end surface, and a reflective film 121 is provided on one end. Lens 11
0 and the reflective film 121 constitute a reflective element 120.

As described later, the light receiving element 181. The sine wave signals from the light receiving element 182 have a phase difference of 90 degrees, and the signal with a phase angle O0 from the light receiving element 181 is transmitted to the signal interpolation circuit 20.
A signal with a phase angle of 90° from the light receiving element 182 is input to the input terminal 2 of the signal interpolation circuit 200. The signal interpolation circuit 200 is composed of the circuit shown in FIG. 1, and calculates the displacement of the stage 300 by dividing the signal from the light receiving element 181182 and counting the up and down pulses formed. Measure. This measurement result is sent to the control device 400, and the control device 400 controls the position of the stage 300 via the drive device 500.

On the other hand, for some reason, the moving speed of the stage 300 increases, and the light receiving element 181. When the frequency of the signal from 182 becomes higher than a certain level, the control device 4
00 issues an alarm. Then, the operation of the device is stopped.

In this embodiment, a coherent light beam from a semiconductor laser 101 is made into a substantially parallel light beam by a collimator lens 102, and is made incident on a polarizing beam splitter 109. ) is divided into two beams.

At this time, the mounting position of the semiconductor laser 101 is adjusted so that the linear polarization direction of the emitted light beam of the semiconductor laser 101 is 45 degrees with respect to the polarization direction of the polarization beam splitter 109. This allows the polarizing beam splitter to
The intensity ratio between the transmitted light beam and the reflected light beam from 109 is approximately 1.l.

Then, the reflected light flux and the transmitted light flux from the polarizing beam splitter 109 are respectively transferred to the A wavelength plate 151. 152 into circularly polarized light, reflected by reflecting mirrors 111 and 11.2, and obliquely incident on optical scale 30. Each light beam is made incident on the optical scale 30 so that the m-th order diffracted light from the target optical scale 30 exits substantially perpendicularly from the diffraction grating surface of the optical scale 30.

That is, the grating pitch of the diffraction grating of the optical scale 30 is P
1. The wavelength of the coherent light beam from the semiconductor laser 101 is λ,
When m is an integer and the angle of incidence of the coherent light beam on the diffraction grating surface (angle from the perpendicular to the diffraction grating surface) is θ□, θm#5in-'(mλ/p)...(
1).

The reflected light beam from the polarizing beam splitter 109 obliquely enters the optical scale 3 at an incident angle θ□, is reflected and diffracted by the diffraction grating of the optical scale 30, and the second diffracted light exits from the optical scale 30 perpendicularly. On the other hand, the transmitted light beam from the polarizing beam splitter 109 obliquely enters the optical scale 30 at an incident angle of -〇□, is reflected and diffracted by the diffraction grating of the optical scale 30, and -1st-order diffracted light is transmitted to the optical scale 30.
Exit vertically from 0. In this embodiment, the incident position of the reflected light flux and the transmitted light flux on the optical scale 30 is the same, and a pair of (±1st-order)
The diffracted lights overlap. Therefore, the reflected and diffracted lights form a common optical path. Note that the optical paths of the transmitted light beam, the reflected light beam, and the reflected diffracted light from the polarizing beam splitter 109 are included in the same plane of incidence (plane parallel to the paper surface).

The ±1 diffracted light emitted perpendicularly from the optical scale 30 heads toward the reflective element 120 and enters the end face of the lens 110. The lens 110 is a stick-shaped lens, and so that parallel light incident on one end surface forms an image on the other end surface.
Its length is set. That is, the focal plane of element 120 is at the end face of the element. A reflective film 121 is formed on the other end face.

Therefore, the upper order diffracted light incident on lens 1]0 is shown in Figure 8 (
After being reflected by the reflective film 121 as shown in FIG.
0.

Then, the ±1st-order reflected diffracted light that is diffracted again by the diffraction grating of the optical scale 30 returns to the original optical path and returns to the reflecting mirror 111.
, 112 and is reflected by the A wave plate 1.51. 1.52 and enters the polarizing beam splitter 109 again.

At this time, each re-diffracted light is transmitted to the % wavelength plate 151. 152, the (S-polarized) light beam that was first reflected by the polarizing beam splitter 109 has a polarization direction of 90 when it re-enters the polarizing beam splitter 1,09.
Since they are P-polarized lights of different degrees, they are transmitted through the polarizing beam splitter 109. Conversely, the light beam (P-polarized light) that first passes through the polarizing beam splitter 109 becomes S-polarized light, and is reflected when it enters the polarizing beam splitter 109 again.

In this way, the two re-diffracted lights are superimposed by the polarizing beam splitter 109, turned into oppositely circularly polarized lights by the wavelength plate 153, and split into two beams by the beam splitter 106, each of which is divided by the polarizing plate 171. via 172,
The light is linearly polarized, and the light receiving element 181. 182 as interference light.

Incidentally, the incident angle θ□ in equation (1) means that the diffracted light is
0 and then enters the optical scale 30 again.

In this example, the phase of the m-th order diffracted light is set to 1 by the diffraction grating.
When the pitch is moved, it changes by 2mπ.

Therefore, the light receiving element 181. 182 receives interference light caused by interference between light beams that have undergone positive and negative m-order diffraction twice and photoelectrically converts it, so when the diffraction grating moves one pitch of the grating, 4m sine wave signals are obtained. It will be done.

Therefore, the pitch of the diffraction grating of the optical scale 30 is set to 3.
Since the first order (m = 1) was used as the 2 μm 1 diffracted light, when the optical scale 30 moved by 3.2 μm, the light receiving element 181. Four sine wave signals are obtained from 182. In other words, the resolution per sine wave is the diffraction grating 30.
pitch of 3.2/4. =0.8 μm is obtained.

In addition, wave plates 151, 152, 153 and polarizing plates 17
By the combination of 1°172, the light receiving elements 181, 1
A phase difference of 90 degrees is provided between the output signals (sine wave signals) from the diffraction grating 82, so that the moving direction of the diffraction grating 30 can be determined and the signals can be interpolated.

In this embodiment, the optical path of the ±1st-order diffracted light emitted from the optical scale 3 is shared, and the light is directed back to the optical scale 3 via a common reflective element 20. That is, since there is no need to provide individual reflecting mirrors for individual diffracted lights, the apparatus can be constructed in a compact and simple manner. Moreover, this reduces the rate at which stray light is generated and reaches the light receiving element, thereby improving the detection accuracy of interference fringes.

Furthermore, as shown in FIG. 1, all the components constituting the device can be easily provided above (on one side) the optical scale 3, providing an extremely versatile optical encoder.

Since the reflective element 120 in this embodiment has a reflective surface near the focal plane, even if the angle of incidence on the lens 110 changes slightly due to a slight change in the diffraction angle due to a change in the oscillation wavelength of the laser beam, for example, , the diffracted light is passed through the optical scale 3 along approximately the same optical path.
can be returned to. As a result, the two positive and negative diffracted lights are accurately overlapped, and as a result, the light receiving element 181.
This prevents the S/N ratio of the output signal of 182 from decreasing. Then, the incident angle θ□ of the laser beam on the optical scale 3
is set as described above, and the reflective element 120 is used to reduce the size of the entire device.

Therefore, the grating pitch 3 of the diffraction grating of the optical scale 30
．． 2 μm, and the wavelength of the laser 101 is 0.78 μm, the diffraction angle of the ±1st order diffracted light is 1 as mentioned above.
It is 4.2 degrees. Therefore, the lens 110 has a diameter of 2 m.
When only the ±1st-order diffracted light is reflected using a graded refractive index lens of about m, the distance from the optical scale 30 to the lens 110 is 2/1 an 14.2° 7.9 mm.
Therefore, it is only necessary to separate them by about 8 mm, and the entire device can be configured to be extremely compact.

In this embodiment, the light receiving element 181. The optical path length (opt
ical path length) are equal. Therefore, even if the wavelength of the semiconductor laser 101 changes, interference fringes that respond only to the displacement of the optical scale 3 can be formed. Furthermore, an inexpensive multimode semiconductor laser can be mounted as a light emitting element.

In this embodiment, as understood from FIG. 1, the polarizing beam splitter 9, the reflecting mirror 111 . 112, the optical path of the optical system consisting of the reflective element 120 is symmetrical, and constitutes a system that is insensitive to disturbances such as vertical movement of the optical scale 30.

In this embodiment, the signal interpolation circuit 200 shown in FIG. 1 is used, but the circuit shown in FIG. 4 or FIG. 7, for example, may also be used. Further, since such a displacement measuring device does not perform inaccurate measurements, it is effective not only for measuring the position of a wafer stage but also for measuring the position of a magnetic head or an optical head.

[Effects of the Invention] As described above, in the present invention, the frequency of the original signal (input signal) is high (
Since it is possible to accurately detect that a malfunction has occurred in the circuit, it is possible to prevent, for example, from continuing to input an erroneous signal to a signal processing system provided at a subsequent stage of the circuit. Therefore, it is possible to provide highly reliable displacement measuring devices such as various types of encoders such as magnetic, optical, linear, and rotary encoders.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal interpolation circuit according to the present invention. FIGS. 2 and 3 show the signal f+ jr m shown in FIG.
The figure which shows the waveform example of rnrp. FIG. 4 is a block diagram showing another embodiment of the signal insertion circuit according to the present invention. 5 and 6 show the signal f+L u+ shown in FIG.
The figure which shows the waveform example of q, r, and s. FIG. 7 is a block diagram showing a further embodiment of the signal interpolation circuit according to the present invention. FIGS. 8(A) and 8(B) are schematic diagrams showing one embodiment of a displacement measuring device according to the present invention. FIG. 9 is a block diagram showing an example of a conventional signal interpolation circuit. FIG. 10 shows the signals f, g, h, i shown in FIG.
, j. The figure which shows the example of a waveform of k. 1.2...Input terminal 3...Inverting circuit 4, 5. 6. 7... Comparator 8...
Direction discrimination circuit 9.90...Counter 10...Delay circuit 11, 13. 14... Pulse generation circuit 1.2.
15. 16...Discrimination circuit 30...Optical scale 100...Scale reading means 200...Signal interpolation circuit 400...Control device ρ l

Claims (1)

[Claims] (1) Division means for dividing an original signal to generate a plurality of pulses of a predetermined number of pulses, and detection for detecting malfunction of the division means based on fluctuations in the plurality of pulses. A signal interpolation circuit having means. (2) A scale reading means that reads the scale formed on the movable scale and outputs a signal according to the displacement of the scale, and divides the signal from the reading means to generate a plurality of pulses with a predetermined number of pulses. A displacement measuring device that measures the displacement of a scale by counting pulses from the dividing means, further comprising a detection unit that detects malfunction of the dividing means based on fluctuations in the plurality of pulses. A displacement measuring device characterized by having a means. (3) When the graduation of the scale is composed of a diffraction grating, the reading means photoelectrically converts the interference light obtained by interfering the positive and negative diffracted lights of the same order generated by the diffraction grating to generate the signal. The displacement measuring device according to claim 2, wherein the displacement measuring device is configured to output. (4) The detecting means is configured to count the number of pulses in one period of the signal from the reading means or a period corresponding to the period, and detect fluctuations in the number of pulses. A displacement measuring device according to claim (2). (5) The displacement measuring device according to claim (2), wherein the detection means is configured to detect periodic fluctuations of the plurality of pulses.