JPH03113939A - Line connection circuit - Google Patents

Abstract

PURPOSE:To prevent power consumption at an undesired time by supplying power to a line forming means of a main equipment side in a transmission line other than a unidirectional transmission line only when a voltage level of the unidirectional transmission line keeps a high level except in the low level for a prescribed time zone. CONSTITUTION:When a master equipment 1 desires write and read to a terminal equipment 2, the terminal equipment 2 connects to the master equipment 1 with a cable 3 to turn on switches 1s, 2s of both the equipments 1, 2. In the case of write, the master equipment 1 sets a driver buffer 4a of each bit in an IC 4 and sends a write control pulse pW to a line 3d. Since the power is supplied to the IC 4 and resistors 5, 6 of the master equipment 1 only when the terminal equipment 2 being a communication opposite party is in the operating state, power consumption at an undesired time is prevented.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a line connection circuit for transmitting data between a main device in a computer system and a terminal device such as an external floppy disk. .

(Prior Art) Conventionally, in information processing-related communication, a system as shown in FIG. 4 is usually used.

In FIG. 2, numeral 1 denotes a main device consisting of a microcomputer, also called a master station, and 2 a terminal consisting of its expansion unit, printer, etc. The main device 1 and the terminal 2 are connected by a cable 3 with a connector. This cable 3 includes data transmission lines, expansion boards 2a, 2
When b, .

In each device 1.2, in front of the connectors 3a, 3b,
A buffer serving as a driver or a receiver, and a terminating resistor for impedance matching to prevent signal reflection are provided. Communication between the devices 1 and 2 is performed with the power switches Is and 2s turned on, respectively, and a communication line established by supplying power to their buffers and terminating resistors.

However, conventionally, in this type of system, as long as the main device 1 is powered on, power is supplied to the buffer and the terminating resistor, and power is consumed, which has been a problem from the viewpoint of energy saving.

In other words, terminal 2 is not connected, or
When terminal 2 is not in operation, the buffer and terminating resistor described above are not required, but even in such a case, if it is powered on, power will be supplied, which will save wasted power. This means that you are consuming it.

In addition, there is a conventional method that deals with this type of power consumption problem, as shown in Japanese Patent Application Laid-Open No. 64-70819, but this method does not depend on whether a terminal is connected to the main device or not. The power supply is controlled only by the system, and it is still far from being sufficient.

(Question 8 to be solved by the invention) In this way, in this type of communication system,
There was a problem in that as long as the i11 was powered on, power was consumed even though it was not necessary.

The present invention has been made in view of these problems.
The purpose is to provide a line connection circuit that can save power in a communication system.

[Structure of the invention]

(Means for Solving the Problems) The line connection circuit of the present invention connects a line driver of a one-way transmission line from the main device to the terminal device among the signal transmission paths connecting the main device and the terminal device to an output terminal thereof. One-way transmission is possible only when the voltage level of this one-way transmission line remains high except for the low-level state for a predetermined period of time. Power is supplied to line forming means on the main device side in a transmission line other than the transmission line.

(Function) According to the present invention, power is supplied to the line forming means of the main device only when the terminal device that is the communication partner is in an operating state, so power is consumed even though it is not necessary. This can be prevented.

Furthermore, according to the present invention, whether or not the terminal device is in an operating state is determined based on the voltage level of the one-way transmission line, so there is no need to add a line dedicated to detection, and the existing cable It is possible to connect with.

(Example) Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a line connection circuit according to an embodiment of the present invention. Here, a case is shown in which the terminal device 2 is an external storage device such as a floppy disk device.

First, the cable 3 includes parallel bidirectional signal transmission lines 3c, 3c, . . . and unidirectional signal transmission lines 3d.
3e. The transmission lines 3c3c, . . . are
They are used as data transmission lines, and for example, in the case of 8-bit parallel, eight lines are provided. One-way transmission line 3
d and 3e are used as control signal lines for read/write and the like.

Note that the signal transmission line serving as the address line is not shown here because it is almost the same as the data transmission line.

The main device 1 is provided with a driver/receiver IC4, and this IC4 connects a parallel circuit consisting of a driver buffer 4a and a receiver buffer 4b to a signal transmission line 3C.
Contains the number of books. Each parallel circuit is connected to each signal transmission line 3C, and controls the connection and directionality of the data transmission line. This IC4 has a power supply voltage V
ccl is applied through the power supply line 27, and each buffer 4a, 4b of the IC4 operates with this power supply voltage Vccl being applied.

One end of each of antireflection terminating resistors 5 and 6 is connected to each connection point between each parallel circuit of the IC 4 and each signal transmission line. The other end of the resistor 5 is connected to the power supply line 27, and the other end of the resistor 6 is grounded.

The main device 1 further includes a driver buffer 7 consisting of an Ic.
．． 8 is provided. Buffer 7 is signal transmission line 3
d, and the buffer 8 is connected to the signal transmission line 3e. The signal transmission line 3d is used for transmitting write control pulses, and the signal transmission line 3e is used for transmitting read control pulses.

Here, FIG. 3 shows the signal state of the main part, and in this figure, the symbol pW is a write control pulse, and the symbol pR
indicate readout control pulses, and each pulse p
W and pR have a short time width of 500 nsec, for example.

The terminal device 2 is provided with an IC 9 for a driver and a receiver, and similarly includes parallel circuits consisting of a driver buffer 9a and a receiver buffer 9b for the number of signal transmission lines 3C. Each of these parallel circuits is connected to each signal transmission line 3.
It is connected to C and controls the connection and directionality of the data transmission path. This IC9 has a power supply voltage Vcc2
is applied to each buffer 11a of IC9.

11b operates while this power supply voltage Vcc2 is applied.

One end of an anti-reflection terminating resistor 10.11 is connected to each connection point between each parallel circuit of the IC9 and each signal transmission line 3C. A power supply voltage Vcc2 is applied to the other end of the resistor 10, and the other end of the resistor 11 is grounded.

The terminal device 2 is further provided with receiver buffers 12 and 13 made of ICs. The buffer 12 is connected to the signal transmission line 3d, the buffer 13 is connected to the signal transmission line 3e, and both 12 and 13 are used to control on/off of the control signal transmission line. These buffers 12.
13 is applied with a power supply voltage V cc2 and operates while receiving this power supply voltage V ec2.

Buffers 12.13 and each signal transmission line 3d.

One end of a pull-up resistor 14, 15 is connected to each connection point with 3e. The power supply voltage Vcc2 is applied to the other ends of these pull-up resistors 14 and 15, and the signal transmission lines 3d and 3e are connected to each pull-up resistor 1.
4.15, it is raised to H'' (high level) as shown in FIG.

The driver buffers 7.8 of the main device 1 are of an oven collector type, and are supplied with an electric R voltage from the terminal device 2 through the signal transmission line 3d or 3e, respectively.

The main device 1 is further provided with a level detection circuit 16, a negative logic AND gate 19, and a switch circuit 20.

The level detection circuit 16 detects the voltage level of the signal transmission line 3d, and the voltage level is set to L due to the write control pulse.
” (low level) state, when the terminal device 2 is maintained at “H”, it is assumed that the terminal device 2 is in the operating state and an operating state notification signal is output. It is configured.

The delay circuit 17 is for delaying the fall of the write control pulse pW, and a time constant is set so that the input level to the inverter gate 18 does not fall below the threshold value during the pulse time width.

The inverter gate 18 is configured to input the signal on the signal transmission line 3d via this delay circuit]7,
As a result, the level of the line 3d is set to "L" (low level) by the write control pulse, as shown in the figure S3.
Except for the state, when maintaining "H", it continues to output "L". This "L" signal is used as the above-mentioned operating state notification signal, and is also passed to an information processing mechanism section (not shown) as a status signal ST.

The "L" signal of the inverter gate 18 and the enable signal EN from the information processing mechanism section are input to the AND gate 19, and both signals are "
The "L" signal is output only when the signal is "L".

The switch circuit 20 consists of a PNP transistor 21, its base resistor 22, and a bias resistor 23, and is driven by the "L° signal" of the AND gate 19 to turn on.
A power supply voltage V eel is applied to C4 and the terminating resistors 5 and 6.

Next, the operation of this embodiment configured as described above will be explained.

First, assuming that the terminal device 2 is not connected to the main device 1, the line 3d becomes "L" and the output of the inverter gate 18 becomes "H", so the output of the AND gate 19 becomes '
Since the transistor 21 is turned off, no current flows through the power supply line 28, and the IC 4 and the terminating resistor 5
, 6 are not supplied with the power supply voltage V eel.

Furthermore, even if the terminal device 2 is connected, if its power switch 2s is off, the line 3d becomes "L" as in the case of not being connected, so the IC 4 and the terminating resistor 5
．． 6, the power supply voltage Vccl is not supplied.

Next, when the switch 2s of the terminal device 2 is turned on,
Since the signal transmission line 3d becomes "H", the output of the inverter gate 18 becomes "L" and the AND gate 19 is opened, so the transistor 21 is turned on by the input of the enable signal EN, and current is applied to the power supply line 28. flows, and the power supply voltage V eel is applied to the IC 4 and the terminal resistors 5 and 6.
is applied.

Therefore, when the clay 5f1 wants to write to or read from the terminal device 2, first connect the terminal device 2 to the main device 1 using the cable 3, and then turn on the switches is and 2s of both devices 1 and 2.
Turn on.

In this state, in the case of writing, the main device 1 turns on the driver buffer 4a of each bit in the IC 4 and transmits a write control pulse pW to the line 3d.

Then, the terminal device 2 receiving this write control pulse pV
turns on the receiver buffer 9a of the IC9.

In this state, the main device 1 transmits write data through the buffers 4a, 4a, . . . lines 3c+3c, . This data is received by receiver buffers 9a, 9a, . . . on the terminal device 2 side, and written to a recording medium (not shown).

Note that in the case of reading, buffer 4b is used instead of buffer 4a, and buffer 9b is used instead of buffer 9a.
This is the same as above except that the terminal device 2 is turned on and the read data flows from the terminal device 2 side to the main device] side.

As described above, according to this embodiment, power is supplied to the IC 4 and the resistors 5 and 6 of the main device 1 to the terminal device 2, which is the communication partner.
Since this is done only when the is in operation, it is possible to prevent power from being consumed unnecessarily.

Furthermore, according to this embodiment, whether or not the terminal device 2 is in an operating state is determined based on the voltage level of the signal transmission line 3d, which is a one-way transmission line.
There is no need to add a dedicated line for detection, and connections can be made using existing cables.

Furthermore, since the inverter gate 18 is of Schmitt characteristic, the terminal device 2
Even if the power supply voltage Vcc2 rises slowly over a long period of time, it is possible to prevent the terminal device 2 from being detected as being in an operating state before its level reaches the drive level.

FIG. 2 shows a modification of the level detection circuit of the line connection circuit according to another embodiment of the present invention.

In this figure, 24 is its level detection circuit. This level detection circuit 24 is composed of inverter gates 25 and 26 having Schmitt characteristics and an OR gate 27 of negative logic.

The inverter gate 25 receives the signal on the signal transmission line 3d, and the inverter gate 26 receives the signal on the signal transmission line 3e.
Take the above signal as input. These outputs are input to the OR gate 27, and if any one of them is “H”,
'L' is output.

In other words, this device focuses on the fact that the write control pulse p'w and the read control pulse pR are not generated at the same time, and detects the levels of both lines 3d and 3e and ORs their outputs. The control pulse pW compensates for each other's level fluctuations to "L", thereby determining whether the terminal device 2 is in the operating state.
, one can be performed without being hindered by pR.

Furthermore, the present invention can be realized even if the driver buffer 7.8 in the main device 1 is configured as an oven-drain type CMO8.

〔Effect of the invention〕

As explained above, according to the present invention, the line driver of the one-way transmission line from the main device to the terminal device among the signal transmission paths connecting the main device and the terminal device has an open output terminal. Only when the voltage level of this unidirectional transmission line is maintained at a high level except for the low level state for a predetermined time width, power is supplied to the line forming means on the main device side of the transmission line other than the unidirectional transmission line. Therefore, power is supplied to the line forming means of the main device only when the terminal device that is the communication partner is in an operating state, thereby preventing power from being consumed unnecessarily. I can do it.

Furthermore, according to the present invention, whether or not the terminal device is in operation is determined based on the voltage level of the unidirectional transmission line, so there is no need to add a dedicated line for detection, and the existing cable Wiring can be done with .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a line connection circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of a level detection circuit of a line connection circuit according to another embodiment of the invention. 3
FIG. 4 is a time chart showing the signal states in the main parts of the circuits shown in FIGS. 1 and 2, and FIG. 4 is a block diagram showing the outline of the data communication system. 1... Main device, 2... Terminal device, 3... Cable, 4... Driver/receiver IC for bidirectional line. 5.6...Terminal resistor, 7,8...Driver buffer with open output and inner terminals, 16.24...Level detection circuit, 20...Switch circuit, 28...Power supply line .

Claims (1)

[Scope of Claims] A line driver provided in a one-way transmission line from the main device to the terminal device among the signal transmission lines connecting the main device and the terminal device, and whose output terminal is an open type; a line forming means provided on the main device side of a transmission line other than the one-way transmission line among the signal transmission paths and configured to establish the transmission line by receiving power supply; and a line forming means provided on the terminal device and configured to establish the transmission line; a pull-up resistor that pulls up the voltage of the one-way transmission line to a high level; and a pull-up resistor that detects the voltage level of the one-way transmission line and maintains the high level except when the voltage level is at a low level for a predetermined time width. level detection means that determines that the terminal device is in an operating state and generates an operating state notification signal; a switch that is turned on by being driven by the operating state notification signal; and only when the switch means is in an on state. A line connection circuit comprising: power supply means for supplying the power to the line forming means;