JPH03113655A - Cache memory and processor element - Google Patents

Abstract

PURPOSE:To easily maintain the consistency of a cache memory without deteriorating the processing performance of a processor by setting access from the processor to be enabled and making a direction transferred from the other device freeze. CONSTITUTION:A control register 9 executes control in such a way that access is not executed as to access from the direction to which prohibition is instructed and writing is executed as to access from a direction to which freezing of the tag part 1 is instructed, and a data part 2 is updated at the time of tag coincidence and the tag part 1 and the data part 2 are not updated at the time of tag part dissidence. Namely, access from the processor is set enabled and the direction transferred from the other device is set frozen. The consistency of the cache memory is maintained without deteriorating the processing capacity of the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a computer cache memory and a processor element using the same, and is particularly closely related to a computer with a multiprocessor configuration. The configuration diagram of the memory is shown in Fig. 5. Here, 1 is a tag, 2 is a data eye, 3 is a comparison @4 is a hit signal, 5 is an address bar input, 6 is a data bus, 9 is a control register, and 17a and 17b are decoder sections. In a conventional cache memory configured as above: In normal use, control register 9 is set to EN (enable) asserted and FRZ (freeze) negated.In this case, when writing, the tag is unconditionally set. When reading, update the tag section 1 and data section 2 only when there is a miss.A Also, when debugging a system using cache memory, make settings different from normal settings.First, control When the EN (enable bit) of register 9 is negated, the cache memory is not accessed. Also, when FRZ (freeze pit) is asserted (the friend cache memory is not updated), the tag part matches when inserted and written. Other than writing to the data section when there is a hit (hit), the tag section and data section are not updated even when there is a match under the tag (hereinafter referred to as a miss).

Furthermore, a configuration diagram of a conventional processor element is shown in FIG. Here, 18 is a cache memory 1, 19 is an external device input, 20 is a processor, and 21 is a data transfer device.
22 is a main memory, 23a and 23b are input signals, and 25 is a transfer control signal.

In the conventional processor element configured as described above, the processor 20 accesses the cache memory 18 via the bus 23a. If the access target does not exist in the cache memory 18, the main memory 22 is accessed via the bus 23b. do.

Data transfer with the external device 19 (The data transfer device 21 sends a transfer control signal 25 to the main memory 22 to transfer data between the main memory 22 and the external device 19. Consistency is guaranteed by software, but there are problems to be solved with the cache memory described above.

The entire cache is inhibited or frozen regardless of the access direction, to maintain consistency in multiprocessor systems that are frequently accessed from multiple directions (if processor processing and transfer target the same memory area) , prohibit the use of the cache or let the cache monitor the main memory (bus snoop) L. If the consistency is broken, cache invalidation etc. are performed. However, during path scooping, the use of the cache is restricted.
This means that the bus bandwidth is reduced, and the processing performance of the processor is reduced.

In addition, since the data is transferred to the main memory using the processor element mentioned above, the transfer speed is slow (Also, since the consistency between the cache memory and main memory depends on the software, it is possible to disable the use of the cache memory or to purge it. Occurs, both of which mean performance degradation.

In view of this, an object of the present invention is to provide a cache memory optimal for a multiprocessor system and a processor element using the cache memory.

Means for Solving the Problems The present invention (table) A tag section holding an address, a data section holding data corresponding to the address, and an address to be accessed and an address read from the tag section are compared and matched; A comparator that determines a mismatch, a control register that stores instruction information for prohibiting each of a plurality of access directions and freezing the tag section, and accessing from a direction that is instructed to be prohibited in the control register. Furthermore, in response to access from the direction in which freezing the tag section is instructed, the data section is updated when writing and the tag section matches, and the tag section and the data section are also updated even when the tag section does not match. This is a cache memory having a control section that performs control that does not perform.

The present invention also provides a data transfer method comprising a processor, a main memory, and a cache memory connected to the processor and the main memory, which can be accessed from the outside and holds a part of the contents of the main memory. The present invention also works on a processor element which is configured with a device and has a mode in which the cache memory is not accessed in response to an external access to the cache memory, or in which update is not performed in the event of a cache miss. With the above-mentioned configuration, the cache memory performs a Clock access in response to an access from a direction that is prohibited (not enabled) by the control register.Also, the cache memory performs a Clock access in response to an access from a direction in which the tag section is instructed to be frozen (freeze). In addition to updating the data section when writing and the tag section match, control is also performed so that the tag section and data section are not updated even when the tag section does not match.

As a result, by enabling access from the processor and freezing the direction of transfer from other devices, the consistency of the cache memory can be maintained without degrading the processing performance of the processor. With the configuration described above, when the data transfer device transfers data to another device (the data is read from the built-in cache memory, the speed is high).Also, when receiving and receiving data transferred from another device, the data transfer device transfers data to another device (a). control, without reducing the processing performance of the processor.
Maintains cache memory consistency.

Embodiment FIG. 1 shows a configuration diagram of a cache memory in an embodiment of the present invention. In FIG. 1, 1 is a tag, 2 is a data sensor, 3 is a comparator, 4 is a hit signal, 5 is an address buff, , 6 is data bar input 9 is control register length
11 is the selection signal q12a, 12b is the chip select signal
13a and 13b are ports, 14 is address selector
15 is a data selector 16 is a control hand Q 17a, 1
7b is a decoder section, and the operation of the cache memory configured as above is explained.The control register 9 is a decoder section, and a control register 9 is a decoder section.
Each has an enable bit (EN) and a freeze bit (FRZ). Here, F and EN mean use of cache memory. J'1LFRZ means freezing of tag section. The control means 16 outputs the selection signal 11 in response to the chip select signals 12a and 12b, and the address selector 14,
Switch the data selector 15 to the boat (13a or 13b) to be accessed.

For access from the direction of EN=1 and FRZ=0, normal access is performed. The lower part of buried board address 5 is decoded by the decoder section 17a and the tag part 1 is read out. This is compared with the upper part of address 5 by the comparator 3. If there is a match, a hit signal 4 is output. If there is a mismatch, it means a miss. Even if the hit signal 4 remains negated, the tag section 1 and the data section 2 will be updated regardless of whether there is a hit or a miss. Update When reading, main memory read is performed only when there is a miss.\ Tag section 1 and data section 2 are updated, but access is not performed from the direction of EN = 0 and FRZ = 0tt Main memory access is performed. (Do not change the contents of the cache memory tt When accessing from the direction of EN = 1 and FRZ = 1 The tag section 1 and the data section 2 are not updated even when there is a mismatch (mishit) in the above mechanism. Although the consistency of the cache memory can be maintained without deteriorating the processing performance of the processor in a multiprocessor system etc. by setting the Figure 3 shows the configuration of the processor element in the first embodiment, and Figure 4 shows the operation timing chart of the multiprocessor system using the processor element of the first embodiment. , 18 is a cache memory, 20 is a processor, 21 is a data transfer function, 22 is a main memory, 2
3 a, 23b, 23c are bar entry 24 is network access
30a and 30b are processor elements, and as shown in FIG. 2, the processor elements are composed of a processor 20, a data transfer device 21 with a built-in cache memory 18, and a main memory 22. Processor 20, data transfer device 2
1. From both sides, the memory hierarchy is cache memory 18,
The main memory 22 is in that order. The data transfer device 21 transfers data to and from outside the processor element (bus 23C).
(via) Case k Memory access is performed in the order of the memory hierarchy described above.

FIG. 2(a) C The processor 20 and the data transfer device 21 are a model in which the data transfer device 21 and the main memory 22 are connected by dedicated buses 23a and 23b, respectively. Since the buses are independent, for example, transfer can be performed simultaneously between the processor 20 and the cache memory 18, and between the data transfer device 21 and the main memory 22, resulting in high transfer performance (1° Fig. 2 (b) (upper processor 20, Data transfer device 2
1. This is a model in which the main memories 22 are connected via a common bus 23a. Since it is a common bus, it is easy to add other devices to the bus 23a, which reduces the performance in the case shown in FIG. 2(a), and has high versatility.

FIG. 3 LL is a configuration diagram of a multiprocessor system in which two processor elements of FIG. 2(a) are connected via a network 24. Here, the cache memory 18 is shown in the embodiment of the present invention, and in any processor element, EN=1 and FRZ=O for access from the processor 20, and FRZ=O for access from the network 24. is EN=1 and F
Set RZ=1.

Processing by the processor and data transfer at this time will be explained using FIG. 4. In cycle 1 (CI), processor 20a processes array A (N). Array A
(N) i Since it is frequently accessed, there is a high probability that it exists in the cache memory 18a. Data transfer device 21. A reads the processed data sequentially from the cache memory 18a and transfers it to the processor element 30b via the network 24. The receiver writes these data to the data transfer device 21b on the receiving side and the main memory 22b.The question here is whether or not to write this data to the cache memory 18b at the same time. At this point, the processor 20b is processing the array B(N), so the array A(N) is stored in the cache memory 18b.
), there is a possibility that the data in array B (N) will be evicted from the cache memory t 8 b. Here, the settings described above come into play effectively. Since updating of the tag part is prohibited for access from the network 24, there is a low possibility that the cache memory 18b will be updated, so the processing function of the processor 20b will not be degraded. Therefore, there is no need to worry about the consistency of the contents being lost (V) From the perspective of the processor element 30b, the operation is the same.In other words, the processor 20b does not process the array B(N)\\The data transfer device 18b does not perform the processing. The completed data is sent to the processor element 3 sequentially via the network 24.
Transfer to 0a side.

Subsequently, in cycle 2 (C2), the processor 20a processes array B (N), and the processor 20b processes array A (N), and after the processing is completed, transfer is performed in the same way as in cycle 1.

In general numerical calculations, this series of operations is repeated until the data converges.

As explained above, when the processor element of this embodiment (the data transfer device transfers data to the network) reads from the built-in cache memory becomes faster.Also, when receiving and receiving data transferred from the network ( It is possible to maintain data that is immediately needed in the cache memory and maintain consistency with the main memory.

Note that in the above embodiment, the cache memory is prohibited from updating the tag section (freeze) when accessed from the network.
For example, in cycle 1, if the software guarantees that the array A (N) does not exist in the cache memory 18b (prohibits access to the cache memory 18b from the friend network 24) EN=0).

Effects of the Invention As described above, the cache memory (friend) of the present invention is
By freezing the direction in which data is transferred from other devices, the consistency of the cache memory can be easily maintained without degrading the processing performance of the processor. In addition, when the data transfer device of the present invention transfers data to another device, it reads from the built-in cache memory, resulting in high speed. Also, when receiving and receiving data transferred from another device, Lt.
Retains immediately needed data in cache memory2.
Maintains cache memory consistency.

This means a significant reduction in overhead for processing transfers, and is extremely useful in multiprocessor systems that are expected to develop in the future.

[Brief explanation of drawings]

FIG. 1 shows the configuration of a cache memory in one embodiment of the present invention.
, Figure 3 shows the configuration of the processor element in the second embodiment, and Figure 4 shows the configuration of the multiprocessor system using the processor element of the first embodiment. Figure 5 shows the operation timing chart of the multiprocessor system. Configuration diagram of a conventional cache memory Figure 6 is a configuration diagram of a conventional processor element.
4...Hit signal 5...Address buff S 6...
・Data bar input 9...Control register length 11...Selection signal q12a, 12b...Chip select signal 13a,
13 b-boat, 14... address select 15
...Data select 16...Control hand tl17a, 1
7b...Decoder clothes 18.18a, 18b--cache memory, 20.20a, 20b-processor, 21.21 a, 2 l b-data transfer device 22
, 22a, 22b...main memory, 23a, 23b
, 23 c-・-ba entry 24-...Network 30
a, 30b...processor element.

Claims (2)

[Claims] (1) a tag section that holds an address, a data section that holds data corresponding to the address, and a comparator that compares the accessed address and the address read from the tag section to determine whether they match or do not match; A control register that stores instruction information for prohibiting and freezing the tag portion for each of a plurality of access directions, and accesses from directions that are instructed to be prohibited in the control register are not accessed;
In addition, for access from the direction where freezing of the tag section is instructed, in addition to updating the data section when writing and the tag section match, the tag section and the data section are also updated when the tag section does not match. A cache memory having a control unit that performs control that is not performed. (2) Data transfer that includes a processor, a main memory, and a cache memory that is connected to the processor and the main memory, that can be accessed from the outside, and that holds part of the contents of the main memory. 1. A processor element comprising a device and having a mode in which the cache memory is not accessed in response to an external access to the cache memory, or an update is not performed in the event of a cache mishit.