JPH03112143A - Socket for testing semiconductor element - Google Patents
Socket for testing semiconductor elementInfo
- Publication number
- JPH03112143A JPH03112143A JP1251677A JP25167789A JPH03112143A JP H03112143 A JPH03112143 A JP H03112143A JP 1251677 A JP1251677 A JP 1251677A JP 25167789 A JP25167789 A JP 25167789A JP H03112143 A JPH03112143 A JP H03112143A
- Authority
- JP
- Japan
- Prior art keywords
- tape carrier
- semiconductor device
- under test
- device under
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 239000011347 resin Substances 0.000 claims abstract description 6
- 230000013011 mating Effects 0.000 claims description 7
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 230000003252 repetitive effect Effects 0.000 abstract 1
- 230000002950 deficient Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920003002 synthetic resin Polymers 0.000 description 3
- 239000000057 synthetic resin Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000003909 pattern recognition Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Connecting Device With Holders (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体素子の試験用ソケットに関し、
被試験半導体素子を試験可能に仮接続し、被試験半導体
素子を着脱して反復使用できるようにすることを目的と
し、
合わせ面中央に被試験半導体素子を挿入セットするくぼ
みを備える絶縁性下部ケースと前記導電接触状況を監視
する覗き窓を有する絶縁性上部押さえ蓋との間に、前記
セットした被試験半導体素子の電極に導電接触するイン
ナーリードと外部試験装置の電極に導電接触するように
外側に張り出したアウタリードとを樹脂フィルム上に形
成してなるテープキャリアと該テープキャリアを押圧す
る添えばねを挟み、係着手段により結合・分離可能に重
ね合わせ構成する。[Detailed Description of the Invention] [Summary] Regarding a socket for testing a semiconductor device, the purpose is to temporarily connect a semiconductor device under test so that it can be tested, and to enable repeated use by attaching and detaching the semiconductor device under test. The electrodes of the set semiconductor device under test are placed between an insulating lower case having a recess in the center of the surface for inserting and setting the semiconductor device under test, and an insulating upper cover having a viewing window for monitoring the conductive contact status. A tape carrier formed by forming an inner lead in conductive contact and an outer lead protruding outward so as to come in conductive contact with an electrode of an external test device on a resin film, and a support spring that presses the tape carrier are sandwiched, and by a fastening means. Constructed in a superimposed manner so that they can be combined and separated.
本発明は半導体素子の試験用ソケットに関する。 The present invention relates to a socket for testing semiconductor devices.
半導体素子(チップ)は電極を備えるがリードがないこ
とから、簡単に無駄なく試験が行えることが望まれてい
る。Semiconductor elements (chips) have electrodes but no leads, so it is desired to be able to perform tests easily and without waste.
従来は半導体素子は電極を備えるがリードがないため、
半導体素子をパンケージングしてリードを出した半導体
装置を対象にする市販の試験用ソケットではリードを利
用して試験を行うので使用できない。そのため、半導体
素子をモジュールやプリント配線板などに一旦、実装し
てから試験し不良品をリジェクトしている。Conventionally, semiconductor devices have electrodes but no leads, so
Commercially available test sockets for semiconductor devices with leads exposed by pan-caging the semiconductor element cannot be used because the tests are performed using the leads. For this reason, semiconductor devices are first mounted on modules, printed wiring boards, etc., then tested, and defective products are rejected.
しかしながら、このような上記試験方法によれば、不良
の半導体素子と共にモジュールやプリント配線板等も使
用できなくなり、無駄が大きいといった問題があった。However, according to the above-mentioned test method, modules, printed wiring boards, etc. can no longer be used along with defective semiconductor elements, resulting in a large amount of waste.
上記問題点に鑑み、本発明は被試験半導体素子を試験可
能に仮接続し、被試験半導体素子を着脱して反復使用す
ることのできる半導体素子の試験用ソケットを提供する
ことを目的とする。In view of the above-mentioned problems, an object of the present invention is to provide a socket for testing a semiconductor device, which can temporarily connect a semiconductor device under test for testing, and can be used repeatedly by attaching and detaching the semiconductor device under test.
上記目的を達成するために、本発明の半導体素子の試験
用ソケットにおいては、合わせ面中央に被試験半導体素
子を挿入セットするくぼみを備える絶縁性下部ケースと
前記導電接触状況を監視する覗き窓を有する絶縁性上部
押さえ蓋との間に、前記セットした被試験半導体素子の
電極に導電接触するインナーリードと外部試験装置の電
極に導電接触するように外側に張り出したアウタリード
とを樹脂フィルム上に形成してなるテープキャリアと該
テープキャリアを押圧する添えばねを挟み、係着手段に
より結合・分離可能に重ね合わせ構成する。In order to achieve the above object, the semiconductor device testing socket of the present invention includes an insulating lower case having a recess in the center of the mating surface for inserting and setting the semiconductor device under test, and a viewing window for monitoring the conductive contact status. An inner lead that makes conductive contact with the electrode of the set semiconductor device under test and an outer lead that protrudes outward so as to make conductive contact with the electrode of the external test device are formed on a resin film between the insulating upper holding lid and the set semiconductor device under test. A tape carrier formed by the above-mentioned tape carrier and a spring for pressing the tape carrier are sandwiched between the tape carrier and the spring that presses the tape carrier.
被試験半導体素子をセントする絶縁性下部ケースと覗き
窓を有する絶縁性上部押さえ盈との間にテープキャリア
と該テープキャリアを押圧するその添えばねを挟み係着
手段により結合することにより、被試験半導体素子の電
極にテープ−トヤリアのインナーリードを、外部試験装
置の電極にアウタリードをそれぞれ添えばねにより押圧
して一時的に圧接導通し電気的を試験を行うことができ
、係着手段を開放することにより絶縁性上部押さえ蓋を
分離して被試験半導体素子を簡単に取り出し反復使用す
ることができる。The tape carrier and its support spring that presses the tape carrier are sandwiched between an insulating lower case that holds the semiconductor device under test and an insulating upper cover having a viewing window, and are connected by a fastening means. Attach the inner lead of the tape to the electrode of the semiconductor element and the outer lead of Toyaria to the electrode of the external test device and press them with a spring to temporarily establish pressure contact and conduct an electrical test, and release the fastening means. By separating the insulating upper cover, the semiconductor device under test can be easily taken out and used repeatedly.
以下図面に示した実施例に基づいて本発明の要旨を詳細
に説明する。The gist of the present invention will be explained in detail below based on embodiments shown in the drawings.
第1図は結合状態の外観斜視図、第2図は第1図のA−
B−C側断面図、及び第3図は第2図の被試験半導体素
子のセット前の分解側断面図である。Figure 1 is an external perspective view of the combined state, Figure 2 is A- in Figure 1.
3 is an exploded side sectional view of the semiconductor device under test shown in FIG. 2 before being set.
図示に示すように試験用ソケット11は、被試験半導体
素子10をセットする絶縁性下部ケース1と、絶縁性上
部押さえ蓋2と、透明ガラス3と、絶縁性下部ケース1
と絶縁性上部押さえ蓋2との間にテープキャリア4と添
えばね5とを挟み係着手段6、即ち留め具により結合・
分離するように構成される。As shown in the drawing, the test socket 11 includes an insulating lower case 1 in which a semiconductor device under test 10 is set, an insulating upper cover 2, a transparent glass 3, and an insulating lower case 1.
The tape carrier 4 and the support spring 5 are sandwiched between the insulating upper presser cover 2 and the tape carrier 4 and the attachment spring 5 are connected by a fastening means 6, that is, a fastener.
Configured to separate.
絶縁性下部ケース1は、合成樹脂材のモールド成形から
なり、合わせ面中央に被試験半導体素子10を挿入セン
トする方形のくぼみlaと、くぼみ1aの周囲合わせ面
にテープキャリア4のインナーリード4aを挿入する位
置決め溝1bを備える。この位置決めllbの深さはテ
ープキャリア4のインナーリード4aの厚さより僅かに
浅くして上からの押さえが効くようにし、挿入したイン
ナーリード4aはくぼみIa内にセットされた被試験半
導体素子10の電極10aに対応し位置決めされるよう
にする。そして、方形のくぼみ1aの平面視大きさ(縦
横)寸法は被試験半導体素子10がインナーリード4a
に対し位置調整することができるように僅かに太き(し
、深さ寸法は被試験半導体素子10を僅かに浮かして調
整できる程度にする。また、くぼみ1aの内周エツジは
面取りしてインナーリード4aが緩やかに撓むように傾
斜面1a−1を付ける。The insulating lower case 1 is made of molded synthetic resin material, and has a rectangular recess la in the center of the mating surface into which the semiconductor device under test 10 is inserted, and an inner lead 4a of the tape carrier 4 on the mating surface around the recess 1a. A positioning groove 1b for insertion is provided. The depth of this positioning Ilb is made slightly shallower than the thickness of the inner lead 4a of the tape carrier 4 so that it can be pressed from above, and the inserted inner lead 4a is attached to the semiconductor device under test 10 set in the recess Ia. The electrode 10a is positioned so as to correspond to the electrode 10a. The planar view size (vertical and horizontal) of the rectangular recess 1a is such that the semiconductor device under test 10 has inner leads 4a.
The inner circumferential edge of the recess 1a is chamfered so that the inner circumferential edge of the recess 1a can be chamfered. An inclined surface 1a-1 is attached so that the lead 4a is gently bent.
絶縁性上部押さえ盈2は、合成樹脂材のモールド成形か
らなり、絶縁性下部ケース1に重ね合わせたとき、くぼ
み1aに挿入した被試験半導体素子10の電極10aと
テープキャリア4のインナーリード4aの突起4a−1
との位置合わせ状況が分かるように透明ガラス3を嵌挿
する覗き窓2aを設け(但し、透明ガラス3は被試験半
導体素子lOをセット完了後に嵌挿する)、合わせ面に
はテープキャリア4を押圧する添えばね5をモールド後
にエポキシ樹脂系接着剤(図示路)で接着(またはイン
サートモールド)により備える。この添えばね5は、第
4図の平面図に示すように金属ばね板をパンチング加工
またはエツチング加工して一旦、リードフレーム5゛を
製作し、内、外枠5a ’ + 5b ’ は絶縁性上
部押さえ蓋2に固着した後にパンチング加工により切断
線E及びDで切断し、切断後に内側先端はインナーリー
ド4aを弾性押圧して撓ませ被試験半導体素子10の電
極10aに圧接導通するように僅かに下方に曲げ成形す
る。The insulating upper retainer 2 is made of molded synthetic resin material, and when stacked on the insulating lower case 1, the electrode 10a of the semiconductor device under test 10 inserted into the recess 1a and the inner lead 4a of the tape carrier 4 are connected to each other. Protrusion 4a-1
A viewing window 2a is provided through which a transparent glass 3 is inserted so that the alignment status can be seen (however, the transparent glass 3 is inserted after the semiconductor device under test IO has been set), and a tape carrier 4 is placed on the mating surface. After molding, the pressing spring 5 is provided by adhesion (or insert molding) with an epoxy resin adhesive (as shown). As shown in the plan view of Fig. 4, this additional spring 5 is made by punching or etching a metal spring plate to form a lead frame 5', and the inner and outer frames 5a' + 5b' are made of an insulating upper part. After being fixed to the holding lid 2, it is cut along cutting lines E and D by punching, and after cutting, the inner tip elastically presses the inner lead 4a to bend it slightly so as to make pressure contact with the electrode 10a of the semiconductor device under test 10. Bend and form downward.
テープキャリア4は、第5図の平面図に示すように絶縁
性下部ケースlのくぼみ1aに挿入セントした被試験半
導体素子10の電極10aに導電接触するインナーリー
ド4aと外部試験装置の電極(図示路)に導電接触する
ように外側に張り出したアウタリード4bとを樹脂フィ
ルム4c上に周知のTAB(Tape Automat
ed Bonding)技術により形成し構成される。As shown in the plan view of FIG. 5, the tape carrier 4 has an inner lead 4a that is in conductive contact with an electrode 10a of a semiconductor device under test 10 inserted into a recess 1a of an insulating lower case l, and an electrode of an external test device (not shown). A well-known TAB (Tape Auto
ed Bonding) technology.
インナーリード4aの先端はそれぞれ銅半球を圧着ボン
ディングした突起4a−1を備える。The tips of the inner leads 4a are each provided with a protrusion 4a-1 having a copper hemisphere bonded by pressure.
テープキャリア4は形状寸法によっては市販のものを流
用することもできる。A commercially available tape carrier 4 may be used depending on the shape and dimensions.
係着手段6、即ち留め具(第6図の斜視図参照)は合成
樹脂材のモールド成形からなり、重ね合わせた絶縁性下
部ケース1と絶縁性上部押さえ蓋2の角部に側面から挿
入して挟み一緒に嵌着する切欠き6aを有し、嵌着面に
凹凸係合する半球状の突起6a−1を突設する。そのた
め、絶縁性下部ケース1及び絶縁性上部押さえM2の方
のそれぞれ4つの角部の切欠きIc、2bの嵌着面にも
凹凸係合する半球状の凹部1cm1,2b−1を形成し
ておく。The fastening means 6, that is, the fastener (see the perspective view of FIG. 6) is made of molded synthetic resin material, and is inserted from the side into the corner of the overlapping insulating lower case 1 and insulating upper cover 2. A hemispherical protrusion 6a-1 protrudes from the fitting surface and has a notch 6a which is inserted into the fitting surface. Therefore, hemispherical recesses 1 cm 1 and 2b-1 that engage with the projections and depressions are also formed on the fitting surfaces of the four corner notches Ic and 2b of the insulating lower case 1 and the insulating upper presser M2, respectively. put.
この試験用ソケット11を用いて被試験半導体素子10
を試験する場合、試験用ソケソ1−11へのセントは′
r八へ自動実装機を用いてつぎのとおりに行う。Using this test socket 11, the semiconductor device under test 10
When testing, the cents to test sockets 1-11 are '
Using an automatic mounting machine, proceed as follows.
先ず、絶縁性下部ケース1をTAB自動実装機のテーブ
ル(図示路)の所定位置に載せ、被試験半導体素子10
をくぼみ内に挿入する。First, the insulating lower case 1 is placed on a predetermined position on the table (the path shown in the figure) of the TAB automatic mounting machine, and the semiconductor device under test 10 is
Insert into the recess.
つぎに、絶縁性下部ケースの位置決め溝1bにテープキ
ャリア4のインナーリード4aを嵌め(樹脂フィルム4
cは合わせ面上にある)、絶縁性下部ケースlの合わせ
面上に動かないようにTAB自動実装機に付属した図示
しない支持手段により保持する。Next, fit the inner lead 4a of the tape carrier 4 into the positioning groove 1b of the insulating lower case (resin film 4
c is on the mating surface), and is held by a support means (not shown) attached to the TAB automatic mounting machine so as not to move on the mating surface of the insulating lower case l.
その状態で、第7図の側断面図に示すようにエアチャッ
ク12を降下して被試験半導体素子10を吸着し僅かに
浮してTAB自動実装機に付属した図示しないパターン
認識手段により被試験半導体素子10の電極10aとテ
ープキャリア4のインナーリード4aの突起4a−1と
が一致するように被試験半導体素子10をくぼみlc内
で直交する矢印X、Y方向に移動調整し位置決めする。In this state, as shown in the side cross-sectional view of FIG. 7, the air chuck 12 is lowered to adsorb the semiconductor device 10 to be tested, and the semiconductor device 10 is slightly lifted up and placed under test by a pattern recognition means (not shown) attached to the TAB automatic mounting machine. The semiconductor device under test 10 is moved and adjusted in the orthogonal directions of arrows X and Y within the recess lc so that the electrode 10a of the semiconductor device 10 and the protrusion 4a-1 of the inner lead 4a of the tape carrier 4 are aligned.
そして、絶縁性下部ケースI及びテープキャリア4との
相対位置を予め、合わせてエアチャック12に吸着した
添えばね5付き絶縁性上部押さえ蓋2を降下して絶縁性
下部ケース1上に重ね合わせテープキャリア4を添えば
ね5で押圧し被試験半導体素子10の電極10aとイン
ナーリード4aの突起4a−1を接触する。Then, the relative positions of the insulating lower case I and the tape carrier 4 are adjusted in advance, and the insulating upper presser cover 2 with the spring 5 adsorbed on the air chuck 12 is lowered and the tape is superimposed on the insulating lower case 1. The carrier 4 is pressed by the support spring 5 to bring the electrode 10a of the semiconductor device under test 10 into contact with the protrusion 4a-1 of the inner lead 4a.
最後に、留め具6を角部の切欠きlc、2bに側面から
挟んで結合し、覗き窓2aに透明ガラス3を嵌挿しく透
明ガラス3は載せているだけで必要に応じて取り外しが
できる)、被試験半導体素子10のセットを完了する。Finally, connect the fasteners 6 by sandwiching them between the corner notches lc and 2b from the sides, and insert the transparent glass 3 into the viewing window 2a.The transparent glass 3 can be removed as needed by simply placing it on it. ), the setting of the semiconductor device under test 10 is completed.
このように半導体素子の試験用ソケットを、被試験半導
体素子をセットする絶縁性下部ケースと絶縁性上部押さ
え苦との間にテープキャリアと添えばねを挟み係着手段
により結合・分離可能に構成することにより、被試験半
導体素子は簡単に着脱することができて試験用ソケット
を反復使用することができ、テープキャリアに添えばね
を併用することにより被試験半導体素子の電極及び外部
試験装置の電極にリードを確実に導電圧接することがで
きる。In this way, the test socket for semiconductor devices is configured such that the tape carrier and the spring are sandwiched between the insulating lower case in which the semiconductor device under test is set and the insulating upper presser, so that they can be connected and separated by the fastening means. As a result, the semiconductor device under test can be easily attached and detached, and the test socket can be used repeatedly.By using the tape carrier in conjunction with the support spring, the semiconductor device under test and the electrodes of the external test equipment can be easily attached and removed. Leads can be reliably connected to conductive voltage.
外部試験装置に例えば、市販されるICソケットを流用
し、本発明の試験用ソケットを挿入し、あるいは試験用
モジュールやプリント配線板等の電極に直接、装着しそ
れらの電極にリードを一時的に導電圧接することにより
、いずれの場合もテープキャリアを半田付けせずに試験
することができる。そのため、被試験半導体素子が不良
の場合、不良の半導体素子だけをリジェクトし相手方は
反復使用することができる。For example, a commercially available IC socket can be used in an external test device, and the test socket of the present invention can be inserted into it, or it can be directly attached to the electrodes of a test module or printed wiring board, etc., and leads can be temporarily attached to those electrodes. The conductive contact allows the tape carrier to be tested without soldering in each case. Therefore, if the semiconductor device under test is defective, only the defective semiconductor device can be rejected and the other device can use it repeatedly.
また、テープキャリアは単体で添えばねと絶縁性下部ケ
ースとの間に挟持されているだけの構成であることから
、テープキャリアが損傷して使用できなくなれば、節単
に取り替え交喚することができ、市販のテープキャリア
も利用することができて好都合である。なお、テープキ
ャリアと被試験半導体素子の電極との位置合わせは従来
のTAB自動実装機を利用しパターン認識技術の応用で
節単に行うことができる。In addition, since the tape carrier is simply held between the support spring and the insulating lower case, it can be easily replaced if the tape carrier becomes damaged and cannot be used. Advantageously, commercially available tape carriers can also be used. Note that alignment of the tape carrier and the electrodes of the semiconductor device under test can be easily performed by using a conventional TAB automatic mounting machine and applying pattern recognition technology.
以上、詳述したように本発明によれば、添えばねを併用
したテープキャリアを絶縁性下部ケースと絶縁性上部押
さえ蓋との間に挟持し係着手段により結合・分離可能な
試験用ソケットに構成することにより、従来、単体で試
験することが困難であったペアチップレベルの半導体素
子をパンケージングされた半導体装置と同様の取扱で試
験用ソケットに簡単に着脱し試験することができ、半田
付は接続をしないため不良の半導体素子だけをリジェク
トすることができて生産性の向上を図ることができると
いった実用上極めて有用な効果を発揮する。As described in detail above, according to the present invention, a tape carrier using a spring is held between an insulating lower case and an insulating upper holding lid to form a test socket that can be connected and separated by a fastening means. By using this configuration, paired chip level semiconductor devices, which were conventionally difficult to test individually, can be easily inserted into and removed from test sockets and tested using the same handling as pancaged semiconductor devices. Since there is no connection, only defective semiconductor elements can be rejected, and productivity can be improved, which is extremely useful in practice.
第1図は本発明による一実施例の外観斜視図、第2図は
第1図のA−B−C側断面図、第3図は第2図の被試験
半導体素子のセント前の分解側断面図
第4図は第3図の添えばねの平面図、
第5図は第3図のテープキャリアの平面図、第6図は第
3図の留め具の斜視図である。
第7図は第2図の被試験半導体素子の位置調整状態を示
す側断面図である。
図において、
1は絶縁性下部ケース、
1aはくぼみ、
2は絶縁性上部押さえ蓋、
2aは覗き窓、
4はテープキャリア、
4aはインナーリード、
4bはアウタリード、
4cは樹脂フィルム、
5は添えばね、
6は係着手段(留め具)、
lOは被試験半導体素子、
10aは電極を示す。
・′?
テープキャリア玉
(係着手段)留め具6FIG. 1 is an external perspective view of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line A-B-C in FIG. 1, and FIG. 3 is an exploded side of the semiconductor device under test shown in FIG. 4 is a plan view of the support spring shown in FIG. 3, FIG. 5 is a plan view of the tape carrier shown in FIG. 3, and FIG. 6 is a perspective view of the fastener shown in FIG. 3. FIG. 7 is a side sectional view showing the position adjustment state of the semiconductor device under test shown in FIG. 2. FIG. In the figure, 1 is an insulating lower case, 1a is a recess, 2 is an insulating upper cover, 2a is a viewing window, 4 is a tape carrier, 4a is an inner lead, 4b is an outer lead, 4c is a resin film, and 5 is a support spring. , 6 is a fastening means (fastener), 1O is a semiconductor device to be tested, and 10a is an electrode.・′? Tape carrier ball (attachment means) fastener 6
Claims (1)
するくぼみ(1a)を備える絶縁性下部ケース(1)と
前記導電接触状況を監視する覗き窓(2a)を有する絶
縁性上部押さえ蓋(2)との間に、前記セットした被試
験半導体素子(10)の電極(10a)に導電接触する
インナーリード(4a)と外部試験装置の電極に導電接
触するように外側に張り出したアウタリード(4b)と
を樹脂フィルム(4c)上に形成してなるテープキャリ
ア(4)と該テープキャリア(4)を押圧する添えばね
(5)を挟み、係着手段(6)により結合・分離可能に
重ね合わせてなることを特徴とする半導体素子の試験用
ソケット。An insulating lower case (1) having a recess (1a) for inserting and setting a semiconductor device under test (10) in the center of the mating surfaces, and an insulating upper holding lid (2) having a viewing window (2a) for monitoring the conductive contact status. ), an inner lead (4a) is in conductive contact with the electrode (10a) of the set semiconductor device under test (10), and an outer lead (4b) extends outward so as to be in conductive contact with the electrode of the external test device. and a tape carrier (4) formed on a resin film (4c) and a spring (5) that presses the tape carrier (4) are sandwiched between the tape carrier (4) and the spring (5) that presses the tape carrier (4). A socket for testing semiconductor devices, which is characterized by the following characteristics:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1251677A JPH03112143A (en) | 1989-09-26 | 1989-09-26 | Socket for testing semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1251677A JPH03112143A (en) | 1989-09-26 | 1989-09-26 | Socket for testing semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03112143A true JPH03112143A (en) | 1991-05-13 |
Family
ID=17226374
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1251677A Pending JPH03112143A (en) | 1989-09-26 | 1989-09-26 | Socket for testing semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03112143A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06313788A (en) * | 1993-04-30 | 1994-11-08 | Fresh Quest Corp | Receptacle for semiconductor chip test |
JPH06331695A (en) * | 1993-05-20 | 1994-12-02 | Fresh Quest Corp | Receptacle for semiconductor chip test |
-
1989
- 1989-09-26 JP JP1251677A patent/JPH03112143A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06313788A (en) * | 1993-04-30 | 1994-11-08 | Fresh Quest Corp | Receptacle for semiconductor chip test |
JPH06331695A (en) * | 1993-05-20 | 1994-12-02 | Fresh Quest Corp | Receptacle for semiconductor chip test |
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