JPH03111724A - Synchronous charge accumulating type photodetector - Google Patents

Synchronous charge accumulating type photodetector

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Publication number
JPH03111724A
JPH03111724A JP25003589A JP25003589A JPH03111724A JP H03111724 A JPH03111724 A JP H03111724A JP 25003589 A JP25003589 A JP 25003589A JP 25003589 A JP25003589 A JP 25003589A JP H03111724 A JPH03111724 A JP H03111724A
Authority
JP
Japan
Prior art keywords
fet
chopper
photodetector
charge
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25003589A
Other languages
Japanese (ja)
Other versions
JPH0574012B2 (en
Inventor
Tsutomu Ichimura
市村 勉
Fumio Inaba
稲場 文男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Research Development Corp of Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Research Development Corp of Japan filed Critical Research Development Corp of Japan
Priority to JP25003589A priority Critical patent/JPH03111724A/en
Publication of JPH03111724A publication Critical patent/JPH03111724A/en
Publication of JPH0574012B2 publication Critical patent/JPH0574012B2/ja
Granted legal-status Critical Current

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  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)

Abstract

PURPOSE:To make it possible to detect light at high sensitivity and low noises by removing all load resistances for a detector, reading a voltage appearing at the internal impedance of an element with a FET amplifier, and providing a resetting FET. CONSTITUTION:A photodetector 1 comprises a photodiode wherein internal impedance is high and dark currents are extremely few. The cathode terminal of the photodetector is connected to the drain of a resetting FET 2 and the gate of a reading FET 3. A virtual capacitance C is present between the gate and the drain of the FET 2. When an ON pulse (-3V) is inputted, positive charge is accumulated in the capacitor C, and the part between the drain and the source conducts. Therefore, the charge accumulated in the stray capacitor of the photodetector 1 flows to the ground. When an OFF pulse (+1V) is inputted, a positive voltage is applied. Therefore, the accumulated positive charge is discharged, and the part between the drain and the source becomes the OFF state. Since any load resistor is connected to the photodetector 1. Johnson noise is determined with only the internal resistance of a detector, and the highly sensitive detection can be performed.

Description

【発明の詳細な説明】 産業上の利用分野〕 本発明は赤外域、特に近赤外域の極微弱光を高感度、低
ノイズで検出する光検出装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a photodetection device that detects extremely weak light in the infrared region, particularly in the near-infrared region, with high sensitivity and low noise.

〔従来の技術〕[Conventional technology]

従来、極微弱光を検出する方法として光電子増倍管を用
いた単一光子計数法が知られている。しかし、近赤外域
、特に900〜1600nmの帯域では光電面の量子効
率が著しく低下するため、Ge、In、GaAs、In
GaAs、あるいはInGaAsP等の半導体検出素子
を用いたほうがより高感度になる。
Conventionally, a single photon counting method using a photomultiplier tube is known as a method for detecting extremely weak light. However, in the near-infrared region, especially in the band from 900 to 1600 nm, the quantum efficiency of the photocathode decreases significantly, so Ge, In, GaAs, In
Higher sensitivity can be obtained by using a semiconductor detection element such as GaAs or InGaAsP.

このような半導体検出素子の中で光−電子増倍管と同様
の増幅能力を有するアバランシェフォトダイオード(A
 P D)を利用すると、単一光子計数法が原理的には
可能である。しかし、受光面の大きな検出素子がないこ
と、現在入手可能な80μm直径の受光面を有するもの
では、ダークカウントが10’とかなり高くなること、
さらには低温域でアバランシェ効果の不安定性によると
思われる波高分布の乱れが起きること等があるため、A
PDを用いた単一光子計数法で安定した動作をさせるこ
とが極めて困難である。
Among these semiconductor detection elements, an avalanche photodiode (A
PD), single photon counting is possible in principle. However, there is no detection element with a large light-receiving surface, and the dark count is quite high at 10' with the currently available one with a light-receiving surface of 80 μm in diameter.
Furthermore, disturbances in wave height distribution may occur in low-temperature regions, which is thought to be due to instability of the avalanche effect.
It is extremely difficult to achieve stable operation using the single photon counting method using PD.

現在近赤外域で用いられている光検出法は半導体素子が
発生した光電流を一般の計測機器で取り扱えるように何
らかの方法で増幅したものである。
The photodetection method currently used in the near-infrared region is to amplify the photocurrent generated by a semiconductor element by some method so that it can be handled by general measurement equipment.

このような前置増幅器には、増幅器自身のノイズをでき
るだけ抑えて素子からの信号を増幅させるもので、雑音
指数を小さくすると共に、必要に応じて信号の時間に対
する応答性を保持する必要がある。
This kind of preamplifier amplifies the signal from the element while suppressing the noise of the amplifier itself as much as possible, and it is necessary to reduce the noise figure and maintain the time response of the signal as necessary. .

一般的に高感度な検出器を前置増幅器としてよく用いて
いるものは、第10図(a)に示すような電圧増幅型、
第10図(b)に示すような電流−電圧変換型がある。
Generally, highly sensitive detectors are often used as preamplifiers, such as the voltage amplification type shown in Figure 10(a).
There is a current-voltage conversion type as shown in FIG. 10(b).

なお、第10図(C)は電圧増幅型検出器の等価回路、
第10図(社)は、電流−電圧変換型の等価回路である
。検出器31は信号源isに内部抵抗Rdと浮遊容量T
、が並列に接続されたものとして表すことができ、第1
0図(C)ではこの内部インピーダンスを信号源に並列
に、第10図(d)では信号源に直列に接続したもので
ある。
In addition, FIG. 10(C) is an equivalent circuit of a voltage amplification type detector,
FIG. 10 (Company) is an equivalent circuit of a current-voltage conversion type. The detector 31 has an internal resistance Rd and a stray capacitance T connected to the signal source is.
, can be represented as connected in parallel, and the first
In FIG. 10(C), this internal impedance is connected in parallel to the signal source, and in FIG. 10(d), this internal impedance is connected in series with the signal source.

電圧変換型においては、検出器に負荷抵抗RLを接続し
ているのみで増幅器32に対して外部抵抗を接続してお
らず、そのため検出器の内部抵抗と容量で決まる狭い帯
域幅を有し、ジョンソンノイズは比較的少ないが、受光
した時の電荷の蓄積時間は内部インピーダンスで決まる
時定数しかとれないため短く、そのため感度を大きくと
れないという欠点がある。
In the voltage conversion type, only the load resistor RL is connected to the detector, and no external resistance is connected to the amplifier 32, so it has a narrow bandwidth determined by the internal resistance and capacitance of the detector. Johnson noise is relatively small, but the charge accumulation time when light is received is short because the time constant determined by the internal impedance is short, so the drawback is that high sensitivity cannot be achieved.

一方、電流−電圧変換型においては、増幅器に帰還抵抗
R3帰還容量CLを並列接続して積分回路を形成したい
るため、外部抵抗と容量とで決まる広い帯域幅を有し、
検出器の内部抵抗と増幅器の外部抵抗両者のジョンソン
ノイズが存在してS/N比が低下してしまうという問題
があるが受光した時の電荷の蓄積時間を大きくとること
ができるため感度を大きくすることが可能である。
On the other hand, in the current-voltage conversion type, the feedback resistor R3 and the feedback capacitor CL are connected in parallel to the amplifier to form an integrating circuit, so it has a wide bandwidth determined by the external resistance and capacitance.
Although there is a problem that the S/N ratio decreases due to the presence of Johnson noise from both the internal resistance of the detector and the external resistance of the amplifier, the sensitivity can be increased because it allows a longer time for the charge to accumulate when light is received. It is possible to do so.

例えば、第11図に示すように増幅器43に帰還インピ
ーダンス44を接続して積分回路を構成し、受光素子4
1で検出した信号を差動増幅器42、増幅器43で読み
出す電流−電圧変換型について実際に測定したところ、
第12図に示すような結果が得られた。
For example, as shown in FIG. 11, a feedback impedance 44 is connected to an amplifier 43 to form an integrating circuit, and the light receiving element 4
When we actually measured the current-voltage conversion type in which the signal detected in step 1 is read out by the differential amplifier 42 and amplifier 43,
The results shown in FIG. 12 were obtained.

図から分かるように、出力には相当のノイズがのってお
り、S/N比が低いことが分かる。このように従来の検
出装置では極微弱光の検出を高精度に行うことができな
かった。
As can be seen from the figure, there is considerable noise in the output, indicating that the S/N ratio is low. As described above, conventional detection devices have been unable to detect extremely weak light with high precision.

本発明は上記課題を解決するためのもので、検出器に対
する一切の負荷抵抗を取り除き、素子の内部インピーダ
ンスに現れる電圧を高インピーダンス低ノイズのFET
増幅器により直接読み出すとともに、リセット用FET
を設けて蓄積電荷を適当な周期で放電させることにより
高感度、低ノイズで光検出を行うことができる同期電荷
蓄積型光検出装置を提供することを目的とする。
The present invention is intended to solve the above problems, and eliminates all load resistance for the detector and converts the voltage appearing in the internal impedance of the element into a high-impedance, low-noise FET.
Direct reading by amplifier and reset FET
It is an object of the present invention to provide a synchronous charge accumulation type photodetection device that can perform photodetection with high sensitivity and low noise by discharging accumulated charges at an appropriate period.

〔課題を解決するための手段〕[Means to solve the problem]

そのために本発明は、内部インピーダンスが高く、暗電
流が極めて少なく、かつ負荷抵抗を接続しない半導体受
光素子を外部抵抗を接続しない電圧増幅型前置増幅器に
より読み出すようにした光検出装置であって、受光素子
のカソードがドレイン端子に接続され、ゲートに印加さ
れるリセットパルスによりON/OFF制御されて受光
素子の浮遊容量に蓄積された電荷を放電させるリセット
用FETを設けたこと、またこのような検出装置を用い
、チョッパーを介して入射光を検出し、チョッパーの開
閉周期に同期したリセット信号でリセット用FETをO
N10 F F動作させ、受光素子の電荷を放電させる
とともに、チョッパーの開閉に同期して加減算カウンタ
を動作させ、チョッパー開の時と閉の時の信号を差し引
いてバックグラウンドを除去するようにしたことを特徴
とする。
To this end, the present invention provides a photodetection device that has high internal impedance, extremely low dark current, and reads out a semiconductor light-receiving element to which no load resistance is connected using a voltage amplification type preamplifier to which no external resistance is connected. The cathode of the light-receiving element is connected to the drain terminal, and a reset FET is provided which is ON/OFF controlled by a reset pulse applied to the gate to discharge the charge accumulated in the stray capacitance of the light-receiving element. A detection device is used to detect the incident light through the chopper, and the reset FET is turned on with a reset signal synchronized with the opening/closing cycle of the chopper.
N10 F F is operated to discharge the charge in the light receiving element, and an addition/subtraction counter is operated in synchronization with the opening and closing of the chopper, and the background is removed by subtracting the signals when the chopper is open and closed. It is characterized by

〔作用〕[Effect]

本発明の光検出装置は、2つのFETと半導体検出素子
から構成し、高インピーダンスの半導体検出素子の浮遊
容量に蓄積された電荷を読み出し用のFETで直接読み
出すとともに、リセット用FETのON/OFFにより
蓄積電荷を放電して初期状態に戻すようにしたもので、
帯域幅は内部インピーダンスだけで決まり、内部インピ
ーダンスが極めて大きく、暗電流の小さい半導体検出素
子を用いることにより、電荷蓄積のり二アリティがよく
、感度を増大することができるとともに、外部抵抗を一
切接続しないため、S/N比を大幅に向上することがで
き、かつ適当な周期でリセットをかけることにより、測
定対象の周期性に応じた検出を行うことが可能となる。
The photodetection device of the present invention is composed of two FETs and a semiconductor detection element, and the readout FET directly reads out the charge accumulated in the stray capacitance of the high impedance semiconductor detection element, and the reset FET is turned ON/OFF. It is designed to discharge the accumulated charge and return to the initial state.
Bandwidth is determined only by internal impedance, and by using a semiconductor detection element with extremely high internal impedance and low dark current, charge storage linearity is good, sensitivity can be increased, and no external resistor is connected. Therefore, the S/N ratio can be greatly improved, and by applying reset at appropriate intervals, it becomes possible to perform detection according to the periodicity of the measurement target.

〔実施例〕〔Example〕

以下、本発明の詳細な説明する。 The present invention will be explained in detail below.

第1図は本発明の検出装置の構成を示す図、第2図は電
荷蓄積の原理を説明するための図、第3図は信号検出に
おける波形図、第4図は検出装置の一例を示す図、第5
図は検出器の取り付は構造を示す図である。図中、1は
受光素子、2はリッセト用FET、3は読み出し用FE
T、4は抵抗、5は差動増幅器、6はツェナーダイオー
ド、7は抵抗素子、8は演算増幅器、9はローパスフィ
ルタ、IOは検出器、11はセンサ、12はマウント装
置、13.14はFET、15は抵抗素子、16は金属
ブロック、17はウィンド、18は端子である。
Fig. 1 is a diagram showing the configuration of the detection device of the present invention, Fig. 2 is a diagram for explaining the principle of charge accumulation, Fig. 3 is a waveform diagram in signal detection, and Fig. 4 is an example of the detection device. Figure, 5th
The figure shows the mounting structure of the detector. In the figure, 1 is a light receiving element, 2 is a reset FET, and 3 is a readout FE.
T, 4 is a resistor, 5 is a differential amplifier, 6 is a Zener diode, 7 is a resistive element, 8 is an operational amplifier, 9 is a low-pass filter, IO is a detector, 11 is a sensor, 12 is a mounting device, 13.14 is a FET, 15 is a resistance element, 16 is a metal block, 17 is a window, and 18 is a terminal.

本発明の受光素子はSi、Ge、In、GaAs、In
GaAsP等の半導体検出素子からなり、内部インピー
ダンスが高く、かつ暗電流が極めて少ない素子からなっ
ており、第5図に示すように、マウント装置12に取り
付けてウィンド17を通して入射する光を検出するよう
になっている。検出信号はFET13.14、抵抗素子
15等からなる前置増幅器を介して出力端子18側から
取り出せるようになっている。なお、FET13.14
は液体窒素で冷却すると共に、検出素子は液体窒素また
は液体ヘリウムで冷却して低ノイズ化を図っている。
The light receiving element of the present invention is Si, Ge, In, GaAs, In
It is made of a semiconductor detection element such as GaAsP, which has high internal impedance and extremely low dark current.As shown in FIG. It has become. The detection signal can be taken out from the output terminal 18 side via a preamplifier consisting of FETs 13 and 14, a resistive element 15, and the like. In addition, FET13.14
is cooled with liquid nitrogen, and the detection element is cooled with liquid nitrogen or liquid helium to reduce noise.

第1図において、受光素子1は内部インピーダンスが高
く暗電流が極めて少ないフォトダイオードからなり、こ
れに逆バイアス電圧を印加して通常はOFF状態にして
おく。受光素子のカソード端子はリセット用FET2の
ドレイン、読み出し用FET3のゲートに接続されてい
る。
In FIG. 1, a light receiving element 1 is comprised of a photodiode with high internal impedance and extremely low dark current, and is normally turned off by applying a reverse bias voltage to it. The cathode terminal of the light receiving element is connected to the drain of the reset FET 2 and the gate of the read FET 3.

第2図(a)に示すように、FET2のゲートには+I
Vと一3Vが印加され、+IVt”OFF。
As shown in Figure 2(a), +I is applied to the gate of FET2.
V and -3V are applied, +IVt"OFF.

3VでONするようになっている。FET2のゲートと
ドレイン間には仮想的な容量Cが存在し、第2図(b)
に示すようにONパルス(−3V)を人力すると、容量
Cに正の電荷が溜まり、ドレイン・ソース間が導通する
ので、受光素子の浮遊容量に蓄積されていた電荷がアー
ス側に流れる。
It is designed to turn on at 3V. There is a virtual capacitance C between the gate and drain of FET2, as shown in Figure 2(b).
As shown in the figure, when an ON pulse (-3V) is applied manually, positive charge accumulates in the capacitor C, and conduction occurs between the drain and source, so the charge accumulated in the stray capacitance of the light-receiving element flows to the ground side.

第2図(C)に示すように、OFFパルス(+IV)を
人力すると、容量Cに正の電圧がかかるため、ここに溜
まっていた正の電荷が吐き出され、ドレイン・ソース間
はOFF状態となる。本発明の検出装置では受光素子1
に何ら負荷抵抗を接続しないため、ジョンソンノイズは
検出器の内部抵抗だけで決まり、またリセットパルスを
かけない限り、電荷は蓄積されるので、蓄積時間が長く
とれ、高感度の検出が可能となる。
As shown in Figure 2 (C), when an OFF pulse (+IV) is applied manually, a positive voltage is applied to the capacitor C, so the positive charge accumulated here is discharged, and the drain-source is in the OFF state. Become. In the detection device of the present invention, the light receiving element 1
Since no load resistance is connected to the sensor, Johnson noise is determined only by the internal resistance of the detector, and the charge will accumulate unless a reset pulse is applied, allowing for a long accumulation time and enabling highly sensitive detection. .

第1図に示すように、FET3をソースフォロアーとし
て動作させて読み出すと、出力vourは第3図(a)
に示すように変化し、ON時間の最初と最後のタイミン
グでサンプリングパルス(第3図う))によりサンプリ
ングし、出力V1、■2を検出しく第3図(C))、V
、とV2の差により受光量を求めることができる 第4図は第1図に示した本発明の検出装置の実際の回路
例を示す図である。一方の入力端子にツェナーダイオー
ド6から定電圧が人力され、他方にフォトダイオードの
蓄積電圧が人力されるソースフォロアー3で読み出した
信号を差動増幅器5、演算増幅器8で増幅してローパス
フィルタ9により所定帯域の信号を検出することができ
る。
As shown in Figure 1, when FET3 is operated as a source follower and read out, the output vour is as shown in Figure 3(a).
The voltage changes as shown in Figure 3 (C)), V
, and V2. FIG. 4 is a diagram showing an actual circuit example of the detection device of the present invention shown in FIG. 1. A constant voltage is input from the Zener diode 6 to one input terminal, and the accumulated voltage of the photodiode is input to the other input terminal.The signal read out by the source follower 3 is amplified by the differential amplifier 5 and the operational amplifier 8, and then filtered by the low-pass filter 9. Signals in a predetermined band can be detected.

第6図は本発明の検出装置により所定の周期でON/O
FFさせた時の検出信号を示す図である。
FIG. 6 shows the ON/OFF state at a predetermined period by the detection device of the present invention.
It is a figure which shows the detection signal when it is made to turn FF.

第6図(a)では10秒周期で検出素子をリセットし、
検出素子への光のON/OFFをリセット周期の数倍に
設定した時の信号波形であり、その詳細は第6図(b)
に示すように、極めてノイズの少ない、リニアリティの
良好な信号出力が得られる。
In Fig. 6(a), the detection element is reset at a cycle of 10 seconds,
This is the signal waveform when the ON/OFF of light to the detection element is set to several times the reset period, and its details are shown in Figure 6 (b).
As shown in the figure, a signal output with extremely low noise and good linearity can be obtained.

なお、第6図(C)は光源をOFFした時の出力で、暗
電流を示している。バックグラウンドは時間的に一定で
あると考えられるので第6図ら)の値から第6図(C)
の値を差し引くことによりバックグラウンドを除去した
信号を検出することができる。
Note that FIG. 6(C) shows the output when the light source is turned off, and shows the dark current. Since the background is considered to be constant over time, Figure 6 (C) is obtained from the values in Figure 6, etc.
By subtracting the value of , a signal from which the background has been removed can be detected.

第7図は本発明と従来の電流−電圧変換型検出器につい
て、S/N=1となる光電流を積分時間の関数として表
したもので、例えば積分時間が同じだとすると、本発明
により1桁程度光電流が小さくても十分検出可能である
ことが分かる。
FIG. 7 shows the photocurrent with S/N=1 as a function of integration time for the current-voltage conversion type detector of the present invention and the conventional current-voltage conversion type detector. It can be seen that sufficient detection is possible even if the photocurrent is small.

第8図は本発明の検出器を用いた検出装置の一実施例を
示す図、第9図は波形図である。
FIG. 8 is a diagram showing an embodiment of a detection device using the detector of the present invention, and FIG. 9 is a waveform diagram.

図において、光源21からの極微弱な入射光をチョッパ
ー22によりチョピングして本発明の検出器23により
検出する。この時チョッパー22の切り替え信号に同期
して制御回路26よりリセット信号を出して検出器23
をリセットする。同時に、チョッパー22の切り替え信
号に同期して制御回路26から出力されるゲート制御信
号により加減算カウンタ35を制御し、検出されてA/
D変換された信号を、光源がONしているときは加算、
光源がOFFしたときの暗電流は減算して結果をデジタ
ルプリンタ/アナログ記録計27で出力する。
In the figure, extremely weak incident light from a light source 21 is chopped by a chopper 22 and detected by a detector 23 of the present invention. At this time, a reset signal is output from the control circuit 26 in synchronization with the switching signal of the chopper 22, and the detector 23
Reset. At the same time, the addition/subtraction counter 35 is controlled by a gate control signal output from the control circuit 26 in synchronization with the switching signal of the chopper 22, and the
Add the D-converted signals when the light source is on,
The dark current when the light source is turned off is subtracted and the result is output by a digital printer/analog recorder 27.

第9図(a)に示すようにチョッパーが開いている間に
は、信号SとノイズNの合計の出力が得られ、チョッパ
ーが閉じている期間にはバックグラウンドのノイズNが
得られたとする。第9図ら)に示すリセット信号の印加
周期でS十Nのそれぞれの信号が積分され、第9図(C
)に示すようにチョッパー開の間は加算ゲート信号によ
り加算され、チョッパーが閉じている間は第9図(d)
に示すように、減算ゲート信号により減算されるように
加減算カウンタ35の制御が行われる。この結果、ノイ
ズは全ての期間にわたって一定に現れる性質があるので
、加減算カウンタ35の出力からはノイズを除去し、信
号Sのみを検出することができる。
As shown in Fig. 9(a), while the chopper is open, the sum of the signal S and the noise N is obtained, and while the chopper is closed, the background noise N is obtained. . Each signal of S and N is integrated at the application period of the reset signal shown in Fig. 9 (C, etc.).
), while the chopper is open, addition is performed by the addition gate signal, and while the chopper is closed, the addition is performed by the addition gate signal, as shown in Figure 9 (d).
As shown in FIG. 3, the addition/subtraction counter 35 is controlled so as to be subtracted by the subtraction gate signal. As a result, since noise has the property of appearing constantly over all periods, it is possible to remove noise from the output of the addition/subtraction counter 35 and detect only the signal S.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、外部抵抗を接続しない電
圧増幅型プリアンプで内部インピーダンスが高く、暗電
流が極めて少ない負荷抵抗を接続しない受光素子の出力
を読み出すことにより、蓄積時間を長くして高感度化を
図り、S/N比を向上させて低雑音高感度で光の極微弱
光の検出を行うことができ、また、所定のタイミングで
蓄積電荷を放電させるようにしたので、さまざまな測定
対象に応じた周期で極微弱光の検出を行うことが可能と
なる。
As described above, according to the present invention, a voltage amplifying preamplifier that does not connect an external resistor has high internal impedance, and dark current is extremely low.By reading out the output of a light receiving element that does not connect a load resistor, the accumulation time can be increased. By increasing the sensitivity and improving the S/N ratio, it is possible to detect extremely weak light with low noise and high sensitivity.In addition, the accumulated charge is discharged at a predetermined timing, so it can be used in various ways. It becomes possible to detect extremely weak light at a periodicity that corresponds to the measurement target.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の検出装置の構成を示す図、第2図は電
荷蓄積の原理を説明するための図、第3図は信号検出に
おける波形図、第4図は検出装置の一例を示す図、第5
図は検出器の取り付は構造を示す図、第6図は本発明の
検出装置により所定の周期でON10 F Fさせた時
の検出信号を示す図、第7図は本発明と従来例の電流−
電圧変換型について、S/N=1となる光電流を積分時
間の関数として表した図、第8図は本発明の一実施例を
示す図、第9図は波形図、第10図は従来の検出装置の
構成を示す図、第11図は従来の電圧−電流変換型検出
装置の構成を示す図、第12図は第11図の装置による
検出結果を示す図である。 1・・・フォトダイオード、2・・・リッセト用FET
。 3・・・読み出し用FET、12・・・マウント装置、
13.14・・・FET0 出  願  人  新技術開発事業団 (外2名)
Fig. 1 is a diagram showing the configuration of the detection device of the present invention, Fig. 2 is a diagram for explaining the principle of charge accumulation, Fig. 3 is a waveform diagram in signal detection, and Fig. 4 is an example of the detection device. Figure, 5th
The figure shows the mounting structure of the detector, Figure 6 shows the detection signal when the detection device of the present invention turns on 10 F F at a predetermined cycle, and Figure 7 shows the difference between the present invention and the conventional example. Current -
For the voltage conversion type, the photocurrent for S/N = 1 is shown as a function of integration time. Figure 8 is a diagram showing an embodiment of the present invention, Figure 9 is a waveform diagram, and Figure 10 is a conventional diagram. FIG. 11 is a diagram showing the configuration of a conventional voltage-current conversion type detection device, and FIG. 12 is a diagram showing detection results by the device of FIG. 11. 1... Photodiode, 2... FET for reset
. 3... Readout FET, 12... Mounting device,
13.14...FET0 Applicant New Technology Development Corporation (2 others)

Claims (4)

【特許請求の範囲】[Claims] (1)内部インピーダンスが高く、暗電流が極めて少な
く、かつ負荷抵抗を接続しない半導体受光素子を外部抵
抗を接続しない電圧増幅型前置増幅器により読み出すよ
うにした光検出装置であって、受光素子のカソードがド
レイン端子に接続され、ゲートに印加されるリセットパ
ルスによりON/OFF制御されて受光素子の浮遊容量
に蓄積された電荷を放電させるリセット用FETを設け
たことを特徴とする同期電荷蓄積型光検出装置。
(1) A photodetection device that has high internal impedance, extremely low dark current, and reads out a semiconductor photodetector without connecting a load resistor using a voltage amplification type preamplifier without connecting an external resistor. A synchronous charge storage type characterized by having a reset FET whose cathode is connected to the drain terminal and which is ON/OFF controlled by a reset pulse applied to the gate to discharge the charge accumulated in the stray capacitance of the light receiving element. Photodetection device.
(2)請求項1記載の検出装置で、チョッパーを介して
入射光を検出し、チョッパーの開閉周期に同期したリセ
ット信号でリセット用FETをON/OFF動作させ、
受光素子の電荷を放電させるとともに、チョッパーの開
閉に同期して加減算カウンタを動作させ、チョッパー開
の時と閉の時の信号を差し引いてバックグラウンドを除
去するようにしたことを特徴とする同期電荷蓄積型光検
出装置。
(2) The detection device according to claim 1, which detects the incident light through the chopper and turns the reset FET ON/OFF using a reset signal synchronized with the opening/closing cycle of the chopper;
The synchronous charge is characterized by discharging the charge in the light receiving element, operating an addition/subtraction counter in synchronization with the opening and closing of the chopper, and subtracting the signals when the chopper is open and closed to remove the background. Storage type photodetector.
(3)受光素子がInGaAs、InGaAsP、In
Sb、InAs、Siからなる検出素子であることを特
徴とする請求項1記載の光検出装置。
(3) The light receiving element is made of InGaAs, InGaAsP, In
2. The photodetection device according to claim 1, wherein the detection element is made of Sb, InAs, or Si.
(4)リセット用FETと読み出し用FETを液体窒素
で冷却すると共に、受光素子を液体窒素または液体ヘリ
ウムで冷却することを特徴とする請求項1記載の光検出
装置。
(4) The photodetection device according to claim 1, wherein the reset FET and readout FET are cooled with liquid nitrogen, and the light receiving element is cooled with liquid nitrogen or liquid helium.
JP25003589A 1989-09-26 1989-09-26 Synchronous charge accumulating type photodetector Granted JPH03111724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25003589A JPH03111724A (en) 1989-09-26 1989-09-26 Synchronous charge accumulating type photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25003589A JPH03111724A (en) 1989-09-26 1989-09-26 Synchronous charge accumulating type photodetector

Publications (2)

Publication Number Publication Date
JPH03111724A true JPH03111724A (en) 1991-05-13
JPH0574012B2 JPH0574012B2 (en) 1993-10-15

Family

ID=17201862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25003589A Granted JPH03111724A (en) 1989-09-26 1989-09-26 Synchronous charge accumulating type photodetector

Country Status (1)

Country Link
JP (1) JPH03111724A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128821A (en) * 1981-02-04 1982-08-10 Nec Corp Intergrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128821A (en) * 1981-02-04 1982-08-10 Nec Corp Intergrated circuit device

Also Published As

Publication number Publication date
JPH0574012B2 (en) 1993-10-15

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