JPH0311171B2 - - Google Patents
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- Publication number
- JPH0311171B2 JPH0311171B2 JP59057683A JP5768384A JPH0311171B2 JP H0311171 B2 JPH0311171 B2 JP H0311171B2 JP 59057683 A JP59057683 A JP 59057683A JP 5768384 A JP5768384 A JP 5768384A JP H0311171 B2 JPH0311171 B2 JP H0311171B2
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- Prior art keywords
- voltage
- differential amplifier
- capacitor
- input
- transistor
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- Expired - Lifetime
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- 238000001514 detection method Methods 0.000 claims description 61
- 239000003990 capacitor Substances 0.000 claims description 45
- 230000005856 abnormality Effects 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 10
- 230000010365 information processing Effects 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 6
- 230000007257 malfunction Effects 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- Measurement Of Current Or Voltage (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は、普通のオフイスに設置される情報処
理装置等に、商用の交流電源を整流した直流電圧
を供給する電源装置の停電検出回路に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a power failure detection circuit for a power supply device that supplies DC voltage obtained by rectifying a commercial AC power supply to information processing equipment installed in ordinary offices. .
(b) 技術の背景
近年、情報処理装置は小形化が進み専用の計算
機室だけでなく普通のオフイスにも設置されるよ
うになつて来た。計算機室に設置される場合は殆
ど専用電源、例えば定電圧で定周波の交流電源が
用意され、該交流電源の出力を整流した直流電圧
を出力する電源装置から情報処理装置に安定した
直流電圧が供給され、停電、瞬断、電圧低下等が
生じないようになつている。しかし、オフイスに
設置される情報処理装置には専用電源が無く、入
力の商用の交流電源をそのまま整流した直流電圧
を使用する場合が多く、このため、商用電源の停
電、瞬断、電圧低下等が生じると情報処理装置が
誤動作してしまうことがある。そこで、其の停
電、瞬断、電圧低下等を検出した停電検出信号を
情報処理装置の割り込み信号として所謂リセツト
処理をして該装置のデータの保護を行つている。(b) Background of the technology In recent years, information processing equipment has become smaller and more compact, and it has come to be installed not only in dedicated computer rooms but also in ordinary offices. When installed in a computer room, a dedicated power supply such as a constant voltage, constant frequency AC power supply is usually prepared, and a stable DC voltage is supplied to the information processing equipment from a power supply device that outputs a DC voltage obtained by rectifying the output of the AC power supply. The system is designed to prevent power outages, instantaneous interruptions, voltage drops, etc. However, information processing equipment installed in offices does not have a dedicated power supply and often uses DC voltage that is rectified from the input commercial AC power supply, resulting in problems such as commercial power outages, instantaneous interruptions, and voltage drops. If this occurs, the information processing device may malfunction. Therefore, a power outage detection signal that detects a power outage, instantaneous interruption, voltage drop, etc. is used as an interrupt signal for the information processing device to perform a so-called reset process to protect the data in the device.
装置の電源の停電検出回路としては、停電時の
検出信号の送出のみならず、正常に復電した時も
負荷装置に誤動作をさせない事が必要である。 The power failure detection circuit for the device's power supply not only needs to send out a detection signal during a power outage, but also needs to prevent the load device from malfunctioning even when the power is restored normally.
(c) 従来技術と問題点
この電源装置の従来の停電検出回路について以
下に説明する。第１図、第２図、第４図、第６図
は、従来の第１、第２、第３、第４の停電検出回
路の構成を示すブロツク図であり、第３図、第５
図、第７図、第８図は、それら従来例の動作を説
明するための電圧波形図である。図において、１
は整流回路、２は抵抗、３はホトカプラ、４は一
次側ダイオード、５は二次側トランジスタ、６は
駆動用トランジスタ、７は継電器、８は検出信号
の出力手段の接点、ａは交流入力端、ｂは検出信
号の出力端を示す。第１の従来例の構成を示す第
１図において、交流入力端ａより入力する商用電
源の交流電圧を整流回路１で整流し、整流して得
た直流電圧を、抵抗２を通してホトカプラ３の一
次側ダイオード４に印加する。(c) Prior Art and Problems The conventional power failure detection circuit of this power supply device will be explained below. 1, 2, 4, and 6 are block diagrams showing the configurations of conventional first, second, third, and fourth power failure detection circuits, and FIGS.
7 and 8 are voltage waveform diagrams for explaining the operations of these conventional examples. In the figure, 1
is a rectifier circuit, 2 is a resistor, 3 is a photocoupler, 4 is a primary side diode, 5 is a secondary side transistor, 6 is a driving transistor, 7 is a relay, 8 is a contact of the detection signal output means, and a is an AC input terminal , b indicates the output end of the detection signal. In FIG. 1 showing the configuration of a first conventional example, a rectifier circuit 1 rectifies the AC voltage of a commercial power supply input from an AC input terminal a, and the DC voltage obtained by rectification is passed through a resistor 2 to the primary of a photocoupler 3. side diode 4.
交流入力端ａの交流電圧が正常で、ホトカプラ
３への入力の直流電圧が正常の時は、ホトカプラ
３の一次側ダイオード４がオンして二次側トラン
ジスタ５もオンする。すると、継電器７の駆動用
のトランジスタ６がオンして継電器７が動作し、
検出接点８が開く。交流入力端ａの交流電圧が停
電又は瞬断すると、ホトカプラ３の一次側ダイオ
ード４がオフし二次側トランジスタ５もオフして
継電器７が非動作となり、継電器７の検出接点８
が閉じて、検出信号の出力端ｂより装置側（図示
せず）に割り込み信号として停電検出信号を送出
していた。また、継電器７を使用せずに駆動用ト
ランジスタ６のエミツタ―コレクタ間の電圧を検
出して停電等の検出信号として場合もある。この
第１の従来例の停電検出回路は、入力の交流電圧
が低下した場合、例えば通常はAC100Vの電圧が
供給されていて、何等かの原因で50Vまで低下し
た場合でも、ホトカプラ３が正常に動作していれ
ば、その電圧低下を検出することが出来ない。し
かし、情報処理装置の電源装置は、その入力の交
流電圧が50Vになれば、整流した直流電圧V1は
大きく低下してしまい、情報処理装置は誤動作
し、装置データが保護されなくなるという欠点を
有する。上述の第１の従来例の欠点は、第２図に
示す如く、入力の交流電源を整流する整流回路１
からの直流電圧V1を、一次側ダイオード４と二
次側トランジスタ５からなるホトカプラ３の一次
側ダイオード４と該ダイオードに直列接続した定
電圧ダイオード１１とを通して入力し、前記入力
電圧V1の低下を含む停電の場合は、該定電圧ダ
イオード１１のオン／オフによる該一次側ダイオ
ード４のオン／オフにより前記ホトカプラ３の二
次側トランジスタ５がオン／オフして、該二次側
トランジスタ５のオフにより、出力接点８が停電
検出信号を送出するように構成した第２の従来例
の停電検出回路によつて達成された。然しなが
ら、この第２の従来例も、定電圧ダイオード１１
をホトカプラ３の一次側ダイオード４と直列接続
しているため、ホトカプラ３と抵抗２に加わる入
力電圧V1は、第３図の電圧波形図に示す如く、
定電圧ダイオード１１のツエナー電圧をVZDとし
た場合、入力電圧V1からツエナー電圧VZDを差引
いた斜線部Ａの歪んだ波形の電圧が、ホトカプラ
３の一次側ダイオード４の入力電圧となる。この
歪んだ波形の入力電圧では、ホトカプラ３の二次
側トランジスタ５への伝達率によつては、該トラ
ンジスタのコレクタに接続された継電器７を動作
させる事が出来なくなる。何となれば、ホトカプ
ラ３の一次側ダイオード４は、最低でも10数mA
の電流を必要とし、定電圧ダイオード１１による
電圧損失が大となるからである。従つて、この定
電圧ダイオード１１の挿入によつて、入力電圧
V1の低下を前記の第１の従来例の回路よりも敏
感に検出するとは言え、継電器７を動作させる事
が出来なければ停電検出回路として意味が無いと
いう欠点を有している。この第２の従来例の欠点
を改善するため、第４図に示す如く、前記ホトカ
プラ３の一次側ダイオード４を該ダイオードをコ
レクタに接続したトランジスタ１２によつてオ
ン／オフさせるように、該トランジスタ１２のベ
ースと前記一次側ダイオード４との間に定電圧ダ
イオード１３を直列抵抗１４と共に挿入して、前
記一次側ダイオード４と前記定電圧ダイオード１
３との接続点と前記トランジスタ１２のエミツタ
との間に前記入力電圧V1を供給するよう構成し、
定電圧ダイオード１３に流れる電流をトランジス
タ１２の１／hfeに小さくし、定電圧ダイオード
１３の電圧損失を大幅に低減させた第３の従来例
の停電検出回路によつて改善された。即ちホトカ
プラ３の一次側ダイオード４と抵抗２に加わる電
圧は、第５図の電圧波形図の斜線部Ｂの如く大き
くなり、ホトカプラ３の二次側への伝達率の経年
変化等を考慮しても充分な電流を流すことが出来
て安定な停電検出回路が得られる。然しながら、
この第４図の第３発明の従来例も、入力電圧V1
の異常が起きると直ちに検出してしまい、例えば
負荷の装置が入力電源の停電から100msec間は出
力電圧を保持できるものとすれば、入力電源の異
常の持続時間が100msec以下の場合は、装置は正
常動作をするため検出信号を送出する必要がな
く、入力異常が起きて直ぐ検出信号を送出する事
は、却つて悪いという欠点を有する。この第３の
従来例の欠点を改善するため、第６図に示す如
く、前記ホトカプラ３の二次側トランジスタ５の
コレクタに充電用のコンデンサ１５を接続し、前
記ホトカプラの二次側トランジスタ５がオフして
前記コンデンサ１５を抵抗１６を通して充電し、
前記コンデンサ１５の充電電圧V2が所定の基準
電圧V3を越えた時に差動増幅器１７が動作し、
該差動増幅器の動作により、入力異常が起きた場
合、コンデンサ１５と抵抗１６の時定数により任
意に選定できる一定時間だけ遅延させて、前記出
力手段８が停電検出信号を送出するよう構成した
第６図の第４の従来例の停電検出回路によつて改
善された。即ち、第６図の充電用のコンデンサ１
５の充電電圧V2は、第７図の電圧波形図に示す
如く、整流回路１からの直流の入力電圧が正常の
場合は、ホトカプラ３のオン／オフにより、コン
デンサ１５と抵抗１６の時定数により定まる一定
時間「PIオフ」で上昇し、同じ時間「PIオン」
で下降する電圧V2の波形となり、コンデンサ１
５の充電電圧V2は、差動増幅器１７の基準電圧
V3より低い電圧に抑えられているため、差動増
幅器１７の出力は“Ｈ”レベルとなり、駆動トラ
ンジスタ６がオンし、継電器７が動作するため、
検出接点８は開放となる。入力の交流電源に異常
が起きて整流回路１からの直流の入力電圧が異常
の場合は、ホトカプラ３の二次側トランジスタ５
がオフの状態を続けるため、第８図の電圧波形図
の如く、コンデンサ１５の充電電圧V2は、抵抗
１６とコンデンサ１５による充電カーブにより上
昇し、差動増幅器１７の基準電圧V3を越えると
該差動増幅器１７の動作が反転し其の出力が
“Ｌ”レベルとなり、駆動トランジスタ６と継電
器７がオフ状態となり、信号出力端ｂより停電検
出信号を送出する。抵抗２０、ダイオード２１、
抵抗２２は、コンデンサ１５の充電電圧V2が図
の検出点Ｃに達した時に、基準電圧V3の値を下
げるよう所謂ヒステリシスを掛けている。以上の
ように、コンデンサ１５と抵抗１６の充電カーブ
により、入力異常時の検出信号の送出を任意に遅
延させることが出来るため、負荷の装置の動作に
合つた停電検出回路となつた。然しながら、この
第４の従来例の停電検出回路は、入力の交流電源
が異常状態から正常に復しホトカプラ３への直流
の入力電圧V1が正常に復帰した場合は、直ちに
異常検出信号の送出を解除してしまう。そのた
め、負荷の装置の動作が完全に立ち上がつていな
い場合は該装置が誤動作してしまうという難点が
ある。 When the AC voltage at the AC input terminal a is normal and the DC voltage input to the photocoupler 3 is normal, the primary side diode 4 of the photocoupler 3 is turned on and the secondary side transistor 5 is also turned on. Then, the transistor 6 for driving the relay 7 turns on, and the relay 7 operates.
Detection contact 8 opens. When the AC voltage at the AC input terminal a is interrupted or momentarily interrupted, the primary side diode 4 of the photocoupler 3 is turned off, the secondary side transistor 5 is also turned off, and the relay 7 becomes inoperable, and the detection contact 8 of the relay 7 is turned off.
was closed, and a power failure detection signal was sent as an interrupt signal to the device (not shown) from the detection signal output terminal b. Furthermore, the voltage between the emitter and collector of the driving transistor 6 may be detected as a detection signal for a power outage, etc., without using the relay 7. The power failure detection circuit of this first conventional example prevents the photocoupler 3 from operating normally even if the input AC voltage drops, for example, even if the voltage that is normally supplied is 100V AC and drops to 50V for some reason. If it is operating, the voltage drop cannot be detected. However, the power supply device for information processing equipment has the drawback that if the input AC voltage reaches 50V, the rectified DC voltage V 1 will drop significantly, causing the information processing equipment to malfunction and the equipment data to be unprotected. have The drawback of the first conventional example described above is that, as shown in FIG.
A DC voltage V 1 from the source is input through the primary diode 4 of the photocoupler 3, which is composed of a primary diode 4 and a secondary transistor 5, and a constant voltage diode 11 connected in series with the diode, and the input voltage V 1 decreases. In the case of a power outage, the secondary side transistor 5 of the photocoupler 3 is turned on/off due to the on/off of the primary side diode 4 due to the on/off of the constant voltage diode 11, and the secondary side transistor 5 of the photocoupler 3 is turned on/off. This was achieved by the second conventional power failure detection circuit configured such that the output contact 8 sends out a power failure detection signal when turned off. However, this second conventional example also has a constant voltage diode 11.
is connected in series with the primary side diode 4 of the photocoupler 3, so the input voltage V1 applied to the photocoupler 3 and the resistor 2 is as shown in the voltage waveform diagram of FIG.
When the Zener voltage of the constant voltage diode 11 is V ZD , the voltage of the distorted waveform in the shaded area A obtained by subtracting the Zener voltage V ZD from the input voltage V 1 becomes the input voltage of the primary side diode 4 of the photocoupler 3 . With the input voltage having this distorted waveform, depending on the transmission rate of the photocoupler 3 to the secondary side transistor 5, it becomes impossible to operate the relay 7 connected to the collector of the transistor. After all, the primary side diode 4 of the photocoupler 3 is at least 10 mA
This is because the voltage loss caused by the constant voltage diode 11 becomes large. Therefore, by inserting this voltage regulator diode 11, the input voltage
Although this circuit detects a drop in V 1 more sensitively than the first conventional circuit, it has the disadvantage that it is meaningless as a power failure detection circuit unless the relay 7 can be operated. In order to improve the drawbacks of the second conventional example, as shown in FIG. A voltage regulator diode 13 is inserted together with a series resistor 14 between the base of the primary diode 12 and the primary diode 4.
configured to supply the input voltage V 1 between the connection point with 3 and the emitter of the transistor 12,
This is improved by the third conventional power failure detection circuit in which the current flowing through the constant voltage diode 13 is reduced to 1/h fe of the transistor 12, and the voltage loss of the constant voltage diode 13 is significantly reduced. In other words, the voltage applied to the primary side diode 4 and resistor 2 of the photocoupler 3 increases as shown in the shaded area B of the voltage waveform diagram in FIG. A stable power failure detection circuit can be obtained by allowing sufficient current to flow. However,
The conventional example of the third invention shown in FIG. 4 also has an input voltage V 1
For example, if a load device is able to maintain the output voltage for 100 msec after an input power failure, if the duration of the input power abnormality is 100 msec or less, the device will detect the abnormality as soon as it occurs. It is not necessary to send out a detection signal for normal operation, and sending out a detection signal immediately after an input abnormality occurs has the disadvantage that it is even worse. In order to improve the drawbacks of the third conventional example, as shown in FIG. 6, a charging capacitor 15 is connected to the collector of the secondary side transistor 5 of the photocoupler 3, turning off and charging the capacitor 15 through the resistor 16;
When the charging voltage V 2 of the capacitor 15 exceeds a predetermined reference voltage V 3 , the differential amplifier 17 operates;
When an input abnormality occurs due to the operation of the differential amplifier, the output means 8 is configured to send out a power failure detection signal by delaying it by a certain period of time that can be arbitrarily selected based on the time constants of the capacitor 15 and the resistor 16. This is improved by the fourth conventional power failure detection circuit shown in FIG. That is, the charging capacitor 1 in FIG.
As shown in the voltage waveform diagram of FIG. 7, when the DC input voltage from the rectifier circuit 1 is normal, the charging voltage V 2 of 5 is determined by the time constant of the capacitor 15 and resistor 16 by turning on/off the photocoupler 3. It rises with "PI off" for a certain period of time determined by, and "PI on" for the same period of time.
The waveform of voltage V 2 drops at
The charging voltage V 2 of 5 is the reference voltage of the differential amplifier 17.
Since the voltage is suppressed to a level lower than V 3 , the output of the differential amplifier 17 becomes "H" level, the drive transistor 6 is turned on, and the relay 7 is operated.
The detection contact 8 becomes open. If an abnormality occurs in the input AC power supply and the DC input voltage from the rectifier circuit 1 is abnormal, the secondary side transistor 5 of the photocoupler 3
continues to be off, the charging voltage V 2 of the capacitor 15 rises due to the charging curve formed by the resistor 16 and the capacitor 15 and exceeds the reference voltage V 3 of the differential amplifier 17, as shown in the voltage waveform diagram of FIG. The operation of the differential amplifier 17 is reversed and its output becomes "L" level, the drive transistor 6 and the relay 7 are turned off, and a power failure detection signal is sent from the signal output terminal b. Resistor 20, diode 21,
The resistor 22 applies so-called hysteresis so that the value of the reference voltage V 3 is lowered when the charging voltage V 2 of the capacitor 15 reaches the detection point C in the figure. As described above, the charging curve of the capacitor 15 and the resistor 16 allows the transmission of the detection signal in the event of an input abnormality to be delayed as desired, resulting in a power failure detection circuit suitable for the operation of the load device. However, the power failure detection circuit of this fourth conventional example immediately sends an abnormality detection signal when the input AC power supply returns to normal from an abnormal state and the DC input voltage V 1 to the photocoupler 3 returns to normal. will be canceled. Therefore, there is a problem that if the load device does not start up completely, the device may malfunction.
以上の回路例の他に、停電時の停電検出信号を
負荷装置の誤動作を引き起こさないように送出す
る停電検出回路は、図示しないが、種々ある。し
かし、停電状態から正常状態に復電した場合の問
題をも考慮した停電検出回路は少ない。 In addition to the above circuit example, there are various power outage detection circuits (not shown) that send out a power outage detection signal during a power outage so as not to cause a malfunction of the load device. However, there are few power outage detection circuits that take into consideration the problems that occur when power is restored to a normal state from a power outage state.
(d) 発明の目的
本発明は、入力の交流電源が異常となつた場合
に、負荷装置に必要な一定時間後に異常検出信号
を送出するばかりでなく、入力の交流電源が異常
状態から正常に復帰した場合に、やはり該装置に
必要な一定時間後に異常検出信号の送出を解除す
るような停電検出回路を提供することを目的とし
ている。(d) Purpose of the invention The present invention not only sends an abnormality detection signal to the load device after a certain period of time when the input AC power becomes abnormal, but also detects when the input AC power returns from the abnormal state to normal. It is an object of the present invention to provide a power outage detection circuit which, when restored, cancels the transmission of an abnormality detection signal after a certain period of time required for the device.
(e) 発明の構成
上記の目的は、入力の交流電源を整流する整流
回路１からの直流電圧V1を、一次側ダイオード
４と二次側トランジスタ５からなるホトカプラ３
の該一次側ダイオードの一端をコレクタに接続し
たトランジスタ１２のエミツタと、該ダイオード
の他端と該トランジスタのベースの間に設けた定
電圧ダイオード１３との接続点との間に入力し、
前記ホトカプラの二次側トランジスタのコレクタ
に充電用の第１のコンデンサ１５を接続し、該入
力電圧V1の低下を含む停電の場合に前記ホトカ
プラの二次側トランジスタがオフして前記第１の
コンデンサを抵抗１６を通して充電し該第１のコ
ンデンサの充電電圧V2が所定の第１の基準電圧
V3を越えた時に第１の差動増幅器１７が動作し、
該第１の差動増幅器の動作により、入力電源の異
常の発生時から一定時間後に、出力手段８が停電
検出信号を送出する停電検出回路において、前記
第１の差動増幅器の動作により動作を反転する第
２の差動増幅器２３と、先に電源電圧Vccで抵抗
２７を通して充電され前記第２の差動増幅器の反
転動作により放電する第２のコンデンサ２５と、
該第２のコンデンサの充電電圧V5が第２の基準
電圧V4より低い時に動作する第３の差動増幅器
２６とを具え、前記入力電圧V1の低下を含む断
の場合は、該第１、第２のコンデンサ１５，２５
と第１、第２、第３の差動増幅器１７，２３，２
６の動作により前記入力電源の異常の発生時から
一定時間後に、前記出力手段８が停電検出信号を
送出し、前記入力電圧V1が正常に復帰した場合
は、前記ホトカプラ３の二次側トランジスタ５が
オンして前記第１のコンデンサ１５を放電し、該
第１のコンデンサの充電電圧V2が前記第１の基
準電圧V3より低くなつて前記第１の差動増幅器
１７の動作が反転し、該第１の差動増幅器の動作
の反転により前記第２の差動増幅器２３の動作が
再反転して前記第２のコンデンサ２５を充電し、
該第２のコンデンサの充電電圧V5が前記第２の
基準電圧V4より高くなり前記第３の差動増幅器
２６の動作が反転して不作動となり、前記入力電
源の異常が正常に復電した時より一定時間後に、
前記出力手段８が送出していた停電検出信号を解
除するように構成した本発明の停電検出回路によ
つて達成される。(e) Structure of the Invention The above object is to convert the DC voltage V 1 from the rectifier circuit 1 that rectifies the input AC power into the photocoupler 3 consisting of the primary side diode 4 and the secondary side transistor 5.
is input between the emitter of a transistor 12 whose collector is connected to one end of the primary side diode, and the connection point between the voltage regulator diode 13 provided between the other end of the diode and the base of the transistor,
A first capacitor 15 for charging is connected to the collector of the secondary transistor of the photocoupler, and in the event of a power outage including a drop in the input voltage V1 , the secondary transistor of the photocoupler is turned off and the first capacitor 15 is turned off. A capacitor is charged through a resistor 16, and the charging voltage V2 of the first capacitor is a predetermined first reference voltage.
When the voltage exceeds V 3 , the first differential amplifier 17 operates,
The operation of the first differential amplifier causes the output means 8 to operate the power failure detection circuit in which the output means 8 sends out a power failure detection signal after a certain period of time from the occurrence of an abnormality in the input power supply. a second differential amplifier 23 that is inverted, and a second capacitor 25 that is previously charged through a resistor 27 with the power supply voltage Vcc and discharged by the inverting operation of the second differential amplifier;
a third differential amplifier 26 that operates when the charging voltage V 5 of the second capacitor is lower than the second reference voltage V 4 ; 1. Second capacitor 15, 25
and first, second, and third differential amplifiers 17, 23, 2
6, the output means 8 sends out a power failure detection signal after a certain period of time from the occurrence of the abnormality in the input power supply, and when the input voltage V1 returns to normal, the secondary side transistor of the photocoupler 3 5 turns on and discharges the first capacitor 15, the charging voltage V2 of the first capacitor becomes lower than the first reference voltage V3 , and the operation of the first differential amplifier 17 is reversed. Then, due to the reversal of the operation of the first differential amplifier, the operation of the second differential amplifier 23 is re-inverted to charge the second capacitor 25,
The charging voltage V 5 of the second capacitor becomes higher than the second reference voltage V 4 and the operation of the third differential amplifier 26 is reversed and becomes inactive, and the abnormality in the input power supply is restored to normal. After a certain period of time,
This is achieved by the power failure detection circuit of the present invention configured to cancel the power failure detection signal sent out by the output means 8.
(f) 発明の実施例
第９図は本発明の実施例の停電検出回路の構成
を示すブロツク図である。第９図において、１５
は第１のコンデンサ、１７は第１の差動増幅器、
２３は第２の差動増幅器、２６は第３の差動増幅
器、２４はトランジスタ、２５は第２のコンデン
サ、２７は充放電用の抵抗、２８，２９は第２の
基準電圧V4を定める抵抗を示す。第２の差動増
幅器２３は、抵抗２８と抵抗２９による電源電圧
Vccの分割電圧で抵抗２９の両端電圧を第２の基
準電圧V4として、其の＋端子と第３の差動増幅
器２６の−端子に印加し、第１の差動増幅器１７
の出力を第２の差動増幅器２３の−端子に入力す
る。そして第１の差動増幅器１７の出力が“Ｈ”
レベルの場合は、第２の差動増幅器２３の出力は
“Ｌ”レベルとなり、第１の差動増幅器１７の出
力が“Ｌ”レベルの場合は、第２の差動増幅器２
３の出力は“Ｈ”レベルとなる。トランジスタ２
４は第２の差動増幅器２３の出力の“Ｈ”レベル
でオンする。(f) Embodiment of the invention FIG. 9 is a block diagram showing the configuration of a power failure detection circuit according to an embodiment of the invention. In Figure 9, 15
is the first capacitor, 17 is the first differential amplifier,
23 is a second differential amplifier, 26 is a third differential amplifier, 24 is a transistor, 25 is a second capacitor, 27 is a charging/discharging resistor, 28 and 29 determine a second reference voltage V 4 Show resistance. The second differential amplifier 23 has a power supply voltage caused by a resistor 28 and a resistor 29.
The voltage across the resistor 29 with the divided voltage of Vcc is set as the second reference voltage V4 , and applied to its + terminal and the - terminal of the third differential amplifier 26, and the voltage across the resistor 29 is applied to the - terminal of the third differential amplifier 26.
The output of the differential amplifier 23 is input to the - terminal of the second differential amplifier 23. Then, the output of the first differential amplifier 17 is “H”
level, the output of the second differential amplifier 23 is "L" level, and when the output of the first differential amplifier 17 is "L" level, the output of the second differential amplifier 23 is "L" level.
The output of No. 3 becomes "H" level. transistor 2
4 is turned on when the output of the second differential amplifier 23 is at "H" level.
第２のコンデンサ２５は、トランジスタ２４の
オンにより充電していた電荷を放電し、トランジ
スタ２４のオフにより充電される。第３の差動増
幅器２６は、第２の基準電圧V4を其の−端子に
印加し、第２のコンデンサ２５に充電される充電
電圧V5を其の＋端子に印加して、充電電圧V5を
基準電圧V4と比較し、充電電圧V5が高く基準電
圧V4が低い場合は、其の出力が“Ｈ”レベルと
なり、継電器７の駆動用のトランジスタ６をオン
する。 The second capacitor 25 discharges the charge it had been charged when the transistor 24 is turned on, and is charged when the transistor 24 is turned off. The third differential amplifier 26 applies a second reference voltage V 4 to its negative terminal, and applies a charging voltage V 5 to be charged to the second capacitor 25 to its positive terminal, thereby increasing the charging voltage. V5 is compared with the reference voltage V4 , and if the charging voltage V5 is high and the reference voltage V4 is low, the output becomes "H" level and turns on the transistor 6 for driving the relay 7.
入力電源が正常の時は、ホトカプラ３のオン／
オフにより、充電用の第１のコンデンサ１５が充
放電するが、該コンデンサ１５の充電電圧V2が
常に第１の差動増幅器１７の基準電圧V3以下に
抑えられているので、該差動増幅器１７の出力は
“Ｈ”レベルである。そして第２の差動増幅器２
３の出力は、第１の差動増幅器１７の出力が
“Ｈ”レベルであるため、其の出力は“Ｌ”レベ
ルである。依つてトランジスタ２４がオフしてい
るため、第２コンデンサ２５の充電電圧V5は高
く、第３の差動増幅器２６の出力は“Ｈ”レベル
となり、駆動用のトランジスタ６と継電器７はオ
ン状態である。 When the input power is normal, photocoupler 3 is turned on/off.
When turned off, the first charging capacitor 15 charges and discharges, but since the charging voltage V 2 of the capacitor 15 is always suppressed below the reference voltage V 3 of the first differential amplifier 17, the differential The output of amplifier 17 is at "H" level. and second differential amplifier 2
Since the output of the first differential amplifier 17 is "H" level, the output of No. 3 is "L" level. Since the transistor 24 is off, the charging voltage V5 of the second capacitor 25 is high, the output of the third differential amplifier 26 is at "H" level, and the driving transistor 6 and relay 7 are on. It is.
入力電源に異常が起きると、ホトカプラ３のオ
フが続くため、充電用の第１のコンデンサ１５の
充電電位V2が上昇し第１の差動増幅器１７の出
力は、“Ｌ”レベルに反転し、第２の差動増幅器
２３の出力は“Ｈ”レベルに反転する。これによ
つてトランジスタ２４がオンし、第２のコンデン
サ２５を放電させ、第３の差動増幅器２６の出力
を“Ｌ”レベルに反転させ、駆動用のトランジス
タ６と継電器７はオフ状態となり、検出接点８が
閉じて、信号出力端ｂより停電検出信号を送出す
る。 When an abnormality occurs in the input power supply, the photocoupler 3 remains off, so the charging potential V2 of the first charging capacitor 15 rises, and the output of the first differential amplifier 17 is inverted to the "L" level. , the output of the second differential amplifier 23 is inverted to "H" level. As a result, the transistor 24 is turned on, the second capacitor 25 is discharged, the output of the third differential amplifier 26 is inverted to "L" level, and the driving transistor 6 and the relay 7 are turned off. The detection contact 8 closes and sends out a power failure detection signal from the signal output terminal b.
ここで入力電源が正常状態に復電したとする
と、ホトカプラ３はオン／オフを始めるため、第
１の差動増幅器１７の出力は“Ｈ”レベルに反転
し、第２の差動増幅器２３の出力は“Ｌ”レベル
に反転し、トランジスタ２４はオフとなる。しか
し、第２のコンデンサ２５は、抵抗２７との時定
数により充電されるため、或る一定の時間後でな
いと第３の差動増幅器２６の出力が“Ｈ”レベル
とならない。そのため継電器７は、一定の遅延時
間を持つてオンされ、検出接点８が開いて、停電
検出信号の送出が解除される。 If the input power is restored to normal state, the photocoupler 3 starts to turn on/off, so the output of the first differential amplifier 17 is inverted to "H" level, and the output of the second differential amplifier 23 is inverted to "H" level. The output is inverted to the "L" level, and the transistor 24 is turned off. However, since the second capacitor 25 is charged by the time constant with the resistor 27, the output of the third differential amplifier 26 does not reach the "H" level until after a certain period of time. Therefore, the relay 7 is turned on after a certain delay time, the detection contact 8 is opened, and the transmission of the power failure detection signal is canceled.
以上述べたように、本発明の実施例の第９図に
示した停電検出回路は、入力電源の停電時には、
負荷の装置の動作に必要な一定時間だけ第１のコ
ンデンサ１５と抵抗１６の時定数により遅延させ
て停電検出信号を送出し、正常に復電した時は、
第２のコンデンサ２５と抵抗２７の時定数によ
り、該装置に必要な一定時間だけ遅延させて停電
検出信号の送出を解除するので、本発明の目的は
達成されて問題は無い。 As described above, the power failure detection circuit shown in FIG. 9 according to the embodiment of the present invention performs
A power failure detection signal is sent after being delayed by the time constant of the first capacitor 15 and resistor 16 for a certain period of time necessary for the operation of the load device, and when the power is restored normally,
Since the time constant of the second capacitor 25 and the resistor 27 cancels the transmission of the power failure detection signal by delaying the device by a certain period of time, the object of the present invention is achieved without any problems.
(g) 発明の効果
以上説明した如く、本発明によれば、入力電源
の停電時には、負荷の装置の動作に必要な一定時
間だけ遅延させて停電検出信号を送出し、正常に
復電した時は、該装置に必要な一定時間だけ遅延
させて停電検出信号の送出を解除するので、負荷
装置の例えば情報処理装置の誤動作を防止し、該
装置のデータを保護する効果が得られる。(g) Effects of the Invention As explained above, according to the present invention, in the event of a power outage of the input power supply, the power outage detection signal is delayed by a certain period of time necessary for the operation of the load device, and the power outage detection signal is sent out when the power is restored normally. Since the transmission of the power failure detection signal is canceled after delaying the power outage detection signal by a certain period of time necessary for the device, it is possible to prevent malfunction of the load device, for example, the information processing device, and to protect the data of the device.
第１図、第２図、第４図、第６図は、従来の停
電検出回路の構成例のブロツク図であり、第３
図、第５図、第７図、第８図は、それら従来例の
動作説明のための電圧波形図であり、第９図が本
発明の実施例の停電検出回路の構成を示すブロツ
ク図である。
図において、１は整流回路、３はホトカプラ、
４は一次側ダイオード、５は二次側トランジス
タ、６は駆動トランジスタ、７は継電器、８は検
出接点、１１，１３は定電圧ダイオード、１２，
２４はトランジスタ、１４，１６，１８，１９，
２０，２２，２７，２８，２９は抵抗、１５は第
１のコンデンサ、２５は第２のコンデンサ、１７
は第１の差動増幅器、２３は第２の差動増幅器、
２６は第３の差動増幅器である。
1, 2, 4, and 6 are block diagrams of configuration examples of conventional power failure detection circuits.
5, 7, and 8 are voltage waveform diagrams for explaining the operation of these conventional examples, and FIG. 9 is a block diagram showing the configuration of a power failure detection circuit according to an embodiment of the present invention. be. In the figure, 1 is a rectifier circuit, 3 is a photocoupler,
4 is a primary side diode, 5 is a secondary side transistor, 6 is a drive transistor, 7 is a relay, 8 is a detection contact, 11 and 13 are constant voltage diodes, 12,
24 is a transistor, 14, 16, 18, 19,
20, 22, 27, 28, 29 are resistors, 15 is a first capacitor, 25 is a second capacitor, 17
is a first differential amplifier, 23 is a second differential amplifier,
26 is a third differential amplifier.
Claims (1)
直流電圧V1を、一次側ダイオード４と二次側ト
ランジスタ５からなるホトカプラ３の該一次側ダ
イオードの一端をコレクタに接続したトランジス
タ１２のエミツタと、該ダイオードの他端と該ト
ランジスタのベースの間に設けた定電圧ダイオー
ド１３との接続点との間に入力し、前記ホトカプ
ラの二次側トランジスタのコレクタに充電用の第
１のコンデンサ１５を接続し、該入力電圧V1の
低下を含む停電の場合に前記ホトカプラの二次側
トランジスタがオフして前記第１のコンデンサを
抵抗１６を通して充電し、該第１のコンデンサの
充電電圧V2が所定の第１の基準電圧V3を越えた
時に第１の差動増幅器１７が動作し、入力電源の
異常の発生時から一定時間後に該第１の差動増幅
器の動作により出力手段８が停電検出信号を送出
する停電検出回路において、 前記第１の差動増幅器の動作により動作を反転
する第２の差動増幅器２３と、先に電源電圧Vcc
で抵抗２７を通して充電され前記第２の差動増幅
器の反転動作により放電する第２のコンデンサ２
５と、該第２のコンデンサの充電電圧V5が第２
の基準電圧V4より低い時に動作する第３の差動
増幅器２６とを具え、 前記入力電圧V1の低下を含む停電の場合は、
該第１、第２のコンデンサ１５，２５と第１、第
２、第３の差動増幅器１７，２３，２６の動作に
より前記入力電源の異常の発生時から一定時間後
に前記出力手段８が停電検出信号を送出し、前記
入力電圧V1が正常に復帰した場合は、前記ホト
カプラ３の二次側トランジスタ５がオンして前記
第１のコンデンサ１５を放電し、該第１のコンデ
ンサの充電電圧V2が前記第１の基準電圧V3より
低くなつて前記第１の差動増幅器１７の動作が反
転し、該第１の差動増幅器の動作の反転により前
記第２の差動増幅器２３の動作が再反転して前記
第２のコンデンサ２５を充電し、該第２のコンデ
ンサの充電電圧V5が前記第２の基準電圧V4より
高くなり前記第３の差動増幅器２６の動作が反転
して不作動となり、入力電源の復電時から一定時
間後に前記出力手段８が送出していた停電検出信
号を解除することを特徴とした停電検出回路。[Claims] 1. A DC voltage V 1 from a rectifier circuit 1 that rectifies an input AC power source is connected to the collector of a photocoupler 3 consisting of a primary diode 4 and a secondary transistor 5, with one end of the primary diode connected to the collector. A charging voltage is input between the emitter of the transistor 12 and the connection point of the constant voltage diode 13 provided between the other end of the diode and the base of the transistor, and the collector of the secondary side transistor of the photocoupler is supplied with a charging voltage. A first capacitor 15 is connected, and in the event of a power outage including a drop in the input voltage V1 , the secondary side transistor of the photocoupler is turned off and the first capacitor is charged through the resistor 16, and the first capacitor The first differential amplifier 17 operates when the charging voltage V 2 exceeds a predetermined first reference voltage V 3 , and the first differential amplifier 17 operates after a certain period of time from the occurrence of an abnormality in the input power supply. In the power outage detection circuit in which the output means 8 sends out a power outage detection signal, the second differential amplifier 23 whose operation is inverted by the operation of the first differential amplifier and the power supply voltage Vcc first are connected.
a second capacitor 2 that is charged through a resistor 27 and discharged by the inverting operation of the second differential amplifier;
5 and the charging voltage V 5 of the second capacitor is the second
a third differential amplifier 26 that operates when the reference voltage V 4 is lower than the input voltage V 4 , and in the case of a power outage including a drop in the input voltage V 1 ,
Due to the operation of the first and second capacitors 15 and 25 and the first, second and third differential amplifiers 17, 23 and 26, the output means 8 is interrupted after a certain period of time from the occurrence of an abnormality in the input power supply. When the detection signal is sent and the input voltage V1 returns to normal, the secondary side transistor 5 of the photocoupler 3 is turned on to discharge the first capacitor 15, and the charging voltage of the first capacitor is reduced. V 2 becomes lower than the first reference voltage V 3 and the operation of the first differential amplifier 17 is reversed, and due to the reversal of the operation of the first differential amplifier, the operation of the second differential amplifier 23 is reversed. The operation is reversed again to charge the second capacitor 25, and the charging voltage V5 of the second capacitor becomes higher than the second reference voltage V4 , and the operation of the third differential amplifier 26 is reversed. The power failure detection circuit is characterized in that the power failure detection signal that the output means 8 has been sending out is canceled after a certain period of time after the input power is restored.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5768384A JPS60200725A (en) | 1984-03-26 | 1984-03-26 | Power interruption detector circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5768384A JPS60200725A (en) | 1984-03-26 | 1984-03-26 | Power interruption detector circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60200725A JPS60200725A (en) | 1985-10-11 |
| JPH0311171B2 true JPH0311171B2 (en) | 1991-02-15 |
Family
ID=13062729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5768384A Granted JPS60200725A (en) | 1984-03-26 | 1984-03-26 | Power interruption detector circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60200725A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008151723A (en) * | 2006-12-20 | 2008-07-03 | Meidensha Corp | Instantaneous voltage drop detection device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5362635U (en) * | 1976-10-29 | 1978-05-27 |
-
1984
- 1984-03-26 JP JP5768384A patent/JPS60200725A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60200725A (en) | 1985-10-11 |
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