JPH0311095B2 - - Google Patents
Info
- Publication number
- JPH0311095B2 JPH0311095B2 JP4411986A JP4411986A JPH0311095B2 JP H0311095 B2 JPH0311095 B2 JP H0311095B2 JP 4411986 A JP4411986 A JP 4411986A JP 4411986 A JP4411986 A JP 4411986A JP H0311095 B2 JPH0311095 B2 JP H0311095B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode
- gaas
- effect
- functional element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000000694 effects Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 239000010936 titanium Substances 0.000 description 7
- 229910052720 vanadium Inorganic materials 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- LMRFGCUCLQUNCZ-UHFFFAOYSA-N hydrogen peroxide hydrofluoride Chemical compound F.OO LMRFGCUCLQUNCZ-UHFFFAOYSA-N 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
〔概要〕
ガリウム砒素（GaAs）系デバイス、特に負電
位を用いた集積回路では、電界効果トランジスタ
（FET）の近傍に設けられた電極（サイドゲート
電極）の電位の影響を受ける、いわゆるサイドゲ
ート効果によりデバイスの特性が劣化する。サイ
ドゲート効果を防止するため、GaAs基板の、
FET形成領域の裏面にリセス（くぼみ）を形成
し、リセス上に形成された電極に正電位を印加で
きるようにした構造を提起する。[Detailed Description of the Invention] [Summary] In gallium arsenide (GaAs)-based devices, especially integrated circuits using negative potential, the influence of the potential of an electrode (side gate electrode) provided near a field-effect transistor (FET) The characteristics of the device deteriorate due to the so-called side gate effect. To prevent the side gate effect, the GaAs substrate
We propose a structure in which a recess (indentation) is formed on the back side of the FET formation area, and a positive potential can be applied to the electrode formed on the recess.
本発明はサイドゲート効果を抑制したGaAs系
半導体装置の構造に関する。
The present invention relates to a structure of a GaAs-based semiconductor device that suppresses side gate effects.
GaAs系デバイスでは、サイドゲート効果によ
りデバイスの特性が劣化するため、デバイスの性
能、および信頼性を低減している。 In GaAs-based devices, side gate effects degrade device characteristics, reducing device performance and reliability.
特に、負電位を用いた集積回路、例えばBFL
（Buffered FET Logic）、SDFL（Schottky
Diode FET Logic）等において、この影響が大
きいため、対策が要望されている。 In particular, integrated circuits using negative potentials, e.g. BFL
(Buffered FET Logic), SDFL (Schottky
Since this has a large effect on devices such as FET Logic (Diode FET Logic), countermeasures are required.
〔従来の技術〕
第２図はGaAs FETを集積した従来の半導体
装置の断面図である。[Prior Art] FIG. 2 is a cross-sectional view of a conventional semiconductor device integrating GaAs FETs.
図において、１はGaAs基板で、この表面より
機能素子形成領域としてｎ型GaAs領域１Ａ，１
Ｂが形成されている。 In the figure, 1 is a GaAs substrate, and n-type GaAs regions 1A and 1 are formed as functional element formation regions from this surface.
B is formed.
機能素子としてGaAs FETが形成され、３Ａ，
３Ｂ，３Ｃはチタンタングステンシリサイド
（Ti WSi）よりなるゲート電極、４Ａ，４Ｂ，
４Ｃ，４Ｄ，４Ｅは金ゲルマニウム／金
（AuGe／Au）よりなるオーミツクス（ソース、
ドレイン）電極である。 A GaAs FET is formed as a functional element, and a 3A,
3B, 3C are gate electrodes made of titanium tungsten silicide (Ti WSi); 4A, 4B,
4C, 4D, and 4E are ohmics (source,
drain) electrode.
５は絶縁層で二酸化珪素（SiO2）層、６は配
線層でチタン／白金／金（Ti／Pt／Au）層であ
る。 5 is an insulating layer, which is a silicon dioxide (SiO 2 ) layer, and 6 is a wiring layer, which is a titanium/platinum/gold (Ti/Pt/Au) layer.
以上のような通常の構造の負電位を用いる集積
回路においては、サイドゲート効果の影響は大き
い。 In an integrated circuit using a negative potential having a normal structure as described above, the influence of the side gate effect is large.
サイドゲート効果を防ぐ従来方法としてFET
の回りにメタルのガードリングを形成する方法が
提案されているが、面積を大きくとるため、高集
積化には不適当である。 FET as a conventional method to prevent side gate effect
A method has been proposed in which a metal guard ring is formed around the device, but this method requires a large area and is not suitable for high integration.
通常の構造ではサイドゲート効果の影響を受
け、また従来のガードリングを用いる方法では集
積度を低下させた。
Conventional structures are affected by side gate effects, and conventional methods using guard rings reduce the degree of integration.
上記問題点の解決は、ガリウム砒素基板の、機
能素子形成領域の裏面に形成されたリセス内に電
極を形成してなり、該電極に正電位を印加するこ
とによりサイドゲート効果を低減する本発明によ
る半導体集積回路装置により達成される。
The above problem is solved by the present invention, which reduces the side gate effect by forming an electrode in the recess formed on the back surface of the functional element formation region of the gallium arsenide substrate and applying a positive potential to the electrode. This is achieved by a semiconductor integrated circuit device.
第３図〜第５図に示される実測図を用いて、本
発明の原理を説明する。
The principle of the present invention will be explained using actual measurement diagrams shown in FIGS. 3 to 5.
第３図は基板バイアス効果を示す図である。 FIG. 3 is a diagram showing the substrate bias effect.
図は、ドレイン−ソース間電圧Vdsを一定に
し、基板バイアスVSUBをパラメータにした、ドレ
イン−ソース電流Idsとゲート−ソース電圧Vgsの
関係を示す。 The figure shows the relationship between the drain-source current I ds and the gate-source voltage V gs when the drain-source voltage V ds is kept constant and the substrate bias V SUB is used as a parameter.
第４図はサイドゲート効果を示す図である。 FIG. 4 is a diagram showing the side gate effect.
図は、Vds＝一定、VSUB＝0Vのときのサイド電
極バイアスVsideをパラメータにした、IdsとVgsの
関係を示す。 The figure shows the relationship between I ds and V gs using the side electrode bias V side when V ds = constant and V SUB = 0V as a parameter.
第５図は本発明の原理を説明する図である。 FIG. 5 is a diagram explaining the principle of the present invention.
図は、VSUBをパラメータにした、Vds＝一定、
Vgs＝0.5VのときをIdsとVsideの関係を示す図であ
る。 The figure shows V ds = constant, with V SUB as a parameter.
FIG. 3 is a diagram showing the relationship between I ds and V side when V gs =0.5V.
図において、VSUB＝−２、−１、０、＋１、＋2V
に対応する曲線郡の内、VSUB＝＋２、＋1Vの曲線
においては、IdsがVsideの影響を受け難いことが
分かる。 In the figure, V SUB = -2, -1, 0, +1, +2V
It can be seen that among the curves corresponding to V SUB =+2 and +1 V, I ds is hardly affected by V side .
第５図の結果が示すように、現象的にはバツク
ゲート（基板）バイアスを正に振つて、サイドゲ
ート効果が抑制されることが分かつたので、機能
素子形成領域の基板の厚さを減らして基板電位の
影響を大きくしてサイドゲート効果の抑制を一層
効果的にし、機能素子形成領域以外の部分は寄生
容量の増加を防ぐためと、強度を保つために基板
の厚さはそのままとする。 As shown in the results shown in Figure 5, it was found that the side gate effect can be suppressed by applying a positive back gate (substrate) bias, so reducing the thickness of the substrate in the functional element formation region. The effect of the substrate potential is increased to more effectively suppress the side gate effect, and the thickness of the substrate is left unchanged in areas other than the functional element formation region to prevent an increase in parasitic capacitance and to maintain strength.
第１図はGaAs FETを集積した本発明の半導
体装置の断面図である。
FIG. 1 is a cross-sectional view of a semiconductor device of the present invention that integrates GaAs FETs.
図において、１は厚さ400〜500〓のGaAs基
板、１Ａ，１Ｂは機能素子（FET）形成領域で
ｎ型GaAs領域、３Ａ，３Ｂ，３ＣはTi WSiよ
りなるゲート電極、４Ａ，４Ｂ，４Ｃ，４Ｄ，４
ＥはAuGe／Auよりなるオーミツク電極、５は
絶縁層でSiO2層、６は配線層でTi／Pt／Au層で
ある。 In the figure, 1 is a GaAs substrate with a thickness of 400 to 500 mm, 1A and 1B are functional element (FET) formation regions and n-type GaAs regions, 3A, 3B, and 3C are gate electrodes made of Ti WSi, and 4A, 4B, and 4C are ,4D,4
E is an ohmic electrode made of AuGe/Au, 5 is an insulating layer of two SiO layers, and 6 is a wiring layer of Ti/Pt/Au layers.
ここまでは従来例と同様であるが、基板裏面に
機能素子の下部に弗酸−過酸化水素系エツチヤン
トを用いてリセスエツチングを行い、深さ250〓
のリセス７，８を形成する。 The process up to this point is the same as the conventional example, but recess etching is performed on the bottom of the functional element on the back side of the substrate using a hydrofluoric acid-hydrogen peroxide etchant to a depth of 250 mm.
recesses 7 and 8 are formed.
つぎに、リセス部、または基板裏面全面に
AuGe／Auよりなる裏面電極９を形成する。 Next, apply it to the recess or the entire backside of the board.
A back electrode 9 made of AuGe/Au is formed.
リセスを深く、裏面電極と機能素子との距離を
短くする程、サイドゲート効果の低減に有効であ
る。 The deeper the recess and the shorter the distance between the back electrode and the functional element, the more effective the side gate effect can be reduced.
このリセスエツチングにより、基板の厚さを従
来の厚さに保つたまま、即ち基板の強度を保つた
まま、裏面電極に有効に正電位を印加することが
できる。 This recess etching makes it possible to effectively apply a positive potential to the back electrode while maintaining the thickness of the substrate at the conventional thickness, that is, while maintaining the strength of the substrate.
また、ゲートアレイ等においては、溝状にリセ
スエツチングすることで、このパターンをマスタ
マスクとすることも可能であり、リセス深さと印
加電圧を調整することにより裏面を電源線とする
ことができる等の利点がある。 Furthermore, in gate arrays, etc., by etching groove-shaped recesses, this pattern can be used as a master mask, and by adjusting the recess depth and applied voltage, the back side can be used as power supply lines, etc. There are advantages.
以上詳細に説明したように本発明によれば、基
板裏面から正電位を有効に印加でき、デバイスの
サイドゲート効果を低減できる。
As described above in detail, according to the present invention, a positive potential can be effectively applied from the back surface of the substrate, and the side gate effect of the device can be reduced.
第１図はGaAs FETを集積した本発明の半導
体装置の断面図、第２図はGaAs FETを集積し
た従来の半導体装置の断面図、第３図は基板バイ
アス効果を示し、Vds＝一定のときの、VSUBをパ
ラメータにしたIdsとVgsの関係を示す図、第４図
はサイドゲート効果を示し、Vds＝一定、VSUB＝
0Vのときの、VsideをパラメータにしたIdsとVgsの
関係を示す図、第５図は本発明の原理を説明する
図で、VSUBをパラメータにした、Vds＝一定、Vgs
＝0.5VのときのIdsとVsideの関係を示す図である。
図において、１はGaAs基板、１Ａ，１Ｂは機
能素子（FET）形成領域でｎ型GaAs領域、３
Ａ，３Ｂ，３ＣはTi WSiよりなるゲート電極、
４Ａ，４Ｂ，４Ｃ，４Ｄ，４ＥはAuGe／Auよ
りなるオートミツク電極、５は絶縁層でSiO2層、
６は配線層でTi／Pt／Au層、７，８はリセス、
９はAuGe／Auよりなる裏面電極である。
Figure 1 is a cross-sectional view of a semiconductor device of the present invention that integrates GaAs FETs, Figure 2 is a cross-sectional view of a conventional semiconductor device that integrates GaAs FETs, and Figure 3 shows the substrate bias effect, with V ds = constant. Figure 4 shows the relationship between I ds and V gs with V SUB as a parameter when V ds = constant, V SUB =
A diagram showing the relationship between I ds and V gs using V side as a parameter at 0V. Figure 5 is a diagram explaining the principle of the present invention. V ds = constant, V gs using V SUB as a parameter.
FIG. 3 is a diagram showing the relationship between I ds and V side when = 0.5V. In the figure, 1 is a GaAs substrate, 1A and 1B are functional element (FET) forming regions, which are n-type GaAs regions, and 3
A, 3B, 3C are gate electrodes made of Ti WSi,
4A, 4B, 4C, 4D, 4E are automatic electrodes made of AuGe/Au, 5 is an insulating layer with two SiO layers,
6 is the wiring layer, Ti/Pt/Au layer, 7 and 8 are recesses,
9 is a back electrode made of AuGe/Au.
Claims (1)
面に形成されたリセス内に電極を形成してなり、
該電極に正電位を印加することを特徴とする半導
体装置。1. An electrode is formed in a recess formed on the back surface of a functional element formation region of a gallium arsenide substrate,
A semiconductor device characterized in that a positive potential is applied to the electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4411986A JPS62202562A (en) | 1986-03-03 | 1986-03-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4411986A JPS62202562A (en) | 1986-03-03 | 1986-03-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62202562A JPS62202562A (en) | 1987-09-07 |
| JPH0311095B2 true JPH0311095B2 (en) | 1991-02-15 |
Family
ID=12682717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4411986A Granted JPS62202562A (en) | 1986-03-03 | 1986-03-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62202562A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10330157A1 (en) * | 2003-07-04 | 2005-02-03 | Zf Friedrichshafen Ag | Powershift transmission for construction machinery, in particular for backhoe loaders and telehandlers |
| DE10330159A1 (en) * | 2003-07-04 | 2005-02-03 | Zf Friedrichshafen Ag | Powershift transmission for construction machinery, in particular for backhoe loaders and telehandlers |
-
1986
- 1986-03-03 JP JP4411986A patent/JPS62202562A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62202562A (en) | 1987-09-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |