JPH03110625A - Barrel shifter - Google Patents

Abstract

PURPOSE:To perform rotation, logical shift, and arithmetic shift in a circuit adapted to integration with a small amount of hardware by providing first and second registers and a bidirectional shift matrix. CONSTITUTION:One of first and second registers 1 and 2 is used as the input register of data for shift processing, and the other is used as the output register of shift results. When an input/output terminal for N-th bit shift data transfer of the first register 1 and that for M-th bit shift data transfer of the second register 2 are connected in a bidirectional shift matrix 3, one transmission gate is connected between both connected terminals in the case of N>=M. In the case of N<M, two transmission gates are connected in series between connected terminals, and one transmission gate is used as a selector. Thus, a high-speed barrel shifter is obtained which has functions of rotation, logical shift, and arithmetic shift with a small amount of hardware in the circuit constitution adapted to integration.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device having a shift function, and in particular realizes rotation with a small number of elements and a circuit suitable for integration. The present invention relates to a shift circuit.

[Conventional technology]

Generally, a data processing device such as a microprocessor is equipped with a barrel shifter to shift multiple bits of data at high speed. In order to perform logical operations and arithmetic operations, the barrel shifter has three types of processing functions: logical shift, arithmetic shift, and rotation.

FIG. 6 is a circuit diagram of a conventional 32-bit barrel shifter. 33 is a 1-bit fixed digit shift circuit, 34 is a 2-bit fixed digit shift circuit, 35 is a 4-bit fixed digit shift circuit, 36 is an 8-bit fixed digit shift circuit, and 37 is a 1-bit fixed digit shift circuit.
This is a 6-bit fixed digit shift circuit. Input signal line 200
-231 are input signal lines for 32-bit data. 4
1 is an AND gate, and 42 is an OR gate. In the 1-bit fixed digit shift circuit 33, 38 is a control signal for performing a 1-bit leftward shift, 39 is a control signal for outputting input data as it is without shifting, and 40
is a control signal for shifting one bit to the right. In the 2-bit fixed digit shift circuit 34, 43 is a control signal for performing a 2-bit leftward shift;
45 is a control signal for outputting the input data as it is without shifting, and 45 is a control signal for shifting 2 bits to the right. In the 4-bit fixed digit shift circuit 35, 46 is a control signal for performing a 4-bit left shift, 47 is a control signal for outputting the input data as it is without shifting, and 48 is a 4-bit right shift signal. This is a control signal for performing a direction shift. In the 8-bit fixed digit shift circuit 36, 49 is a control signal for performing an 8-bit leftward shift, 50 is a control signal for outputting the input data as it is without shifting, and 51 is an 8-bit rightward shift. This is a control signal for shifting.

In the 16-bit fixed digit shift circuit 37, 52 is 1
Control signal for performing a 6-bit leftward shift, 53
54 is a control signal for outputting the input data as it is without shifting, and 54 is a control signal for shifting 16 bits to the right.

The 1-bit fixed digit shift circuit 33 outputs the control signal 38 as “
When the control signal 39 is set to "H", it is possible to rotate one bit to the left, and when the control signal 39 is set to "H", the input data can be output as is.

By setting the control signal 40 to "H", one bit can be rotated to the right.

When configuring a 32-bit barrel shifter, 2 bits,
The 4-bit, 8-bit, and 16-bit fixed digit shift circuits were constructed in the same configuration as the 1-bit fixed digit shift circuit 33, and by connecting them in five stages in series, it was possible to rotate any bit in the left/right direction. .

For example, when rotating 10 bits to the right,
The control signal 45 is changed by the 2-bit fixed digit shift circuit 34.
By setting it to H''', 2 bits are rotated to the right, and by setting the control signal 51 of the 8-bit fixed digit shift circuit 36 to ``H'' for the rotated data, 8 bits are rotated to the right. perform rotation,
The other fixed digit shift circuits can achieve a rightward rotation of 10 bits by setting the control signals 39, 47, 53 to "H'" so as to output the input signals as they are.

[Problem to be solved by the invention]

In the above-mentioned conventional barrel shifter, as mentioned above, multiple stages of fixed digit chics are connected in series, and the delay becomes thick (and the processing time becomes long) because it passes through many gates.
There was a problem in that the wiring became complicated when implementing it into an LSI.

Further, the barrel shifter is used exclusively for rotation operations, and if it were attempted to add logical shift and arithmetic shift functions, there was a problem in that the number of control signals and the number of transistors would increase.

This invention was made in order to solve the problems of the conventional ones, and provides a barrel shifter that can perform rotation, logical shift, and arithmetic shift with a small amount of hardware and with a circuit suitable for integration. The purpose is to

[Means to solve the problem]

The barrel shifter according to the present invention has a bidirectional shift matrix, and in the shift matrix, the first
If the input/output terminal for transferring the N-th bit shift data of the register is connected to the input/output terminal for transferring the M-th bit shift data of the second register, if 82M, there is a connection between the connected terminals. If one transmission gate is connected and N<M, two transmission gates are connected in series between the connected terminals, and the negative transmission gate is configured to function as a selector. The barrel shifter is a charge system and is configured to perform a shift operation using inverted logic to increase speed.

[Effect]

In the present invention, a bidirectional shift matrix is provided, and in each shift matrix, an input/output terminal for transferring N-th bit shift data of a first register and a second
When the input/output terminals for transferring the M-th bit shift data of the register are connected, if it is 82M, one transmitter gate is connected between the connected terminals, and N
<M, by configuring the shift circuit so that two transmission gates are connected between the connected terminals and one transmission gate serves as a selector, the amount of hardware can be reduced and integration can be achieved. With a suitable circuit configuration, a high-speed barrel shifter having rotation, logical shift, and arithmetic shift functions can be realized.

(Example〕 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a 32-bit barrel shifter according to one embodiment of the present invention, where 1 is BBOO, BBOI.

This is a second register consisting of 32 bits BBO2, . . . , BB31. 2 is BAOO, BAOL, BA
O2, ... The second consisting of 32 bits of BA31
It is a register. One of the above registers serves as an input register for data during shift processing, and the other serves as an output register for shift results. 3 is a bidirectional shift matrix, 4 is a data input bus, and 5 is a shift result output bus.

7ij (0-5i≦3, O≦j≦9) is a control signal that becomes “H” depending on the shift width, and 71j is a control signal that becomes “H” when the shift width is 1.
This is a control signal that becomes "H" when the bit is j. 10 is a control signal that becomes "H" when performing a rotation, 11 is an arithmetic shift, a shift in the right direction, and a sign bit of "
This is a control signal that becomes "H" only when ROTIO is "H". Reference numeral 17 is a transistor group that is turned on when ROTIO is "H". Reference numeral 17 is a transistor group that is turned on when 5HAII is "H". 5ij is 5FTlj (7i j
) is a group of transistors that turn on when it is “H”.80
0 to 831 are shift buses connected to the No. 1 register, and shift paths <5k1) (0≦≦3.0≦1≦9)
is connected to the 1st bit BBk1 of the register 1. 900 to 931 are shift paths connected to the second register 2, and shift paths 9st (Q≦3≦3.0≦
t≦9) is connected to the st bit BA3t of the second register 2. 600 to 631 are shift paths required when performing rotation or arithmetic shift, and shift path (6g h) (0≦g≦3.0≦h≦9) is the shift path (6g h) (0≦g≦3.0≦h≦9) when the transistor group 16 is turned on.
8g h).

The circuit diagram of the barrel shifter shown in FIG. 1, which is an embodiment of the present invention, is shown in a block diagram as shown in FIG.

No. 1. The circuit configuration of the second register 2 is shown in FIG. 3, where 23 is a latch that holds data, and 24 is an input bus 4.
a transmitter gate 25 that opens when input data is taken into the register 1 or the second register 2;
26 is an inverter; 27 is an N-channel transistor connected in series for discharging; 28 is a P-channel transistor for precharging; 29 is PATH, which is connected to the shift path 800-831.900-931. 30 is a transmission gate for feedback of the latch 23, and 31 and 32 are inverters.

FIG. 4 is a timing diagram when rotating one bit to the right in the shift circuit of FIG. 1. 21
is an internal operating clock of a data processing device including a shift circuit, and a barrel shifter according to an embodiment of the present invention has clocks A and B.
, C, and D. 22 is a clock signal φ for controlling the P-channel transistor 28 for precharging.

The operations of the first register 1 and the second register 2 will be explained using FIGS. 3 and 4. When the internal operation clock 21 is at timing A, the transmission gate 24 for taking in input data opens, and the latch 2 is transferred from the input bus 4.
By taking in the input data into the register 3, the input data is stored in the register 1. When the internal operation clock 21 reaches timing B, the control clock φ22 becomes "L",
P-channel transistor 28 is ONL, shift path 6
00-631.800-831.900-931 are precharged. When the internal operation clock 21 performs a rightward rotation, arithmetic shift, or logical shift at timing C, C4, which is one of the gate signals of the discharge transistor 27 connected in series in the second register 2, becomes H''. At this time, the latch 2 of the first register
If the data stored in 3 is 0'', PATH29
is not discharged and the precharged data “
1'' is output on the PATH 29. The data ``1'' output on the PATH 29 is shifted, inverted by the inverter 26 of the second register 2, and taken into the latch 23. , the shift result "0" is stored. Conversely, if the data stored in the latch 23 of the first register 1 is "1", the PAT
H29 is discharged by the discharge transistor 27, and the discharged data “0” becomes P.
Output on ATH29.

The data "0" output on the PATH 29 is shifted, inverted by the inverter 26 of the second register 2, and taken into the latch 23, so that the shift result 1" is stored in the second register 2. In this way, data is transferred within the shift matrix using inverted logic.

Next, the operation of the rotito will be explained using FIGS. 1 and 4. First, a case will be described in which a one-focus rotation to the right is performed using 32-bit data.

Data input from the input bus 4 is stored in the first register 1. The MSB is BB31.

When rotating, ROTIO becomes "H" from the rising edge of D to the next rising edge of D, and this opens the transistor group 16.Since no arithmetic shift is performed, 5HAIL remains "L". In this example, since the rotation is 1 bit to the right, only 5FTOI (701) becomes "H", and 5FTOO (700), 5FTO2 (702),
...5FT31 (731) becomes 'L'', which turns on the transistor group 501. By turning on the transistor group 501, the BBO of the first transistor 1 turns on.
The input data stored in I, .
The signals are transmitted to shift paths 900 to 930 and shifted to BAOO, . . . BA30 of the second register 2. BBOO of the first register is transmitted from the shift path 800 to the shift path 600 via the transmission gate 16a, and then transmitted to the shift path 931 via the transmission gate 501a, and rotated to BA31 of the second register 2. Rotating one bit to the right is performed as described above.

The above description has been about rightward rotation of 1 bit, but even in the case of 1 bit leftward rotation, the input register where input data is stored is the second register 2, and the output register where the shift result is stored is the register 2. The operation is exactly the same as in the case of a rightward rotation of 1 bit.

In the above, we have described the case where 1-bit rotation is performed for 32-bit data, but the 32-bit barrel shifter of the present invention can rotate not only 32-bit data but also halfword 16-bit and byte (8-bit) data. It is also possible to achieve rotito.

FIG. 5 is a diagram showing a method of processing various sizes in an embodiment of the present invention. As shown in FIG. 5(a), 1
When handling 6-bit data, input 16-bit data to both the upper 16 bits and lower 16 bits of the 32-bit register 1, and rotate the right rotation as shown in Figure 5(b). In the case of , the MS of the second register 2
The upper 16 bits on the B side are output, and in the case of leftward rotation, the lower 16 bits on the LSB side of the second register 2 are output. Also, when handling 8-bit data, the fifth
As shown in Figure (a), 8-bit data is input to both the upper 8 bits and lower 8 bits of the 32-bit register 1, and as shown in Figure 5 (b), the data is input to the right. In the case of rotation, the upper 8 on the MSB side of the second register 2
Outputs the bit, and in case of rotation to the left, the second
The lower 8 bits on the LSB side of register 2 are output.

When performing a 1-bit rightward logical shift, ROTIO remains at "L" in the timing diagram shown in FIG. 4, and the other signals are the same as in the case of ROTIO. Therefore, in the case of a rightward logical shift, there is no path for shifting from the register 1 to the 31st bit BA31 of the second register 2. As a result, "0", which is the inverted signal of the precharged shift path 931, is taken into the 31st bit BA31 of the second register 2 and zero-extended. In the case of a 1-bit leftward logical shift, the second register 2 or the second
There is no longer a path to shift to the O-th bit BBoo of register 2. 4: As a result, “0”, which is the inverted signal of the precharged shift path 800, is transferred to the first register
The data is taken into the 0th bit of BBOO and zero-extended.

Next, arithmetic shift will be explained. The operation of an arithmetic shift differs from that of a logical shift in that it is a rightward shift, and
This applies only when the sign bit is “l”. Therefore, we will explain the case of arithmetic shift to the right by 1 bit (sign bit is “1”). In this case, 1 phase with a timing of 5HA11'l<C. As a result, a rightward shift is performed, and the precharged shift paths 600 to 631 are discharged by the transistor group 17 to become 60'', and the data discharged by turning on the transmission gate 501a. "0" passes through the shift path 931, and by inverting the data "0", the data "0" is transferred to the 31st bit BA31 of the second register 2, which requires sign extension.
Store "1".

With the operation described above, the operation of arithmetic shift, and
The present circuit can also operate when there is a rightward shift and the sign bit is "1".

Note that although the above description has been made regarding the l-bit logical shift, arithmetic shift, and roti shift, the same operation applies to the N-bit logical shift, arithmetic shift, and roti.

Further, although an example of a 32-bit barrel shifter has been shown above, an N-bit barrel shifter can be similarly implemented.

〔Effect of the invention〕

As described above, according to the present invention, there is a bidirectional shift matrix, and in the shift matrix, the first
When the input/output terminal for transferring the N-th bit shift data of the register is connected to the input/output terminal for transferring the M-th bit shift data of the second register, if N≧M, the connected terminal One transmission gate is connected between them, and if N<M, the shift circuit is configured such that two transmission gates are connected in series between the connected terminals.The circuit configuration is as follows. It has a simple repeating structure, has a regular structure suitable for integration, and can be laid out in a bit-sliced manner. Furthermore, since the shift path can be constructed using one or two stages of N-channel MO3s that are bidirectionally shiftable, the number of gate stages in the shift path is small, and a high-speed barrel shifter can be realized. Furthermore, by simply adding a discharge transistor for sign extension required during arithmetic shift, there is an effect that logical shift and arithmetic shift can be selectively realized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a barrel shifter according to an embodiment of the present invention, FIG. 2 is a block diagram of the barrel shifter of the above embodiment, and FIG. 3 is a diagram showing a barrel shifter according to an embodiment of the present invention. A circuit configuration diagram of the second register 2, FIG. 4 is a timing diagram when rotating one bit in the shift circuit of FIG. 1, FIG. 5 is a diagram showing how to process data of various sizes, and FIG. 1 is a diagram showing an example of a conventional 32-bit barrel shifter. l is the 32-bit second register; 2 is the 32-bit second register;
One of the registers serves as an input register for input data, and the other serves as an output register for shift results. 3 is a shift matrix whose shift direction is bidirectional, 4 is an input bus for input data, and 5 is an output bus for shift results. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) Two sets of first and second registers each having a plurality of bits and each bit having one data input/output terminal and one shift data transfer input/output terminal. a bidirectional shift matrix having a number of terminal groups equal to the number of bits of each of the first and second registers;
When the input/output terminal for bit-th shift data transfer and the input/output terminal for M-th shift data transfer of the second register are connected, if N≧M, there is a connection between the connected terminals. A barrel shifter characterized in that one transmission gate is connected, and if N<M, two transmission gates are connected in series between the connected terminals. (2) In the shift matrix, the input/output terminal for transferring the N-th bit shift data of the first register is connected to the input/output terminal for transferring the M-th bit shift data of the second register. If N<M, two transmission gates are connected in series between the connected terminals, and one transmission gate serves as a selector for a logical shift and an arithmetic shift. A barrel shifter according to claim 1. (3) The input/output terminals for shift data transfer of the first and second registers include a precharge circuit, and the shift data transfer is performed using inverted logic. Barrel shifter according to item 1 or 2.