JPH03106216A - Comparator - Google Patents

Abstract

PURPOSE:To prevent generation of an offset voltage without decreasing the output speed by dispersing equally a channel charge when a 1st MOS transistor(TR) short-circuiting input/output terminals of a logic inverter is switched into OFF state. CONSTITUTION:The comparator is provided with a switch S1 leading an input voltage Vref to a capacitor C1 when a 1st MOS TR G1 short-circuiting the input terminal and the output terminal of a logic inverter R1 in response to a control signal is turned on and with a switch S2 leading an input voltage Vin to the capacitor C1 when the switch S1 is turned off. Moreover, the comparator is provided with a MOS TR G2 connecting to the input terminal of a source-drain logic inverter R1 and receiving an inverse of the control signal to its gate and with a 2nd capacitor C2 connecting to an output terminal of the logic inverter R1 via a MOS TR G3 to disperse the electric charge stored in the channel region to the source and the drain uniformly when the MOS TR G1 is turned off. Thus, the generation of an offset voltage is prevented without decreasing the output speed.

Description

[Detailed description of the invention] [Table of contents] Overview (Fig. 1) Conventional technology (Figs. 4, 5, and 6) Problems to be solved by the invention (Fig. 5) Problems to be solved by the invention Means (Fig. 1) Effect (Fig. 1) Embodiment (1) First embodiment (Fig. 2) (2) Second embodiment (Fig. 3) Effects of the invention [Summary] Binary information Regarding the technology for eliminating or mitigating the offset voltage that occurs when a MOS device is turned off in a comparator that compares and outputs a signal as a result of the comparison, the present invention relates to a technology that eliminates or alleviates the offset voltage that occurs when a MOS device turns off, without reducing the output speed of the comparator.
A first capacitor (C1), a logic inverter (R1) whose input end is connected to one end of the first capacitor (C1), and the logic inverter (R1) for the purpose of preventing the generation of offset voltage. ) A first MOS transistor (G1) that short-circuits the input terminal and output terminal of the circuit in response to a control signal.
and when the first MOS transistor (G1) is turned on, the first
A first input voltage (Vref.
), and when the first switch (St) is turned off, the first capacitor (
A second input voltage (Vin) is applied to the other end of C1).
The switch (S2) has a channel area approximately half that of the first MOS transistor (G1), and has a source 1 and a drain connected to the logic inverter (R
A second MOS transistor (G2) is connected to the input terminal of 1) and receives an inverted signal of the control signal at its gate, and a second MOS transistor (G2) which is connected to the input terminal of , the third MOS transistor (
a second capacitor (C2) connected to the output terminal of the logic inverter (R1) via the logic inverter (R1), and the third MOS transistor (G3) is controlled by a signal obtained by delaying the control signal. It is structured as follows.

[Industrial application field]

The present invention relates to improvements in comparators. Specifically, in an inverter to which an input signal is input via a capacitor, and a comparator configured with a MOS transistor as a switch that shorts the input and output terminals of the inverter, the magnitude of two input voltages is compared, The present invention relates to a technique for eliminating or alleviating an offset voltage that occurs when an M○S transistor is turned off in a comparator that outputs a comparison result as a signal.

Conventionally, there has been a circuit (hereinafter referred to as a converter) that compares a certain voltage with another reference voltage and outputs the result.

) is often used, but a MOS transistor is used in this converter as a switch that shorts the input and output terminals of the inverter when a reference voltage is input. However, a problem arises in that an offset voltage is generated due to the clock feed-through when the MOS transistor is turned off, and an error occurs in the comparison result, which affects the comparison accuracy. Comparators are increasingly being used in fields that require even higher accuracy, and the appearance of a comparator that does not generate offset voltage has been awaited.

[Conventional technology]

Hereinafter, a conventional converter will be explained with reference to FIG. First, the circuit structure will be explained.

FIG. 4 is an explanatory diagram of the operation of a conventional converter, showing control signal input terminal Pc, Vin input terminal P fn, Vref. Input end Pref. Three input terminals and one output terminal Pout
and Vref. Transistors SL and S2 are provided in order to switch which of
Vin, Vref. Charge by. or discharged capacitor C1 and inverter Rl (e.g. CMOS
(inverter) in series to reach the output end.

Furthermore, both ends of the inverter R1 are connected in parallel to the source and drain of a transistor G1, which is turned on and off in response to a control signal received at its gate.

Next, ■the input voltage Vin is the reference voltage Vref. If the input voltage Vin is larger than the reference voltage Vref. The operation when the value is smaller than is explained in order. In addition, inverter R
It is assumed that the self-bias voltage at the input and output terminals when the input and output terminals of No. 1 are short-circuited is 2.5V.

■First, Vin=40mV, Vref. =30mV
The case will be explained using an example. First, transistor S1
Turn on the input terminal Pref. The reference voltage Vref.
Incorporate. Meanwhile, in synchronization with this, the transistor S2 is turned off to cut off the input from the input terminal Pin. At this time, the transistor G1 is turned on in synchronization with the turning on of these transistors S1 and the turning off of S2, thereby self-biasing the inverter Rl. Since a voltage of 2.5V is applied to one end of the capacitor C1 from the self-biased inverter R1 side, this capacitor C1 has CI X (2.
A charge of 5 V - 30 mV) is accumulated. This is followed by transistor Sl. 52 are turned off and on at the same time, the voltage Vin is input to the circuit. In synchronization with this, the transistor G1 is turned off.

At this time, the voltage at the other end of capacitor C1 changes from 30a+V to 4QmV, so the voltage at the other end of capacitor C1 (
The voltage at the input terminal of inverter R1 increases by about 10 mV to 2.5V+10mV. In other words, the input voltage of inverter Rl is the input voltage of inverter I? Since the voltage rises by 10 mV from the threshold value of 1, the voltage at the output terminal Pout falls from 2.5V.

■Next, Vin=20mV, Vref. =30mV(D
This will be explained using an example. As in the case (2), it is assumed that a self-bias voltage of 2.5V is applied to the inverter. First, transistor Sl is turned on and input terminal Pref. The voltage Vref. Incorporate. Meanwhile, in synchronization with this, the gate of the transistor S2 is turned off, cutting off the input from the input terminal Pin. At this time, transistor G1 is turned on in synchronization with these transistors 31 and S2. When the transistor S1 is turned on, a charge of CIX (2.5V-30mV) is accumulated in the capacitor Ct. Next, if the transistors S1' and Gl are turned off at the same time, the input voltage Vin
is input to the circuit.

In synchronization with this, the transistor S2 is turned on. At this time, the voltage at the other end of capacitor C1 is from 30 mV to 20 mV.
The voltage at one end of the capacitor drops by about 10 mV. In other words, the voltage on the input side of inverter R1 is 2.5
The voltage at the output terminal Pout drops by 10mV from V and becomes 2.5
rises from v. Through the above operations ■■, the output of the inverter changes as Vin becomes V ref . When it is larger than
It increases from 2.5v and Vin becomes Vref. When the voltage is smaller than 2.5v, the voltage drops from 2.5v. The above is the basic operation of the conventional circuit shown in FIG.

However, when the voltages to be compared are minute like this, the signal amplitude at the output end of the inverter R1 is minute and insufficient as a logic amplitude. Therefore, the circuit receiving the output of this comparator is O. SV or less”
If 3.2V or higher is considered to be "H", it becomes impossible to directly control other logic circuits with the output of the comparator.Therefore, the output of the comparator shown in Figure 4 is usually amplified. A plurality of stages of amplifiers are connected in series to amplify the signal and output it.The circuit shown in Fig. 6 is a comparator based on this conventional technology. A voltage Vtn signal is input from the input terminal Pin, a reference voltage Vref. signal is input from the input terminal Pref., and the gate of the MOS transistor is turned on.
A control signal to be turned off is input, and Vin becomes Vref. Information on whether the signal is larger or smaller is output as "H'" or "L". In the circuit shown in Figure 6, similar amplifiers are connected in four stages to improve gain, but each stage provides a gain of about IO times, so a four-stage configuration can provide a gain of 10' times. It is a structure that can be used.

However, regarding the on/off of transistor G1,
Both the circuit of FIG. 4 and the circuit of FIG. 6 have the following problems. In the following, to simplify the explanation, it is assumed that among the signals input to the control signal input @P, "H" is 5V and "L" is oV.

Now, if a signal of "H" (=5V) is input to the control signal input terminal P, a channel is generated under the gate electrode of the transistor. After this, the control signal input terminal P
When an 'L' (=OV) signal is input to c, the channel disappears and the charge in the channel region is transferred to the transistor Gl.
are distributed between the source and drain regions. Therefore, at the point where the input terminals of capacitor c1 and inverter Rl shown in FIG. 4 and the source terminal of transistor G1 are connected to each other, charge is released from the channel region when transistor G1 changes from on to off. This changes the voltage at the input terminal of the self-biased inverter R1 (that is, a so-called offset voltage occurs), which impairs correct voltage comparison of the converter.

As a means to solve this problem, a structure is known in which a circuit is provided with a portion that absorbs the charge injected from the channel region of the transistor G1 to the source side.

This will be explained with reference to FIG. FIG. 5 is an explanatory diagram of the operation of the first stage circuit of this improved converter.
In the figure, parts that are the same as those in FIG. 4 are indicated by the same symbols.

In FIG. 5, in addition to the structure shown in FIG. 4, an inverter R2 is connected between the source and gate of the transistor G1 from the gate side.
, a capacitor C2 consisting of a MOS transistor whose source and drain are short-circuited, and whose channel region area is approximately half that of the transistor G1.
This is a structure in which these are connected in series.

The operation of the circuit shown in FIG. 5 will be explained below. "H" to the control signal input terminal PC connected to the gate of the transistor Gl
It is assumed that a signal is input and the transistor Gl is turned on. At this time, the inverter R is connected to the terminal of the capacitor C2.
An "L" signal is applied through the two terminals. Thereafter, an "L" signal is input to the control signal input terminal PC to turn off the transistor G1. At this time, an "H" signal is applied to the gate of the transistor constituting the capacitor C2 with a delay corresponding to the time required to pass through one inverter. As a result, a channel is created in the MOSI transistor, forming a capacitor between the gate and the channel. The charge discharged from the channel of the transistor Gl to the source side is absorbed by this capacitor C2. MO to make capacitor C2
Since the channel area of the S transistor is approximately equal to half of the channel area of the transistor G1, this transistor G
All charges released from the channel of G1 to the source side of transistor G1 are stored in capacitor C2. That is, all the excess charge that causes the offset is absorbed by the capacitor C2, so that the problem of offset voltage occurring when the transistor G1 changes from on to off can be solved.

[Problem to be solved by the invention]

However, the method of connecting the capacitor C2, which is made up of a transistor having a channel region half as large as that of the transistor G1, to the source side of the transistor G1 as described above does not allow the channel of the transistor G1 to be connected to the source side. It is assumed that charge is released evenly to each drain side. However, in reality, it is impossible for charges to be completely evenly released from the channel of the transistor G1 toward the source and drain.

This is because the impedance is different between the source side and the drain side of the transistor G1. Therefore, even if offset voltage compensating means as shown in FIG. 5 is used, the occurrence of offset voltage cannot be completely prevented. When comparing weak voltages using a converter using such a circuit, even a slight offset voltage is critical to accuracy.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to prevent offset voltage from occurring in a converter without reducing the output speed.

[Means to solve the problem]

In order to achieve such an objective, the present invention employs the following precepts as means.

A first capacitor (C1), a logic inverter (R1) whose input end is connected to one end of the first capacitor (C1), and control between the input end and the output end of the logic inverter (R1). A first MOS transistor (G1) that shorts in response to a signal.
and when the first MOS transistor (G1) is turned on, the first
A first input voltage (Vref.
), and when the first switch (S1) is off, the first capacitor (
A second input voltage (Vin) is applied to the other end of C1).
The switch (S2) has a channel area approximately half that of the first MOS transistor (G1), and the source and drain are connected to the logic inverter (R1).
), the second MOS transistor (G2) receives an inverted signal of the control signal at its gate, and the second MOS transistor (G2) receives the charge accumulated in the channel region when the first MOS transistor (G1) is turned off. In order to distribute it evenly to the drain side, the third MOS transistor (G
3), the third MOS transistor (G3) is controlled by a signal obtained by delaying the control signal. It is structured as follows.

[Effect]

That is, in the present invention, when the first MOS transistor that short-circuits the output terminal of the logic inverter is switched off, the second capacitor is connected to the output terminal of the logic inverter via the third MOS transistor. The accuracy of offset compensation is improved by balancing the impedance on the source and drain sides of the transistor to evenly distribute the charge on the channel. By turning OFF, the subsequent changes in the comparator output are prevented from being delayed.

〔Example〕

In the following, the present invention will be explained based on a plurality of embodiments.

(1) First Embodiment FIG. 2 is an explanatory diagram of an integrated circuit using the comparator of the present invention. This shows the case when applied to a circuit. In addition, Figure 4 in the figure,
The same parts as in FIG. 5 are indicated by the same symbols. In such a converter circuit, to improve the gain,
Four stages of similar circuits are connected in series, and each of the circuits in each stage operates in the same manner as in FIG. In Fig. 2, the input terminals are a control signal input terminal Pc, a Vin input terminal Pin,
Vref, input end Pref. In addition, an output terminal Pout is provided as an output terminal for outputting the result. Note that if the control signal PC is input to each stage at the same time, the problem of offset voltage generation described above will occur at the same time in each stage, and even the offset voltage will be amplified by the number of stages, which is bad. . By slightly shifting the input of the control signal Pc for each stage, the offset voltage generated in the first stage is not transferred to the subsequent stage, and superimposition with the offset voltage generated in the next stage can be avoided. Based on this idea, in the comparator circuit shown in Figure 2,
A delay circuit consisting of several inverters connected in series is provided between each stage of the control signal line.

In this circuit, when the comparison result signal is output from the inverter R1, a charge corresponding to the comparison result signal is stored in the capacitor of the next stage circuit connected to the inverter R1. The second-stage circuit also operates in the same way as the first-stage circuit due to the charge pushed out or attracted into the second-stage circuit as a result of this change in the amount of charge. The inverter connected to the capacitor in the second stage circuit amplifies the signal in the same way as the inverter in the first stage circuit, and this signal is further transferred to the third stage circuit. This follows and an amplified signal is taken out at the output Pout.

The reason why the present invention was able to eliminate the conventional problem of offset voltage will be explained. Conventionally, the cause of the offset voltage has been that the charges injected into the circuit from the source and drain ends of the transistor Gl are not equal. In the present invention, first, the source end of the transistor G1, which is a problem in the first stage circuit of the converter shown in FIG.
The impedances at the drain ends (2) are designed to be approximately equal to each other. Therefore, the sum of all capacitors connected to this source end (C1+C2+C I1)
(Here, the capacitor CIL indicates the parasitic capacitance between the source and gate of the transistor Gl.) and the drain terminal
The structure is such that the sum of all capacitors connected to is balanced.

According to the circuit of FIG. 1 described above, the inverter R
1 input end. Since the total amount of capacitors connected to each output terminal is set to be equal to each other,
No offset voltage occurs.

However, in the inverter R1 having a high amplification factor, the impedance Z1 of the inverter R1 itself is also large. Due to the existence of this impedance z1, a potential difference occurs between both ends of the inverter R1 (the source end and the drain end of the transistor G1), and charge injection is not performed evenly. In a transient state where transistor ct transitions from on to off,
The source and drain terminals of the transistor G1 (ie, the output terminal of the inverter R1) have the same impedance, and the present invention attempts to maintain this state. For this explanation, reference will be made below to FIG. 1, which is a diagram illustrating the operation of the first stage circuit of the converter of the present invention.

When the transistor 61 is turned off, even if the signal applied to this gate simply changes from "H" to "L" as shown in the figure, the connection point P! The waveform observed at , as shown in the figure, drops sharply and then gradually recovers to a voltage close to the "H" level. That is, at the connection point P2, the voltage does not fall to the "L" level even after the transistor G1 is turned off, and current flows from the connection point P2 toward the inverter R1. In order to eliminate this change in waveform and make it similar to the waveform of the signal applied to the gate of transistor G1, the time for transistor G1 to switch from on to off, that is, the time constant, must be set at the falling edge of the signal at connection point P2. It is designed to be significantly smaller than the time. First, the time constant at this connection point Pg is the impedance Z1 of the inverter R1 connected to this connection point, the capacitor C2, the capacitor C3, the source of the transistor G3, which is also connected to this connection point,
Parasitic capacitance C between the gates IL+ and parasitic capacitance C between the gate and drain of transistor G3? The sum of the capacities of (C2
+c3+CIL+C+■). That is, the time constant τ at the connection point P2 is T <
Zl (C2 + C3+ C IL + C I R
) to satisfy.

According to such a structure, the above-mentioned problem of waveform change can be solved.

On the other hand, in the circuit structure, compared to the conventional improved circuit shown in FIG.
A new feature is that the drain terminal of this transistor G3 is grounded (connected to a reference voltage) via a capacitor C2. In this way, connection point P2
Since a part of the capacitor connected to P2 is placed between the reference voltage and the reference voltage, this capacitor can be disconnected during the comparison operation without affecting the comparison operation of the circuit, and the total amount of capacitors connected to the connection point P2 can be reduced. I can do it. In order to adopt this new circuit structure, first the reference voltage Vref.
is input to the circuit, then the transistor G
1 is on, and transistor G3 is on.

Therefore, the reference voltage Vref. As long as C2 is input to the circuit, capacitor C2 is electrically connected to the circuit. Thereafter, when the voltage ■in is input to the circuit, the transistor G1 is turned off and a signal indicating the comparison result appears at the output side of the inverter R1. However, since the load at the connection point P2 is large, the potential difference between the "H" signal and the "L" signal becomes small, resulting in a delay in outputting the comparison result to the output terminal Pout. According to the above circuit configuration, the transistor G3 is turned off after a delay of the time required to pass through the two inverters from the fall of the control signal (that is, after the transistor G1 is turned off and an offset voltage is generated).

At the instant when the comparison result is output, the capacitor C2 is electrically disconnected from the circuit, and the load at the connection point P2 is reduced, so that the comparison result is quickly sent to the output terminal Pout.

As already mentioned, when the potential difference between the two signals to be compared is small, the "H" signal and "L" signal output from the first stage circuit (the part surrounded by the dotted line) The potential difference is also small. Except for the operation of the first stage circuit, this circuit is the same as the conventional circuit shown in FIG. In this circuit, the signal is amplified by the amplifiers in the subsequent circuits, so like the circuit in Figure 6, even though the voltage to be compared is extremely small, it must be operated with the output of this converter. This is effective when the logic amplitude of the circuit threshold is large.

(2) Second Embodiment FIG. 3 is an explanatory diagram of an integrated circuit according to the second embodiment of the present invention. Basically, the value of Vin can be varied at the input of the circuit of FIG. 1. The structure is equipped with a resistance ladder RB. Note that the symbols in the figure indicate the same parts as in FIGS. 2, 4, and 5, and a voltage +Fs is applied to one end of the input side, and a voltage -Fs is applied to the other end. Also,
The terminal to which the voltage used for comparison is input is grounded to the reference voltage v0 (voltage given by analog ground), and has a control signal input terminal Pc, and is almost the same as the circuit shown in FIG. .

In this circuit of Fig. 3, the maximum value 10 F is used instead of the voltage Vin.
The structure is such that any value can be selected between s and the lowest value 1 Fs according to instructions to the gate of the transistor. For this purpose, in the circuit of FIG. 3, the circuit of FIG. 1 is replaced with a resistor lug RB in which a large number of resistors are connected in series, in the part where the transistor G1 and the Vin input terminal Pin are connected. Both ends of this resistance ladder RB are connected to the signal 1Fs that gives the highest voltage and the signal 1Fs that gives the lowest voltage, and each connection point between the resistors that make up this resistance ladder RB has a The source ends of the transistors prepared one by one are connected to each other. Furthermore, the drain end of each of these transistors is connected to the same capacitor C1, and the gate of each transistor is opened and closed in response to slightly different control signals to change the resistance value and vary the input voltage VinO value. In this circuit, the voltage used as a reference for comparison is taken as VAG (voltage corresponding to analog ground).

On the other hand, any one of the MOS transistors connected to the resistance ladder RB is turned on and the others are turned off between the lowest voltage 1Fs connection end and the highest voltage 1Fs connection end. By varying the MOS transistor that is turned on, the lowest voltage is 1 Fs and the highest voltage is 10 Fs? Any voltage between can be compared. When turning on any one of the transistors connected to this resistance ladder R8, the inverted signal of the same control signal turns off the transistor connected to the input terminal of the reference voltage. Therefore, the transistor G1 is turned off. When this control signal is inverted, each transistor maintains this inverted state. First, when the reference voltage V■ is input to the circuit, some charge is stored in the capacitor C1. Next, when the control signal switches from "L" to "H" and any voltage between this minimum voltage 1Fs and maximum voltage 10Fs is input to the circuit, the voltage initially stored in the capacitor C1 Depending on whether the charge is larger or smaller than the charge, the charge flows from the capacitor CI toward the inverter R1, or from the inverter R1 toward the capacitor C1. From this, on the output side of inverter R1, "H"
II or "LI+" signal is output.

Since this circuit can compare any voltage with the reference voltage between the highest voltage value corresponding to the signal 10 Fs and the lowest voltage value corresponding to the signal 1 Fs, it is suitable for applications such as the output circuit of a D/A converter. be. Although the features of the present invention have been explained using the above two embodiments, the present invention is not limited to these two embodiments and can be freely modified. For example, an inverter can be used as a logic inverter instead of an inverter, and can be widely applied to comparison circuits. Furthermore, all of the four stages of comparison circuits that replace the comparator circuits shown in the first embodiment may be replaced by the circuits shown in FIG. In this case, the detection accuracy is naturally improved compared to the case where the circuit shown in FIG. 1 is used only in the first stage circuit.

〔Effect of the invention〕

According to the present invention, it is possible to construct a converter circuit in which the offset voltage is considerably reduced or completely prevented, and it is possible to determine whether a certain voltage value is higher or lower than a specified voltage value with higher accuracy than before. There is.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the operation of a converter according to the present invention, FIG. 2 is an explanatory diagram of an integrated circuit according to the present invention, and FIG. 3 is an explanatory diagram of an integrated circuit according to an embodiment of the present invention. FIG. 4 is an explanatory diagram of the operation of a conventional converter, FIG. 5 is an explanatory diagram of the operation of an improved conventional converter, and FIG. 6 is an explanatory diagram of an integrated circuit according to the prior art. Vin...first voltage, Vref. ...Second voltage, Pin...First input terminal, Pref. ...
Second input terminal, Pout...output terminal, Pc...
Control signal input terminal, Pi...connection point, P2...connection point, P3...connection point, P4...connection point, S
t...Transistor (switch), S2...Transistor (switch), G1...Transistor (1st M
OS transistor), G3...transistor (3rd M
OS transistor), c1... Capacitor (first capacitor), G2... Second MOS transistor, Rl
... Inverter (logic inversion H), R2... Inverter (second logic inverter), R3... Inverter (third logic inverter), RB... To resistance ladder>

Claims (1)

[Claims] A first capacitor (Cl), a logic inverter (R1) whose input end is connected to one end of the first capacitor (C1), and an input end and an output of the logic inverter (R1). a first MOS transistor (G1) that short-circuits the terminal in response to a control signal;
and when the first MOS transistor (G1) is turned on, the first
A first input voltage (Vref.
), and when the first switch (S1) is off, the first capacitor (
A second input voltage (Vin) is applied to the other end of C1).
The switch (S2) has a channel area approximately half that of the first MOS transistor (G1), and the source and drain are connected to the logic inverter (R1).
), the second MOS transistor (G2) receives an inverted signal of the control signal at its gate; In order to distribute it evenly to the drain side, the third MOS transistor (G
3), the third MOS transistor (G3) is controlled by a signal obtained by delaying the control signal. A comparator characterized by: