JPH03105644A - Access control system for virtual storage address space - Google Patents

Abstract

PURPOSE:To obtain a high cost performance by executing an access register (AR) conversion exception processing and an AR conversion test processing by an emulating routine. CONSTITUTION:In the case an access register conversion impact mechanism (ALB) 4 does not hit in the course of executing a general instruction, or in the case an AR conversion test instruction is executed, an AR process latch 6 is set by a microprogram routine actuated in an instruction execution control part 5. In the case an exception is detected in the course of AR conversion, a program interruption emulating routine 11 is called. The emulating routine 11 refers to program interrupting information 12 and emulates a prescribed processing. In such a way, an AR conversion processing is realized without causing an increase of a hardware and a complication of a control circuit, and a high cost performance can be obtained.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a virtual memory address space access control method for referencing data in an arbitrary address space in an information processing device having a virtual memory device consisting of a plurality of address spaces. The aim is to realize access register conversion processing without increasing the amount of hardware and complicating the control circuit, and to obtain high cost performance. Means for indicating that the conversion process is being performed during the access register conversion process for determining a segment table origin (s"ro) that specifies an address space by the contents of the access register indexed by the pace register number of the instruction. If a program interrupt exception is detected during the conversion process, the information is retained and stored along with the program interrupt code that identifies the exception in the main memory area where the program interrupt emulation routine runs. Constructed.

[Industrial application field]

What is the present invention? This paper relates to a virtual memory address space access control method for referencing data in arbitrary address spaces in an information processing device having a virtual memory device consisting of Jl number of address spaces. In recent years, demands on information processing devices have exceeded the limits of address space in conventional virtual storage devices. What is desired is an architecture that allows a user program to directly access data in multiple address spaces. The present invention is. One control means for that purpose is provided.

[Conventional technology]

In a conventional virtual storage information processing device, as shown in FIG. 3, only access to data within a single address space specified by a control register (CRI) is permitted. Therefore, in order to refer to data in multiple address spaces, the control register (CR
It was necessary to replace the contents of I), which was under the control of the operating system. Under these circumstances, user programs were not allowed to directly process data across multiple address spaces.

However, in response to the demand for expansion of virtual memory space, it has become necessary to allow user programs to directly access the address space determined by the base register number.

For this reason, the following methods can be considered as a mechanism.

That is, for multiple address spaces used by the user, an access list that specifies those spaces and a segment table corresponding to each space are prepared, and multiple segment table origins (ST○) that are pointers to the table are prepared. Which ST○ is used is determined based on the contents of the access register indexed by the Heath register number used in the access.

The outline will be explained with reference to Fig. 4. First, the access register number 22 specified by the base register number specified by the instruction 21 is selected, and the access list entry token ALET of its contents is used to index the access list 23 placed in the real storage space. The information in the access list 23 is information that specifies STOs, and one STO 24 is selected accordingly. This is to determine the segment table 25. However, the method shown in Figure 4 requires time to refer to the access list. To further speed up the access, a translation buffer ALB is usually introduced which stores part of the contents of the access register and the STO in pairs.

FIG. 5 shows an overview of such a conversion buffer A-structure ALB.

In FIG. 5, ALB 27 is 5 access registers 22
A part of the contents of ALET (access list entry token) and STO are registered as a pair. When the access register 22 is selected using the base register number taken out from the instruction 21, the ALB 27 is searched using the ALET of its contents. If ALB27 hits. The STO is extracted from the read data. If there is a mishit, ALET is used to refer to the access list and obtain a STO.

Here, the access list in the real storage space is indexed according to the contents of the access register, and the result is transferred to the conversion buffer mechanism ALB.
If you try to implement all the functions for registering using hardware, the amount of hardware will increase significantly. Also, in the above conversion process, the functions required when indexing the access list in the real storage space are as follows. Fetching data.
Since the functions are similar to existing hardware functions such as checking bits and comparing numbers, if a dedicated circuit is provided, it would be wasteful to have duplicate similar circuits. In order to further test the above conversion process. An instruction is required to report exceptions found during conversion using condition codes and insert conversion exception identification codes into specified registers. The control circuit for executing such instructions is.
It becomes extremely complicated. For example, such instructions include the following instructions called TAR instruction, LRA instruction, and TPROT instruction.

The TAR command is a command that tests a newly created access list. Specify and index ALET information. This is to check whether the results are correct or not. The LRA instruction is an instruction to obtain a real address from two virtual addresses. Issued to test whether the OS can use a certain virtual address.
If the virtual address is not available. If a conversion exception occurs, it responds with a condition code CC and stores the address in the specified register. And the TPROT command is. This is a command to test whether the result of specifying a protection key is correct or not. (Problems to be Solved by the Invention) The present invention solves the problem that access register conversion causes an increase in hardware and a complicated control circuit in a virtual memory information processing device that refers to data existing in multiple address spaces. The purpose is to achieve high cost performance by realizing access register conversion processing without any need for access register conversion processing. (Means for solving i!Ha) The present invention provides a translation buffer mechanism (A
LB) and the process of referring to the access list of the real storage space and registering it in the ALB at the time of a hit, TAR, LRA, TP
Control of access register conversion test instructions such as ROT,
This is achieved by using existing hardware circuits. Figure 1 is a diagram of the principle of the present invention. l is an instruction processing device.

2 is. This is an instruction register. 3 is an access register (AR). 4 is an access register conversion buffer (ALB). 5 is an instruction execution control unit operated by a microprogram routine. 6 is an AR process latch (AR-PROC-LcH) that indicates that the access register conversion process is in progress. 7 is the program interrupt code (PGM IC). 8 is a main storage device.

9 is an access list. 10 is. This is the emulation routine running area. 1] is a program interrupt error routine. l2 is. This is program interrupt information. The instruction execution control unit 5 sets the AR process latch 6 to ON when the ALB 4 misses in the AR conversion process and when executing AR conversion test instructions such as TAR, LRA, and TPROT.
This means that the AR conversion process is in progress. Also, when the conversion process ends or the execution of the AR conversion test command ends, the AR
Reset process latch 6 to OFF. Program interrupt code 7 has a flag (T bit) indicating an AR conversion exception and a flag (S bit) indicating that an AR conversion test instruction is being executed. The value is set when each event occurs. Program interrupt information I2 is . Contains program interrupt code and identification information of AR conversion test command.
Set when a program interrupt occurs.

The program interrupt emulation routine 1l is activated by a program interrupt when an AR conversion exception occurs during the execution of a general instruction and when an AR conversion test instruction is executed, and emulates a predetermined process by referring to the program interrupt information ful2.

[For production]

In Figure 1, during the execution of a general instruction, if the translation buffer (ALB) in which a part of the contents of the access register and ST○ are registered as a pair does not hit, or if an instruction for testing AR translation ( When a TAR, LRA, TPROT instruction, etc.) is executed, the AR process latch is set by a microprogram routine activated in the instruction execution control unit 5. If an exception is detected during AR conversion, a flag (T bit) indicating that it is an exception during AR conversion, and
A flag (S
bit), the program interrupt code that identifies the AR conversion exception, and the program interrupt emulation routine are stored in the main memory area where the program interrupt emulation routine runs, and the program interrupt emulation routine is called. In the program interrupt emulation routine, if there is a T bit and no S bit, a normal program interrupt is emulated, and if there is a T bit and an S bit, the condition code is changed and converted. Insert the exception identification code into the specified register and emulate the AR conversion test instruction. [Embodiment] Figure 2 shows a hardware configuration according to an embodiment of the present invention. The illustrated circuit is the W cycle of the instruction execution pipeline (
This figure shows the main structure of the D, A, T, B, E, and W cycle pipeline.

WXC is Exception' of W cycle: 1-
WXV (W Ex
When there is a ceptionVa item d), its contents are shifted and held in the PGMIC register. From there, it is stored in main memory.

The AR PROCESS latch is set and reset by the instruction execution control microprogram.
PC as T bint with WXC when there is MIC
Stored in a register, indicating that an exception was detected during AR conversion. Also, AR PROCESS latch and W
The XV signal causes W NULLIFY{. The t number is generated. Prohibits updating of PSW JAR and invalidates it.

The W-OPCODE is shifted to the NR OPCODE register, held, decoded, and stored in main memory. Also, W-OPCODE is directly decoded. T/M? ，
When an AR conversion test command such as LRA or TPROT is identified, the S bit of the PGMIC register is set and the AR
Indicates that the conversion test command has been executed. The T bit on the PGMIC register is FORCE-HP
Activates the V ON-PX signal and switches the state to the state in which the program interrupt emulate routine runs (hypervisor HPV mode).

〔Effect of the invention〕

As described above, according to the present invention, when an exception is detected during AR conversion or when an AR conversion test instruction is executed, necessary information can be stored in the main memory, and the interrupt emulate routine can be efficiently processed. Control can be passed. Due to this. ARil9 exception handling and A
Since it is possible to execute R conversion test processing, it is possible to realize a virtual memory type information processing device that can operate multiple address spaces with good cost performance.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention. FIG. 2 is a hardware configuration diagram according to an embodiment of the present invention, and FIG. 3 is an explanatory diagram of an address space designation method using a conventional control register. FIG. 4 is an explanatory diagram of a conventional AR conversion processing method that specifies an address space using an access register, and FIG. 5 is an explanatory diagram of a conventional AR conversion loose IIi mechanism. In Figure 1, 1: Instruction processing device 2: Instruction register 3: Access register (AR) 4: Access register conversion buffer mechanism (ALB) 5
: Instruction execution control unit 6: AR process latch (AR-PROC-LClf) 7: Program interrupt code 8: Main storage device 9: Access list 10: Emulate routine running area 11: Program interrupt Emulate routine 12: Program interrupt information

Claims (2)

[Claims] (1) When determining the effective address for the main memory operand of an instruction from the base, index, and displacement in a virtual memory information processing device that references data existing in multiple address spaces by access register conversion using access registers. means for indicating that the conversion process is being performed during an access register conversion process for determining a segment table origin (STO) specifying an address space by the contents of an access register indexed by a base register number used for the process. and when a program interrupt exception is detected during the conversion process, by retaining that information and storing it along with a program interrupt code identifying the exception on a main memory area in which a program interrupt emulation routine runs.
A virtual memory address space access control method characterized by causing a program interrupt emulation routine to efficiently handle exceptions. (2) In claim (1), a program interrupt exception occurs when the translation buffer (ALB) that uses access registers does not hit when executing a general instruction, and when a predetermined access register translation test instruction is executed. A virtual memory address space access control method characterized by: