JPH03104083A - Refresh control system - Google Patents

Abstract

PURPOSE:To apply an optimum refresh system corresponding to the presence and absence, etc., of interruption by providing a distributed refresh control part and a concentrated refresh control part and selecting respective refresh requests to be outputted. CONSTITUTION:A distributed refresh request signal 13 and a concentrated refresh request signal 14 are respectively independently outputted by a distributed refresh request part 2 and a concentrated refresh request part 3. A CPU 1 writes the selection information of the refresh system to an I/O register 4 by using an I/O write signal 11 and a refresh system selection part 5 selects one of the two refresh request signals according to a refresh system select signal 15 and outputs a refresh request signal 16. Thus, when a program requires a response at real time, the distributed refresh system is selected and when the hit rate of a high-speed access mode for a dynamic memory is desired to be high, the concentrated refresh system can be selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a refresh control method for a dynamic memory in an information processing device such as a personal computer or a word processor.

[Conventional technology]

2. Description of the Related Art In information processing devices such as personal computers and word processors, dynamic memories (hereinafter abbreviated as DRAMs) are widely used as storage devices due to their integration density, cost, etc.

1) RAM requires a refresh operation to be performed on memory cells in order to retain memory contents.

Although it depends on the device, the number of refresh cycles required within a certain period of time is generally specified, such as 256 refresh cycles for 4++a and 512 refresh cycles for 1 or 8 mwg. Figure 4 shows an example of the conventional glue freshening tool control method. This refresh control method, as shown in Figure 4,
The PU 1 and the memory 10 are provided with an access request arbiter 6, a reflex counter 7, a RAS/self η generation section 8, and a multiplexer 9 and flexi 3L request section 26.

The memory glue flex operation is performed as follows. The reflexion request section 26 outputs the refreshment request signal 16, and the reflexion counter 7 generates the refreshment tool address 22.

The access request arbiter 6 receives the refresh request signal 1
6 and the memory access request signal 12 which is an access request from the CPU 1 to the memory 10.5.
In DRAM, stored information corresponds to the presence or absence of charge on a capacitor. Therefore, if the refresh operation is not performed at the specified time, the charges will be discharged and the stored information will be lost. Therefore, the access request arbiter 6
If an access to the memory 10 of the PU 1 and a refresh request occur at the same time, the reflex S request signal 16 is given priority. When the refresh request is accepted, the access request arbiter 6 outputs the refresh cycle signal 17 and the memory cycle activation signal 1B.

? Address Strope (hereinafter abbreviated as RAS) and Column Address Stroke (hereinafter abbreviated as CAS) generation unit 8
(hereinafter abbreviated as the 1st row/τ row generation section) is driven by the memory cycle start signal 18, and the RAS 19a and CAS
Generate 19k. Multiplexer 9 outputs refresh share address 22 as memory address 20 in response to refresh cycle signal 17 .

When the reflex shake is completed, the reflex counter 7 counts up to indicate the next refresh address.

In FIG. 4, the refresh crystal requesting section 26 sends a refresh request signal 16 so as to satisfy the reflex regulation.
However, in that method, for example, 256
When performing a refresh cycle, there are the following two methods. One method is to allocate 256 cycles evenly between the four shoulders and perform a refresh cycle once every approximately 15.6 μ kick (#4 Rinko/256) (hereinafter this method will be referred to as the distributed refresh method). ). The other method is a method in which 256 cycles of refresh are performed continuously every 4 asec (hereinafter, this method will be referred to as an intensive refresh method). In general, the distributed reflex type is often used. f. In an actual system, there are a FURAN row/column address multiplexer and an address multiplex signal, but these are omitted here.

Figure 5 shows an example of a timing chart for the distributed refresh method. The refresh request signal 16 is sent out at intervals of 15.6μ, and is sent to memory address 2 at the falling edge of 1πf S19a.
The memory cells indicated by 0 are refreshed.
Memory address 20 is added every refresh cycle, and 256 refresh cycles are completed in 4 ssec. Figure 6 shows an example of a timing chart for a different intensive refresh method. The refresh request signal 16 is output every k cycle times required for one flexié cycle, and the refresher is performed 256 times in succession.

With this method, one cycle time is approximately 300+ss
ec, 256 refreshes are completed at approximately 768μ flags, and after 4 repetitions, refresh request signal 16 is sent and refresh is started.In the distributed refresh method, CPU 1 memory access Even if there is a conflict with the refresh, the CPU 1 can access the memory 10 once one refresh cycle is completed.

In the intensive refresh method, after 256 consecutive Nori Freshier cycles, it takes approximately 5 hours until the next Nori Freshener.
During this period, the CPU 1 can access the memory 10 without conflicting with refresh.

General known examples of reflexure include JP-A-62-165790, JP-A-60-1265594, and the like. [Problems to be Solved by the Invention] The above-mentioned conventional techniques each have the following problems.

That is, in the distributed reflexine method, since the refresh interval is as short as 15.6 μm, the CPU 1's access request to the memory 10 tends to compete with the refresh device request. For example, as shown in Figure 7, tgDRA
This is especially a problem when DRAM is used in high-speed access mode, such as page mode operation of M. Page mode works as follows. In FIG. 7, data 30, although not shown in FIG. 4, is data that the memory 10 outputs to the data bus of the system. At time T1, a memory access request signal 12 is sent, and the first access is started. tzu, iko1”19
At the falling edge of g, the value of memory address 20 is taken in as a row address, and at the falling edge of CAB19h at time ja+rt, the value of memory address 20 is taken in as a sum address, and data 50 is output at time TI.

After this, in normal operation, RAS 19@, CAS 1
9k both return to the high level once, but if the row address of the next memory access is equal to the row address of the previous access (hereinafter referred to as base hit), the time T
4, RAS 19g remains at low level. All you need to do is to return only CAS 19b to high level and then bring it down again to capture only the new column address. Page hit? ．． In this case, there is no need to change the RAS 19g, so the time from access start to data output is shortened.

In this way, the condition for page mode operation is that the row address is the same in consecutive accesses, and if the row address is different from the previous access, page mode operation is not possible and normal operation is resumed. (This is called a page miss hit.)

At time Ts, when the 7 rex request signal 16 is sent during the page mode operation, the refresh operation is performed with priority. However, at this time, there is no relationship between the row address that was currently being accessed in the cabinet and the refresh address, so it is the same as a page miss. RAS1
9α and CAS 19A need to be returned to high level. Thereafter, at time T6, -RAS19m falls, refresh memory address 20 is fetched, and 7 less cycles are performed. The next access starts from time T. Here, time T.
Even if the row address fetched at time T is equal to the row address fetched at time T,
Since memory address 20 for refresh has been taken in, it is necessary to return RAS 19g to the high level once as shown at time ra in case of a page miss.As mentioned above, in the distributed reflex method, There is a problem in that the number of mishits such as page mode operation is high.

Oh, as for things related to page mode, please refer to Japanese Unexamined Patent Publication No. 6
There is a publication No. 1-42793. On the other hand, in the intensive refresh method, the refresh. Because the period without tx. < , which is advantageous in terms of performance.

However, in this concentrated refresh method, since the refresh island priority is high, once refresh starts, 25
As long as all 6 refreshes have been completed and the color is red, CPU 1 cannot access the memory.For this reason, if an interrupt processing request is made to CPU 1 from external power 1 during the 7' refresh period, it may be forced to wait for a long time. , may not be accepted, and the responsiveness of the system will deteriorate. This is particularly a problem in tx processing where a response is required within a limited time such as communication. In recent years, laptops;? Increasingly, systems are powered by batteries, such as small-sized computers. By the way, it is known that the discharge characteristics of dry batteries are that intermittent discharge has a longer discharge duration than continuous discharge. When such a device uses the distributed refresh island method, the refresh island current flows at short intervals of 15.6μ, so the battery enters a sustained discharge state and the electric oil is consumed more quickly than the concentrated refresh island method. It is considered a thing. In this way, in the conventional method, if the dispersion 7 less delta method is adopted with priority given to system responsiveness, the hit rate in DRAM high-speed access mode decreases, and battery consumption in battery-driven systems is reduced. There is a problem that the problem occurs quickly. On the other hand, if the centralized refresh method is adopted, there are problems such as interrupt processing requests during the refresh period having to wait for a long time or not being accepted.

An object of the present invention is to provide a refresh control method that can apply an optimal flexié method depending on the presence or absence of an interrupt in a running program. Another object of the present invention is to provide a refresh control method that reduces battery consumption in a system driven by batteries, bacteria, etc. Still another object of the present invention is to provide a refresh control method that reduces the number of misses when a DRAM is operated in a high-speed access mode such as page mode operation.

[Means to solve lI@]

In order to achieve the above object, the present invention provides two reflexion requesting sections, a distributed reflexion & requesting section and a centralized reflexion requesting section, and further includes refresh method selection means. This refresh method allows you to select either a distributed method or a centralized method. The above selection can be made, for example, by writing the running status of the application program detected by the CPU, etc., into information holding means such as an I/Q register, and based on the written information, the reflex one-way selection means can be set to a distributed refresh method or a centralized refresh method. This can be done by selecting one of the refresh methods.

Further, the present invention provides a means for detecting connection of an external device that requires interrupt processing and responsiveness, detects the presence or absence of the connection, and a refresher method selection means selects either the distributed refresh island method or the centralized refresher method. Refresh 1
It is possible to plan to do this. Furthermore, the present invention provides means for detecting the type of drive power source, and the reflex three method selection means selects either the distributed refresh method or the concentrated refresh island method depending on the type of power source, and performs the refresh island. It can be configured as follows.

Furthermore, the present invention provides a configuration in which a means for detecting an interrupt request from an externally connected device is provided, the presence or absence of the interrupt request is provided, and the refresh island method selection means selects either the distributed refresh method or the centralized refresh method to perform refresh. It is also possible to do this. [Operation] The distributed reflex & request section and the centralized refresh request section are
A distributed refresh request and a centralized refresh request are sent independently. The CPU detects the running status of the application program, such as whether or not it is jammed. When the program requires real-time responsiveness, the refresh method selection means selects the refresh method JL1! from the distributed reflexia requesting section. Select your request. When it is desired to increase the hit rate of the DRAM high-speed access mode, a refresher request is selected from the intensive refresh request section.

The selection method is to switch based on information written by the CPU to an I/O register or the like. Alternatively, the presence or absence of an externally connected device that outputs an interrupt signal, the presence or absence of an interrupt signal from the externally connected device, the type of power supply, etc. may be detected by a device detection section, a power supply detection section, etc., and switching may be performed based on that information. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In addition, in each embodiment, the same structures or elements are denoted by the same reference numerals, and redundant explanation will be omitted.

The embodiment shown in FIG. 1 has a CPU 1 and a memory 10.
Similar to the conventional system, the present embodiment includes an access ice arbiter 6, a refresh counter 7, a RASl cis raw command section 8, and a multiplexer 9. Furthermore, as a characteristic part of this embodiment, a distributed refresh request section 2 and a refresh counter 7 are provided. , the centralized refresh request unit 5 and . It is configured to include an I/O register 4 and a refresh method selection section 5.

In addition, in FIG. 1, 11 is an I/O write signal, and 13 is an I/O write signal.
14 is a distributed refresher request signal, 14 is a concentrated refresher signal, and 15 is a refresher method selection signal.

The distributed refresh cost requesting unit 2 and the centralized reflex & requesting unit 3 in this figure are the same as the distributed refresh & requesting unit 2 in FIG.
6. 1. Distributed refresh I in this figure
The IX signal 13 and the intensive refresh request signal 14 are
In FIG. 4, it corresponds to the refresh request signal 16. In FIG. 1, a distributed refresher requesting unit 2 and a centralized reflex & requesting unit 3 each independently provide a distributed refresher &
A request signal 15 and an intensive refresh request signal 14 are output. The CPU 1 writes the refresh method selection information to the I/O register 4 using the I/Q write signal 11. The refresh Δ method selection section 5 selects one of the two refresher request signals based on the refresher method selection signal 15 and outputs it as a reflex & request signal 16 .

The other movements are the same as in Figure 4, so the redundant explanation will be omitted. It should be noted that writing to the I/Q register may be done by an interrupt program or the operating system, or by the user, depending on the presence or absence of an external interrupt.

FIG. 2 shows the configuration of another embodiment of the present invention. In this embodiment, instead of having the I/O register 4 in the embodiment shown in FIG. Control unit 23
The other precepts are the same as those shown in Figure 1.

When the communication control unit 23 receives an interrupt request from an external connection device, it sends an interrupt request signal 24 to the CPU 1.

The device detection unit 26 uses the device detection signal 25 to detect the presence or absence of connection of an external device that causes an interrupt or the like, and controls the reflex one-way selection signal 15.

FIG. 3 shows the configuration of still another embodiment of the present invention.In this embodiment, instead of having the 1/Q register in the embodiment shown in FIG. 27, and the other structure is the same as that shown in Figure 1. The power source detection unit 28 uses the power source detection signal 29 to detect whether the system power source is the dry cell battery 27 and controls the refresher a method selection signal 15. Next, the effects of each of the above embodiments will be explained collectively. Figures 8 and 9 show an example of a timing chart of the switching operation of the two fresh gourd request signals. FIG. 8 shows the switching operation from the centralized refresh method to the distributed refresh method.

The switching of the refresh method is performed as follows to satisfy the above-mentioned DRAM retaché regulations. In FIG. 8, the time rto when the intensive refresh request signal 14 is selected as the refresh request signal 16 is
When the refresh method selection signal 15 switches from low level to high level, the refresh method selection unit 5 changes the distributed refresh request signal 13 to the refresh request signal 16 instead of the concentrated refresh request signal 14.
Select as.

At this time, time T. . If the interval exceeds 1&6 μm, there will be memory cells that do not satisfy the DRAM refresh regulation after switching to the distributed refresh method. child. Tame, IJ 7lessi. Immediately after outputting the intensive refresh request signal 14 starting from time Tl1 as the refresh request signal 16, the method selection unit 5 switches to output the distributed refresh request signal 15 as the refresh request signal 16 at time mr, . Performed the action 5. FIG. 9 shows the switching operation from the distributed refresh method to the centralized refresh method.

At time 714 when the distributed refresh request signal 13 is selected as the reflex & request signal 16, when the refresh island method selection signal 15 switches from high level to low level, the centralized refresh request signal 13 replaces the distributed refresh 3-request signal 13. Signal 14 is selected as refresh request signal 16.

At this time, the previous distributed refresh island request sending time 7't
From s to T14 onwards, the intensive refresh request signal 1 is first
If the interval up to the time rta when 4 is sent out exceeds 15.6μ, after switching to the intensive refresh method, there will be memory cells that do not meet the DRAM Flexier specification. Therefore, the reflexion method selection unit 5 outputs the distributed refresh request signal 13 as the refresh request signal 16 from time 7'l4 until time Tla immediately before the first concentrated refresh request signal 14 is sent, and then outputs the distributed refresh request signal 13 as the refresh request signal 16 at time T, Reflex request signal 1
4 is output as the reflex request signal 16.

Instead of the CPU 1 in the embodiments shown in FIGS. 1, 2, and 3, other bus masters such as a DMAC (direct memory access controller) may be used. Furthermore, a plurality of refresh request sections including a distributed refresh request section 2 and a centralized reflex request section 3 are provided, and a refresh method selection section 5 selects one from a plurality of refresh S requests sent by the plurality of refresh request sections. It is also possible to have a configuration in which

Furthermore, the I/O register 4 in the embodiment shown in FIG.
Writing refresh and method selection information to cpv1
This can be done based on the results of repeated polling of externally connected devices that do not generate interrupt requests, or it can be done if keyboard input is monitored and there is no input after a certain period of time. ．． In the embodiment shown in FIG. 2, since the communication control unit 25 is essentially required to be responsive, it does not depend on the presence or absence of the interrupt request signal 24, and may be based on a polling control method. . Furthermore, the communication control unit 23 may be another unit such as a disk control unit that requires responsiveness of the CPU 1.

Further, the device detection section 26 may be configured to detect the presence or absence of an interrupt request from an externally connected device and control the reflexion method selection signal 15.

In the embodiment shown in FIG.
The essence is to detect a power source with a finite lifespan other than the C power source, and it is not only possible to detect the dry battery 27, but also to detect a rechargeable battery such as a battery, or the degree of battery consumption. ? Furthermore, the present invention may be combined as appropriate with each of the above-described embodiments and their modifications.

〔Effect of the invention〕

According to the present invention, I) in the RAM glue flexi,
Multiple glue flexure control methods can be selected to improve performance,
This enables an optimal refresh control method depending on responsiveness, power supply, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the invention, FIG. 2 is a block diagram showing another embodiment of the invention, FIG. 3 is a block diagram showing still another embodiment of the invention, and FIG. 4 is a block diagram showing another embodiment of the invention. Figure 5 is a block diagram showing the conventional technology, Figure 5 is a timing chart showing an example of the operation of the distributed refresh method, Figure 6 is a timing chart showing an example of the operation of the centralized refresh method, and Figure 7 is a page diagram of the DRAM. Timing chart showing an example of mode operation. Figure 8 is a timing chart showing an example of switching operation from centralized refresh method to distributed refresh 5 method. Figure 9 is a timing chart showing an example of switching operation from centralized refresh method to distributed refresh island method. 3 is a timing chart illustrating an example. 1 ・・・・・・・・・・・・ CPU2・・・・・・
...Distributed refresh request section 3...
...Intensive refresh request section 4...
...I/O register 5 ...... Refresh method selection section 7 ...... Refresh counter 8 ...... ...RAS/
Part 10...Memory 11...I/O write signal 13...
...Distributed reflexion request signal 14...
...Intensive refreshment 3. Request signal 15...
...Refresh 1 method selection signal 16...
Refresh request signal 23...Communication control unit 24...Interrupt request signal 25...
...Device detection signal 26...Device detection section 27...Dry battery 28...
...Power detection section 29...Power detection signal

Claims (1)

[Claims] 1. In a refresh control method in an information processing device having a CPU (central processing unit) and a memory using a dynamic RAM that requires refreshing of n addresses within a predetermined time t. , approximately 1 at time t/n
a distributed refresh control unit that sends a refresh request to the memory once every time t; a centralized refresh control unit that sends out a refresh request consecutively n times every time t; and an output from the distributed refresh control unit and the centralized refresh control unit and means for selecting each refresh request. 2. The CPU includes an I/O register in which a set value is written using an I/O write signal, and the refresh request selection means is controlled by the set value of the I/O register. A refresh control method as described in the claims. 3. It is characterized by comprising an externally connected device detection unit that detects the presence or absence of an externally connected device, and the refresh request selection means is controlled depending on the presence or absence of external device connection detected by the externally connected device detecting unit. 2. The refresh control method according to claim 1. 4. A power supply detection unit that detects the type of power supply of the system, and the refresh request selection means for the system power supply is controlled according to the type of power supply detected by the power supply detection unit. A refresh control method as described in the claims. 5. The device comprises means for detecting an interrupt request from the outside, and the refresh request selection means is controlled based on the result of the interrupt request detecting means detecting the presence or absence of an interrupt request from an externally connected device. Claim 1 characterized by
The refresh control method described.